From: "Benjamin Doron" <benjamin.doron00@gmail.com>
To: devel@edk2.groups.io
Cc: Chasel Chiu <chasel.chiu@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>,
Ankit Sinha <ankit.sinha@intel.com>,
Isaac Oram <isaac.w.oram@intel.com>,
Liming Gao <gaoliming@byosoft.com.cn>,
Eric Dong <eric.dong@intel.com>
Subject: [PATCH v1 4/5] [WIP] MinPlatformPkg: Implement S3 resume
Date: Fri, 22 Jul 2022 20:20:00 -0400 [thread overview]
Message-ID: <20220723002001.1309418-5-benjamin.doron00@gmail.com> (raw)
In-Reply-To: <20220723002001.1309418-1-benjamin.doron00@gmail.com>
Allocate memory to use on S3 resume.
TODO: Size calculation, confirm implementation goes in this module.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 133 ++++++++++++++++++++
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h | 4 +
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 6 +
Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c | 70 ++++++++++-
Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf | 2 +
Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h | 22 ++++
Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc | 4 +
Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf | 4 +
8 files changed, 244 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index c7e87cbd7d9d..1d369e7a6541 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -1424,6 +1424,135 @@ AcpiEndOfDxeEvent (
IsHardwareChange ();
}
+/**
+ Get the mem size in memory type infromation table.
+
+ @return the mem size in memory type infromation table.
+**/
+STATIC
+UINT64
+GetMemorySizeInMemoryTypeInformation (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_MEMORY_TYPE_INFORMATION *MemoryData;
+ UINT8 Index;
+ UINTN TempPageNum;
+
+ Status = EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGuid, (VOID **) &MemoryData);
+
+ if (EFI_ERROR (Status) || MemoryData == NULL) {
+ return 0;
+ }
+
+ TempPageNum = 0;
+ for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {
+ //
+ // Accumulate default memory size requirements
+ //
+ TempPageNum += MemoryData[Index].NumberOfPages;
+ }
+
+ return TempPageNum * EFI_PAGE_SIZE;
+}
+
+/**
+ Get the mem size need to be consumed and reserved for PEI phase resume.
+
+ @return the mem size to be reserved for PEI phase resume.
+**/
+STATIC
+UINT64
+GetPeiMemSize (
+ VOID
+ )
+{
+ #define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE)
+
+ UINT64 Size;
+
+ Size = GetMemorySizeInMemoryTypeInformation ();
+
+ return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE;
+}
+
+/**
+ Allocate EfiACPIMemoryNVS below 4G memory address.
+
+ This function allocates EfiACPIMemoryNVS below 4G memory address.
+
+ @param Size Size of memory to allocate.
+
+ @return Allocated address for output.
+
+**/
+VOID *
+AllocateAcpiNvsMemoryBelow4G (
+ IN UINTN Size
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ VOID *Buffer;
+
+ Pages = EFI_SIZE_TO_PAGES (Size);
+ Address = 0xffffffff;
+
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Buffer = (VOID *)(UINTN)Address;
+ ZeroMem (Buffer, Size);
+
+ return Buffer;
+}
+
+/**
+ Allocates memory to use on S3 resume
+**/
+STATIC
+VOID
+EFIAPI
+AllocateS3ResumeMemory (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT64 S3PeiMemBase;
+ UINT64 S3PeiMemSize;
+ ACPI_S3_MEMORY S3MemoryInfo;
+
+ DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));
+
+ S3PeiMemSize = GetPeiMemSize ();
+ S3PeiMemBase = (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize);
+ ASSERT (S3PeiMemBase != 0);
+
+ S3MemoryInfo.S3PeiMemBase = S3PeiMemBase;
+ S3MemoryInfo.S3PeiMemSize = S3PeiMemSize;
+
+ DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase));
+ DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize));
+
+ Status = gRT->SetVariable (
+ ACPI_S3_MEMORY_NV_NAME,
+ &gEfiAcpiVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ sizeof (S3MemoryInfo),
+ &S3MemoryInfo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));
+}
+
/**
ACPI Platform driver installation function.
@@ -1493,5 +1622,9 @@ InstallAcpiPlatform (
InstallMadtFromScratch ();
InstallMcfgFromScratch ();
+ //if (FeaturePcdGet (PcdS3FeatureEnable)) {
+ AllocateS3ResumeMemory ();
+ //}
+
return EFI_SUCCESS;
}
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
index 9bdc482f4382..381bdd25f671 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
@@ -21,8 +21,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
#include <IndustryStandard/WindowsSmmSecurityMitigationTable.h>
#include <Register/Hpet.h>
+#include <Guid/AcpiS3Context.h>
#include <Guid/EventGroup.h>
#include <Guid/GlobalVariable.h>
+#include <Guid/MemoryTypeInformation.h>
#include <Library/UefiLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UefiRuntimeServicesTableLib.h>
@@ -43,4 +45,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Register/Cpuid.h>
+#include <AcpiS3MemoryNvData.h>
+
#endif
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
index 31b6c3be3cc1..1b59427d3452 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
@@ -28,6 +28,7 @@
MdeModulePkg/MdeModulePkg.dec
UefiCpuPkg/UefiCpuPkg.dec
MinPlatformPkg/MinPlatformPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
PcAtChipsetPkg/PcAtChipsetPkg.dec
[LibraryClasses]
@@ -115,6 +116,9 @@
gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags
+ #gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize
+
[Protocols]
gEfiAcpiTableProtocolGuid ## CONSUMES
gEfiMpServiceProtocolGuid ## CONSUMES
@@ -124,6 +128,8 @@
gEfiGlobalVariableGuid ## CONSUMES
gEfiHobListGuid ## CONSUMES
gEfiEndOfDxeEventGroupGuid ## CONSUMES
+ gEfiMemoryTypeInformationGuid ## CONSUMES
+ gEfiAcpiVariableGuid ## CONSUMES
[Depex]
gEfiAcpiTableProtocolGuid AND
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
index 7ee4d3a31c49..992ec5d41bd8 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
@@ -16,14 +16,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/FspWrapperPlatformLib.h>
+#include <Guid/AcpiS3Context.h>
#include <Guid/GuidHobFspEas.h>
#include <Guid/MemoryTypeInformation.h>
#include <Guid/GraphicsInfoHob.h>
#include <Guid/PcdDataBaseHobGuid.h>
#include <Guid/ZeroGuid.h>
#include <Ppi/Capsule.h>
+#include <Ppi/ReadOnlyVariable2.h>
#include <FspEas.h>
+#include <AcpiS3MemoryNvData.h>
//
// Additional pages are used by DXE memory manager.
@@ -130,6 +133,55 @@ GetPeiMemSize (
return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE;
}
+/**
+ Get S3 PEI memory information.
+
+ @note At this point, memory is ready, and PeiServices are available to use.
+ Platform can get some data from SMRAM directly.
+
+ @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.
+ @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.
+
+ @return If S3 PEI memory information is got successfully.
+**/
+EFI_STATUS
+EFIAPI
+GetS3MemoryInfo (
+ OUT UINT64 *S3PeiMemSize,
+ OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+ UINTN DataSize;
+ ACPI_S3_MEMORY S3MemoryInfo;
+
+ *S3PeiMemBase = 0;
+ *S3PeiMemSize = 0;
+
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi);
+ ASSERT_EFI_ERROR (Status);
+
+ DataSize = sizeof (S3MemoryInfo);
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ ACPI_S3_MEMORY_NV_NAME,
+ &gEfiAcpiVariableGuid,
+ NULL,
+ &DataSize,
+ &S3MemoryInfo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *S3PeiMemBase = S3MemoryInfo.S3PeiMemBase;
+ *S3PeiMemSize = S3MemoryInfo.S3PeiMemSize;
+ return EFI_SUCCESS;
+}
+
/**
Post FSP-M HOB process for Memory Resource Descriptor.
@@ -280,7 +332,7 @@ PostFspmHobProcess (
0x1000
);
-
+ if (BootMode != BOOT_ON_S3_RESUME) {
//
// Capsule mode
//
@@ -337,7 +389,23 @@ PostFspmHobProcess (
if (Capsule != NULL) {
Status = Capsule->CreateState ((EFI_PEI_SERVICES **)PeiServices, CapsuleBuffer, CapsuleBufferLength);
}
+ } else {
+ // TODO: Must BuildResourceDescriptorHob()?
+ Status = GetS3MemoryInfo (&PeiMemSize, &PeiMemBase);
+ ASSERT_EFI_ERROR (Status);
+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemBase : 0x%08x\n", PeiMemBase));
+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemSize : 0x%08x\n", PeiMemSize));
+
+ //
+ // Install efi memory
+ //
+ Status = PeiServicesInstallPeiMemory (
+ PeiMemBase,
+ PeiMemSize
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
//
// Create a memory allocation HOB at fixed location for MP Services PPI AP wait loop.
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
index b846e7af1d2d..e2aac36bf018 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
@@ -75,7 +75,9 @@
gZeroGuid
gEfiGraphicsInfoHobGuid
gEfiGraphicsDeviceInfoHobGuid
+ gEfiAcpiVariableGuid
[Ppis]
gEfiPeiCapsulePpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
gEdkiiSiliconInitializedPpiGuid ## PRODUCES
diff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
new file mode 100644
index 000000000000..0d75af8e9a03
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for NV data structure definition.
+
+Copyright (c) 2021, Baruch Binyamin Doron
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ACPI_S3_MEMORY_NV_DATA_H__
+#define __ACPI_S3_MEMORY_NV_DATA_H__
+
+//
+// NV data structure
+//
+typedef struct {
+ UINT64 S3PeiMemBase;
+ UINT64 S3PeiMemSize;
+} ACPI_S3_MEMORY;
+
+#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo"
+
+#endif
diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
index 08e50cac075f..0eb0cc8306ee 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
@@ -41,3 +41,7 @@
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
}
!endif
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE
+ MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
+!endif
diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
index 3c2716d6728a..d8fb6683f7d4 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
@@ -6,3 +6,7 @@
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE && gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE
+ INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
+!endif
--
2.36.1
next prev parent reply other threads:[~2022-07-23 0:22 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-23 0:19 [PATCH v1 0/5] MinPlatform: Implement S3 resume feature Benjamin Doron
2022-07-23 0:19 ` [PATCH v1 1/5] IntelSiliconPkg/Feature/PeiSmmAccessLibSmramc: Implement chipset support Benjamin Doron
2022-07-23 0:19 ` [PATCH v1 2/5] Silicon/Intel: Port SMM Control protocol to PPI for S3 Benjamin Doron
2022-07-23 0:19 ` [PATCH v1 3/5] S3FeaturePkg: Implement S3 resume Benjamin Doron
2022-07-23 0:20 ` Benjamin Doron [this message]
2022-07-23 0:20 ` [PATCH v1 5/5] [WIP] KabylakeOpenBoardPkg: Example of board S3 Benjamin Doron
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