[PATCH v1 5/5] [WIP] KabylakeOpenBoardPkg: Example of board S3

["Benjamin Doron" <benjamin.doron00@gmail.com>]

Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 12 ++-
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c      | 13 ++-
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c                 | 84 +++++++++++++-------
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf                           |  4 +-
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c     | 12 ++-
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf   |  1 +
 Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc                                                                |  1 +
 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc                                                              |  1 +
 8 files changed, 97 insertions(+), 31 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index a9b7e446c8d6..7e4194bf4fe6 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,6 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/DebugLib.h>
 #include <Library/PciLib.h>
 #include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
+
 #include <FspEas.h>
 #include <FspmUpd.h>
 #include <FspsUpd.h>
@@ -32,11 +34,15 @@ PeiFspMiscUpdUpdatePreMem (
   )
 {
   EFI_STATUS                        Status;
+  EFI_BOOT_MODE                     BootMode;
   UINTN                             VariableSize;
   VOID                              *FspNvsBufferPtr;
   UINT8                             MorControl;
   VOID                              *MorControlPtr;
 
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
   //
   // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
   //
@@ -70,7 +76,11 @@ PeiFspMiscUpdUpdatePreMem (
              &VariableSize
              );
   DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
-  if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+  //
+  // Do not set CleanMemory on S3 resume
+  // TODO: Handle advanced features later - capsule update is in-memory list
+  //
+  if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) {
     FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
   }
 
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index 4621cbd3ca3a..ca91eaa8836b 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/MemoryAllocationLib.h>
 #include <Library/PeiSaPolicyLib.h>
 #include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
 
 /**
   Performs FSP SA PEI Policy initialization.
@@ -27,12 +28,17 @@ PeiFspSaPolicyUpdate (
   IN OUT FSPS_UPD    *FspsUpd
   )
 {
+  EFI_STATUS                      Status;
+  EFI_BOOT_MODE                   BootMode;
   VOID                            *Buffer;
   VOID                            *MemBuffer;
   UINT32                          Size;
 
   DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
 
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
     FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
 
     Size   = 0;
@@ -40,7 +46,12 @@ PeiFspSaPolicyUpdate (
     PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
     if (Buffer == NULL) {
       DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
-    } else {
+    //
+    // TODO: Follow coreboot and do not assign
+    //       GraphicsConfigPtr on S3 resume.
+    // - Reinitialisation is unnecessary?
+    //
+    } else if (BootMode != BOOT_ON_S3_RESUME) {
       MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
       if ((MemBuffer != NULL) && (Buffer != NULL)) {
         CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
index 487caf158fb2..bd87b1409575 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
@@ -12,9 +12,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/PcdLib.h>
 #include <Library/PchCycleDecodingLib.h>
 #include <Library/PchResetLib.h>
+#include <Library/PciLib.h>
 #include <Library/SiliconInitLib.h>
 #include <Library/TimerLib.h>
-#include <Library/PeiLib.h>
+#include <Library/PchPmcLib.h>
 
 #include <Library/GpioLib.h>
 #include <GpioPinsSklLp.h>
@@ -45,12 +46,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAspireVn7Dash572G[SA_MRC_M
 #define DGPU_HOLD_RST	GPIO_SKL_LP_GPP_B4	/* Active low */
 #define DGPU_PWR_EN	GPIO_SKL_LP_GPP_B21	/* Active low */
 
-EFI_STATUS
-EFIAPI
-AspireVn7Dash572GBoardDetect (
-  VOID
-  );
-
 /**
   Aspire VN7-572G board configuration init function for PEI pre-memory phase.
 
@@ -73,7 +68,7 @@ AspireVn7Dash572GInitPreMem (
   //
   PcdSet8S (PcdSaMiscUserBd, 5);     // ULT/ULX/Mobile Halo
   PcdSet8S (PcdMrcCaVrefConfig, 2);  // DDR4: "VREF_CA to CH_A and VREF_DQ_B to CH_B"
-  // TODO: Clear Dq/Dqs?
+  // TODO: Search vendor FW for Dq/Dqs. Unnecessary if FSP detects LPDDR
   PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE);
 
   PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorAspireVn7Dash572G);
@@ -134,7 +129,7 @@ DgpuPowerOn (
 {
   UINT32         OutputVal;
 
-  DEBUG ((DEBUG_INFO, "DgpuPowerOn() Start\n"));
+  DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));
 
   GpioGetOutputValue (DGPU_PRESENT, &OutputVal);
   if (!OutputVal) {
@@ -151,7 +146,7 @@ DgpuPowerOn (
     GpioSetOutputValue (DGPU_PWR_EN, 1);    // Deassert dGPU_PWR_EN#
   }
 
-  DEBUG ((DEBUG_INFO, "DgpuPowerOn() End\n"));
+  DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));
 }
 
 /**
@@ -225,7 +220,7 @@ AspireVn7Dash572GBoardInitAfterMemoryInit (
   VOID
   )
 {
-  EFI_STATUS  Status;
+  EFI_STATUS     Status;
 
   // BUGBUG: Workaround for a misbehaving system firmware not setting goIdle
   // - Based on prior investigation for coreboot, I suspect FSP
@@ -239,15 +234,24 @@ AspireVn7Dash572GBoardInitAfterMemoryInit (
   if (EFI_ERROR (Status)) {
     DEBUG ((DEBUG_WARN, "Failed to enable LGMR. Were ACPI tables built for LGMR memory map?\n"));
   }
+
   return EFI_SUCCESS;
 }
 
+EFI_STATUS
+EFIAPI
+AspireVn7Dash572GBoardDetect (
+  VOID
+  );
+
 EFI_STATUS
 EFIAPI
 AspireVn7Dash572GBoardDebugInit (
   VOID
   )
 {
+  UINT16  ABase;
+
   ///
   /// Do Early PCH init
   ///
@@ -258,6 +262,16 @@ AspireVn7Dash572GBoardDebugInit (
   // - Alternatively, move the preceding calls to BoardDetect()
   AspireVn7Dash572GBoardDetect ();
 
+  // Dump relevant registers
+  // - TODO: Remove after debugging
+  DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A= 0x%x\n", PciRead32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A))));
+  DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B= 0x%x\n", PciRead32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_B))));
+
+  PchAcpiBaseGet (&ABase);
+  DEBUG ((DEBUG_INFO, "ABase PM1_STS= 0x%x\n", IoRead16 (ABase)));
+  DEBUG ((DEBUG_INFO, "ABase PM1_EN= 0x%x\n", IoRead16 (ABase + R_PCH_ACPI_PM1_EN)));
+  DEBUG ((DEBUG_INFO, "ABase PM1_CNT= 0x%x\n", IoRead32 (ABase + R_PCH_ACPI_PM1_CNT)));
+
   return EFI_SUCCESS;
 }
 
@@ -267,26 +281,42 @@ AspireVn7Dash572GBoardBootModeDetect (
   VOID
   )
 {
-  UINT16         ABase;
   UINT32         SleepType;
+  EFI_BOOT_MODE  BootMode;
+  UINT16  ABase;
 
   DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
 
-  // TODO: Perform advanced detection (recovery/capsule)
-  // FIXME: This violates PI specification? But BOOT_WITH* would always take precedence
-  //        over BOOT_ON_S{4,5}...
-  // - Use PchPmcLib GetSleepTypeAfterWakeup() instead
-  PchAcpiBaseGet (&ABase);
-  SleepType = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT_SLP_TYP;
+  // Known sane defaults; TODO: Consider "default"?
+  BootMode = BOOT_WITH_FULL_CONFIGURATION;
 
-  switch (SleepType) {
-    case V_PCH_ACPI_PM1_CNT_S3:
-      return BOOT_ON_S3_RESUME;
-    case V_PCH_ACPI_PM1_CNT_S4:
-      return BOOT_ON_S4_RESUME;
-//    case V_PCH_ACPI_PM1_CNT_S5:
-//      return BOOT_ON_S5_RESUME;
-    default:
-      return BOOT_WITH_FULL_CONFIGURATION;
+  // TODO: Perform advanced detection (capsule/recovery)
+  // TODO: Perform "IsFirstBoot" test with VariablePpi for "minimal"/"assume"
+  if (GetSleepTypeAfterWakeup (&SleepType)) {
+    switch (SleepType) {
+      case V_PCH_ACPI_PM1_CNT_S3:
+        BootMode = BOOT_ON_S3_RESUME;
+        break;
+      case V_PCH_ACPI_PM1_CNT_S4:
+        BootMode = BOOT_ON_S4_RESUME;
+        break;
+      case V_PCH_ACPI_PM1_CNT_S5:
+        BootMode = BOOT_ON_S5_RESUME;
+        break;
+    }
   }
+
+  DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
+
+  // Dump relevant registers
+  // - TODO: Remove after debugging
+  DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A= 0x%x\n", PciRead32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_A))));
+  DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B= 0x%x\n", PciRead32 ((UINTN)PCI_LIB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PCH_PMC_GEN_PMCON_B))));
+
+  PchAcpiBaseGet (&ABase);
+  DEBUG ((DEBUG_INFO, "ABase PM1_STS= 0x%x\n", IoRead16 (ABase)));
+  DEBUG ((DEBUG_INFO, "ABase PM1_EN= 0x%x\n", IoRead16 (ABase + R_PCH_ACPI_PM1_EN)));
+  DEBUG ((DEBUG_INFO, "ABase PM1_CNT= 0x%x\n", IoRead32 (ABase + R_PCH_ACPI_PM1_CNT)));
+
+  return BootMode;
 }
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index 4de6b7e1721e..a3164870ef9b 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -23,11 +23,13 @@
   TimerLib
   PchCycleDecodingLib
   PchResetLib
+  PciLib
   IoLib
   EcLib
   BoardEcLib
   GpioLib
-  PeiLib
+  PeiServicesLib
+  PchPmcLib
 
 [Packages]
   MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
index 3764f7c3ac09..9c8542a29719 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
 #include <Library/DebugLib.h>
 #include <Library/ConfigBlockLib.h>
 #include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
 #include <Library/BaseMemoryLib.h>
 #include <Library/MemoryAllocationLib.h>
 #include <Library/CpuPlatformLib.h>
@@ -549,6 +550,7 @@ SiliconPolicyUpdatePostMem (
   )
 {
   EFI_STATUS                      Status;
+  EFI_BOOT_MODE                   BootMode;
   VOID                            *Buffer;
   VOID                            *MemBuffer;
   UINT32                          Size;
@@ -557,6 +559,9 @@ SiliconPolicyUpdatePostMem (
 
   DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));
 
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
   GtConfig = NULL;
   Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
   ASSERT_EFI_ERROR (Status);
@@ -571,7 +576,12 @@ SiliconPolicyUpdatePostMem (
     PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
     if (Buffer == NULL) {
       DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
-    } else {
+    //
+    // TODO: Follow coreboot and do not assign
+    //       GraphicsConfigPtr on S3 resume.
+    // - Reinitialisation is unnecessary?
+    //
+    } else if (BootMode != BOOT_ON_S3_RESUME) {
       MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
       if ((MemBuffer != NULL) && (Buffer != NULL)) {
         CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
index 1ce26fc3dcec..31a45292209d 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -23,6 +23,7 @@
   BaseMemoryLib
   MemoryAllocationLib
   PeiLib
+  PeiServicesLib
   CpuPlatformLib
   PchPcieRpLib
   PchInfoLib
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index 2e3c6d3ca506..985c1ea93660 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -108,6 +108,7 @@
   ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
   SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
   SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFsp.inf
+  IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.inf
 
   #####################################
   # Platform Package
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 26a54b0dc7cc..a2c548101ff3 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -138,6 +138,7 @@
   #######################################
   ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockLib.inf
   SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSiliconInitLib.inf
+  IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLibKbl/BaseIntelCompatShimLibKbl.inf
 
 !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
   #
-- 
2.36.1