From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qt1-f181.google.com (mail-qt1-f181.google.com [209.85.160.181]) by mx.groups.io with SMTP id smtpd.web08.1595.1658535729136005758 for ; Fri, 22 Jul 2022 17:22:11 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=cRYZVNxz; spf=pass (domain: gmail.com, ip: 209.85.160.181, mailfrom: benjamin.doron00@gmail.com) Received: by mail-qt1-f181.google.com with SMTP id g24so4656249qtu.2 for ; Fri, 22 Jul 2022 17:22:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9bwejoz/c7/4YNsicNO4HSM6nh1sia1dDTJftQku2AE=; b=cRYZVNxzsb1wLkvY5C77GPH1eoQ0uhiC1BULncgZ2cQS8gOymYA39uTnMfWz420im/ 0kES5mXmiyW7rgsL4lcCzVReEI9Sg0yHSzDdvve+yKYPNmdPpGFicdEwTOafmCYxsEid Blh5VA+XonGoOMvD40AGPTVn5YxLl7yQToI17rpZiduPHhzKc8R/kJ3TXX2edsFnKIjq D3NP2y1O8SdR8GzbTFwWvSNyKicFLtN/8rBjX721u15JX+R3EeOwDUskGY2/Tw1nOclI SD6FVqymXkH7OmEZkO+D6VRb4Kg3QatMcQLktCwAJrfqbJuAce4N/rgq5vh1HXgO54sg 917g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9bwejoz/c7/4YNsicNO4HSM6nh1sia1dDTJftQku2AE=; b=S3+bObXttMovAdWCamLPVvJeGM/pJj6pAu/XGNwyZUCPV0uytRh1/jb25+RkZtIrd/ oXaDZI1At4xblXmI7R/IeGwjwpSD9phsBu2wLTMtgbtHRWn6xS5IOMXbePgN7TSPOEih HIO8539fxhn9xKnCvAPX+HSjw8XBt8VEbhRP4Nx7JlDIzQtxY5bLuu12IeMWOXMjWa1A HphOBkeMJkRJgBZU/ia24+7+1RBzDvyMNnhgxdvkVemFgiGuu1gPbdyYTqSOcQgCP1bM 8ADO7jCpvr8mE2GF91DZw8xxK732BHlu7ZB+CLJu0tUpcuZBaWFEs6zMEM5o6/aMnA0x Lq5A== X-Gm-Message-State: AJIora9gl66W0N51g23zjkvAlAYGlLe2YX4g+Jxt7NYjDa832Az9ShAp vIZQO2LrtfbdM+w5FHwm2sSKu2xM5Y8= X-Google-Smtp-Source: AGRyM1ujzFMEQLlPPgWXqBrg0yVBM0aQ1lKT0coVBePin0JUVaMpSVf2RJczBhAKszwIgacdFDh8/w== X-Received: by 2002:ac8:5784:0:b0:31f:24e:93f5 with SMTP id v4-20020ac85784000000b0031f024e93f5mr2304665qta.429.1658535730120; Fri, 22 Jul 2022 17:22:10 -0700 (PDT) Return-Path: Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:39b7:8453:91b5:69bf]) by smtp.gmail.com with ESMTPSA id z8-20020ac84308000000b0031ee1f0c420sm3766705qtm.10.2022.07.22.17.22.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Jul 2022 17:22:09 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Subject: [PATCH v1 5/5] [WIP] KabylakeOpenBoardPkg: Example of board S3 Date: Fri, 22 Jul 2022 20:20:01 -0400 Message-Id: <20220723002001.1309418-6-benjamin.doron00@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220723002001.1309418-1-benjamin.doron00@gmail.com> References: <20220723002001.1309418-1-benjamin.doron00@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Signed-off-by: Benjamin Doron --- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 12 ++- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c | 13 ++- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiAspireVn7Dash572GInitPreMemLib.c | 84 +++++++++++++----= --- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf | 4 +- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c | 12 ++- Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 1 + Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc = | 1 + Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc = | 1 + 8 files changed, 97 insertions(+), 31 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform= /Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c index a9b7e446c8d6..7e4194bf4fe6 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,6 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D +=0D #include =0D #include =0D #include =0D @@ -32,11 +34,15 @@ PeiFspMiscUpdUpdatePreMem ( )=0D {=0D EFI_STATUS Status;=0D + EFI_BOOT_MODE BootMode;=0D UINTN VariableSize;=0D VOID *FspNvsBufferPtr;=0D UINT8 MorControl;=0D VOID *MorControlPtr;=0D =0D + Status =3D PeiServicesGetBootMode (&BootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D //=0D // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths.=0D //=0D @@ -70,7 +76,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize=0D );=0D DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));=0D - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {=0D + //=0D + // Do not set CleanMemory on S3 resume=0D + // TODO: Handle advanced features later - capsule update is in-memory li= st=0D + //=0D + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) {=0D FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK);=0D }=0D =0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Inte= l/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.c index 4621cbd3ca3a..ca91eaa8836b 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D =0D /**=0D Performs FSP SA PEI Policy initialization.=0D @@ -27,12 +28,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd=0D )=0D {=0D + EFI_STATUS Status;=0D + EFI_BOOT_MODE BootMode;=0D VOID *Buffer;=0D VOID *MemBuffer;=0D UINT32 Size;=0D =0D DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));=0D =0D + Status =3D PeiServicesGetBootMode (&BootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1;=0D =0D Size =3D 0;=0D @@ -40,7 +46,12 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size);=0D if (Buffer =3D=3D NULL) {=0D DEBUG((DEBUG_WARN, "Could not locate VBT\n"));=0D - } else {=0D + //=0D + // TODO: Follow coreboot and do not assign=0D + // GraphicsConfigPtr on S3 resume.=0D + // - Reinitialisation is unnecessary?=0D + //=0D + } else if (BootMode !=3D BOOT_ON_S3_RESUME) {=0D MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= );=0D if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {=0D CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeO= penBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInit= PreMemLib.c index 487caf158fb2..bd87b1409575 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c @@ -12,9 +12,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D -#include =0D +#include =0D =0D #include =0D #include =0D @@ -45,12 +46,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAs= pireVn7Dash572G[SA_MRC_M #define DGPU_HOLD_RST GPIO_SKL_LP_GPP_B4 /* Active low */=0D #define DGPU_PWR_EN GPIO_SKL_LP_GPP_B21 /* Active low */=0D =0D -EFI_STATUS=0D -EFIAPI=0D -AspireVn7Dash572GBoardDetect (=0D - VOID=0D - );=0D -=0D /**=0D Aspire VN7-572G board configuration init function for PEI pre-memory pha= se.=0D =0D @@ -73,7 +68,7 @@ AspireVn7Dash572GInitPreMem ( //=0D PcdSet8S (PcdSaMiscUserBd, 5); // ULT/ULX/Mobile Halo=0D PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4: "VREF_CA to CH_A and VREF_DQ= _B to CH_B"=0D - // TODO: Clear Dq/Dqs?=0D + // TODO: Search vendor FW for Dq/Dqs. Unnecessary if FSP detects LPDDR=0D PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE);=0D =0D PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorAspireVn7Dash572G);= =0D @@ -134,7 +129,7 @@ DgpuPowerOn ( {=0D UINT32 OutputVal;=0D =0D - DEBUG ((DEBUG_INFO, "DgpuPowerOn() Start\n"));=0D + DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));=0D =0D GpioGetOutputValue (DGPU_PRESENT, &OutputVal);=0D if (!OutputVal) {=0D @@ -151,7 +146,7 @@ DgpuPowerOn ( GpioSetOutputValue (DGPU_PWR_EN, 1); // Deassert dGPU_PWR_EN#=0D }=0D =0D - DEBUG ((DEBUG_INFO, "DgpuPowerOn() End\n"));=0D + DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));=0D }=0D =0D /**=0D @@ -225,7 +220,7 @@ AspireVn7Dash572GBoardInitAfterMemoryInit ( VOID=0D )=0D {=0D - EFI_STATUS Status;=0D + EFI_STATUS Status;=0D =0D // BUGBUG: Workaround for a misbehaving system firmware not setting goId= le=0D // - Based on prior investigation for coreboot, I suspect FSP=0D @@ -239,15 +234,24 @@ AspireVn7Dash572GBoardInitAfterMemoryInit ( if (EFI_ERROR (Status)) {=0D DEBUG ((DEBUG_WARN, "Failed to enable LGMR. Were ACPI tables built for= LGMR memory map?\n"));=0D }=0D +=0D return EFI_SUCCESS;=0D }=0D =0D +EFI_STATUS=0D +EFIAPI=0D +AspireVn7Dash572GBoardDetect (=0D + VOID=0D + );=0D +=0D EFI_STATUS=0D EFIAPI=0D AspireVn7Dash572GBoardDebugInit (=0D VOID=0D )=0D {=0D + UINT16 ABase;=0D +=0D ///=0D /// Do Early PCH init=0D ///=0D @@ -258,6 +262,16 @@ AspireVn7Dash572GBoardDebugInit ( // - Alternatively, move the preceding calls to BoardDetect()=0D AspireVn7Dash572GBoardDetect ();=0D =0D + // Dump relevant registers=0D + // - TODO: Remove after debugging=0D + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_A))));=0D + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_B))));=0D +=0D + PchAcpiBaseGet (&ABase);=0D + DEBUG ((DEBUG_INFO, "ABase PM1_STS=3D 0x%x\n", IoRead16 (ABase)));=0D + DEBUG ((DEBUG_INFO, "ABase PM1_EN=3D 0x%x\n", IoRead16 (ABase + R_PCH_AC= PI_PM1_EN)));=0D + DEBUG ((DEBUG_INFO, "ABase PM1_CNT=3D 0x%x\n", IoRead32 (ABase + R_PCH_A= CPI_PM1_CNT)));=0D +=0D return EFI_SUCCESS;=0D }=0D =0D @@ -267,26 +281,42 @@ AspireVn7Dash572GBoardBootModeDetect ( VOID=0D )=0D {=0D - UINT16 ABase;=0D UINT32 SleepType;=0D + EFI_BOOT_MODE BootMode;=0D + UINT16 ABase;=0D =0D DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));=0D =0D - // TODO: Perform advanced detection (recovery/capsule)=0D - // FIXME: This violates PI specification? But BOOT_WITH* would always ta= ke precedence=0D - // over BOOT_ON_S{4,5}...=0D - // - Use PchPmcLib GetSleepTypeAfterWakeup() instead=0D - PchAcpiBaseGet (&ABase);=0D - SleepType =3D IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT= _SLP_TYP;=0D + // Known sane defaults; TODO: Consider "default"?=0D + BootMode =3D BOOT_WITH_FULL_CONFIGURATION;=0D =0D - switch (SleepType) {=0D - case V_PCH_ACPI_PM1_CNT_S3:=0D - return BOOT_ON_S3_RESUME;=0D - case V_PCH_ACPI_PM1_CNT_S4:=0D - return BOOT_ON_S4_RESUME;=0D -// case V_PCH_ACPI_PM1_CNT_S5:=0D -// return BOOT_ON_S5_RESUME;=0D - default:=0D - return BOOT_WITH_FULL_CONFIGURATION;=0D + // TODO: Perform advanced detection (capsule/recovery)=0D + // TODO: Perform "IsFirstBoot" test with VariablePpi for "minimal"/"assu= me"=0D + if (GetSleepTypeAfterWakeup (&SleepType)) {=0D + switch (SleepType) {=0D + case V_PCH_ACPI_PM1_CNT_S3:=0D + BootMode =3D BOOT_ON_S3_RESUME;=0D + break;=0D + case V_PCH_ACPI_PM1_CNT_S4:=0D + BootMode =3D BOOT_ON_S4_RESUME;=0D + break;=0D + case V_PCH_ACPI_PM1_CNT_S5:=0D + BootMode =3D BOOT_ON_S5_RESUME;=0D + break;=0D + }=0D }=0D +=0D + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));=0D +=0D + // Dump relevant registers=0D + // - TODO: Remove after debugging=0D + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_A))));=0D + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_B))));=0D +=0D + PchAcpiBaseGet (&ABase);=0D + DEBUG ((DEBUG_INFO, "ABase PM1_STS=3D 0x%x\n", IoRead16 (ABase)));=0D + DEBUG ((DEBUG_INFO, "ABase PM1_EN=3D 0x%x\n", IoRead16 (ABase + R_PCH_AC= PI_PM1_EN)));=0D + DEBUG ((DEBUG_INFO, "ABase PM1_CNT=3D 0x%x\n", IoRead32 (ABase + R_PCH_A= CPI_PM1_CNT)));=0D +=0D + return BootMode;=0D }=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index 4de6b7e1721e..a3164870ef9b 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf @@ -23,11 +23,13 @@ TimerLib=0D PchCycleDecodingLib=0D PchResetLib=0D + PciLib=0D IoLib=0D EcLib=0D BoardEcLib=0D GpioLib=0D - PeiLib=0D + PeiServicesLib=0D + PchPmcLib=0D =0D [Packages]=0D MinPlatformPkg/MinPlatformPkg.dec=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUp= dateLib/PeiSiliconPolicyUpdateLib.c index 3764f7c3ac09..9c8542a29719 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D #include =0D @@ -549,6 +550,7 @@ SiliconPolicyUpdatePostMem ( )=0D {=0D EFI_STATUS Status;=0D + EFI_BOOT_MODE BootMode;=0D VOID *Buffer;=0D VOID *MemBuffer;=0D UINT32 Size;=0D @@ -557,6 +559,9 @@ SiliconPolicyUpdatePostMem ( =0D DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));=0D =0D + Status =3D PeiServicesGetBootMode (&BootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D GtConfig =3D NULL;=0D Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VO= ID *)&GtConfig);=0D ASSERT_EFI_ERROR (Status);=0D @@ -571,7 +576,12 @@ SiliconPolicyUpdatePostMem ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size);=0D if (Buffer =3D=3D NULL) {=0D DEBUG((DEBUG_WARN, "Could not locate VBT\n"));=0D - } else {=0D + //=0D + // TODO: Follow coreboot and do not assign=0D + // GraphicsConfigPtr on S3 resume.=0D + // - Reinitialisation is unnecessary?=0D + //=0D + } else if (BootMode !=3D BOOT_ON_S3_RESUME) {=0D MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= );=0D if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) {=0D CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicy= UpdateLib/PeiSiliconPolicyUpdateLib.inf index 1ce26fc3dcec..31a45292209d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -23,6 +23,7 @@ BaseMemoryLib=0D MemoryAllocationLib=0D PeiLib=0D + PeiServicesLib=0D CpuPlatformLib=0D PchPcieRpLib=0D PchInfoLib=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index 2e3c6d3ca506..985c1ea93660 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -108,6 +108,7 @@ ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf=0D SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf=0D SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf=0D + IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLib= Kbl/BaseIntelCompatShimLibKbl.inf=0D =0D #####################################=0D # Platform Package=0D diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 26a54b0dc7cc..a2c548101ff3 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -138,6 +138,7 @@ #######################################=0D ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf=0D SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf=0D + IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLib= Kbl/BaseIntelCompatShimLibKbl.inf=0D =0D !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D #=0D --=20 2.36.1