* [edk2-devel][edk2-platforms][PATCH V1 1/1] 1. Add the PCD for GPE 1 block register width control in FADT 2. Re-arrange PCD category for some PCDs
@ 2022-07-27 18:59 Sinha, Ankit
0 siblings, 0 replies; only message in thread
From: Sinha, Ankit @ 2022-07-27 18:59 UTC (permalink / raw)
To: devel; +Cc: Isaac Oram, Nate DeSimone, Eric Dong
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Ankit Sinha <ankit.sinha@intel.com>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 1 +
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 1 +
Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 9 ++++++---
3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index c7e87cbd7d9d..e68b6070607f 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -1227,6 +1227,7 @@ PlatformUpdateTables (
FadtHeader->XPmTmrBlk.AccessSize = PcdGet8 (PcdAcpiXPmTmrBlkAccessSize);
FadtHeader->XGpe0Blk.AccessSize = PcdGet8 (PcdAcpiXGpe0BlkAccessSize);
FadtHeader->XGpe1Blk.AccessSize = PcdGet8 (PcdAcpiXGpe1BlkAccessSize);
+ FadtHeader->XGpe1Blk.RegisterBitWidth = PcdGet8 (PcdAcpiXGpe1BlkRegisterBitWidth);
FadtHeader->SleepControlReg.AddressSpaceId = PcdGet8 (PcdAcpiSleepControlRegisterAddressSpaceId);
FadtHeader->SleepControlReg.RegisterBitWidth = PcdGet8 (PcdAcpiSleepControlRegisterBitWidth);
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
index 31b6c3be3cc1..1dc0683da650 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
@@ -93,6 +93,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPmTmrBlkAccessSize
gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe0BlkAccessSize
gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe1BlkAccessSize
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe1BlkRegisterBitWidth
gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegisterAddressSpaceId
gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegisterBitWidth
gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegisterBitOffset
diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
index 098bb50075d1..3a735b0e1917 100644
--- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
+++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec
@@ -134,6 +134,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdAcpiXPmTmrBlkAccessSize|0x00|UINT8|0x00010048
gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe0BlkAccessSize|0x00|UINT8|0x00010049
gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe1BlkAccessSize|0x00|UINT8|0x0001004A
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiXGpe1BlkRegisterBitWidth|0x00|UINT8|0x00010056
gMinPlatformPkgTokenSpaceGuid.PcdAcpiS4BiosReq|0x0000|UINT8|0x00010055
#
@@ -266,9 +267,6 @@
[PcdsDynamic, PcdsDynamicEx]
gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UINT32|0x90000019
- gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x90000025
- gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x90000026
- gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027
gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegisterAddressSpaceId|0x00|UINT8|0x0001004B
gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegisterBitWidth|0x00|UINT8|0x0001004C
gMinPlatformPkgTokenSpaceGuid.PcdAcpiSleepControlRegisterBitOffset|0x00|UINT8|0x0001004D
@@ -337,6 +335,11 @@
# //Header<BR>
# 0x7F, 0xFF, 0x04, 0x00}<BR>
gMinPlatformPkgTokenSpaceGuid.PcdTrustedStorageDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x17, 0x7F, 0xFF, 0x04, 0x00}|VOID*|0x3000010
+
+ ## ACPI
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x02|UINT8|0x90000025
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0001|UINT16|0x90000026
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000086A5|UINT32|0x90000027
[PcdsFixedAtBuild]
--
2.27.0.windows.1
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2022-07-27 18:59 [edk2-devel][edk2-platforms][PATCH V1 1/1] 1. Add the PCD for GPE 1 block register width control in FADT 2. Re-arrange PCD category for some PCDs Sinha, Ankit
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