From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web09.1465.1659658812988341838 for ; Thu, 04 Aug 2022 17:20:14 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=lNogtLKk; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: chasel.chiu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659658814; x=1691194814; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3DVuzTMABM2R/LBhHHcKu2ta2QrYfj009Fmpj2rQ+Zs=; b=lNogtLKk/+Z1OJQEMhKimpBYn8otWwI6BzmoFADBUapKw0crQiX9xstX A8jiOY5LyrVCDQ57+9D08uOY9jXW/JJdULhe3M4nvNn3ygu3x7j4TrTMd qOrzqyKKpGdFoMdHJ6fS8145WMTlCP+gfAG8vNqITL/O0+4C8bpkBN83L 3607FL52FY7bje+NUhplhM+LEIdM65tmv9ui8RBLuidNqr7tKmEK9lmkf ktKXY93Hvs+M4oVfQYeK/h1A4I82yTo3gh7PP116GFVQv9Veb1m/X1E7m DgYVXX71dHejQjHxu14v56SDom1vN9j/oHancYmqe5vGb/IAPXZa8+s9Q A==; X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="287647673" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="287647673" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:14 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="671497592" Received: from jwiegert-mobl1.amr.corp.intel.com (HELO cchiu4-mobl.gar.corp.intel.com) ([10.212.235.240]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:09 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [PATCH 1/4] IntelFsp2Pkg: Add FSP 2.4 MultiPhase interface. Date: Thu, 4 Aug 2022 17:19:48 -0700 Message-Id: <20220805001951.3687-2-chasel.chiu@intel.com> X-Mailer: git-send-email 2.35.0.windows.1 In-Reply-To: <20220805001951.3687-1-chasel.chiu@intel.com> References: <20220805001951.3687-1-chasel.chiu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 Provide FSP 2.4 MultiPhase interface and scripts support. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c | 176 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++ IntelFsp2Pkg/Include/FspEas/FspApi.h | 62 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- IntelFsp2Pkg/Include/FspGlobalData.h | 5 += +++- IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h | 54 += +++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/IntelFsp2Pkg.dec | 12 += +++++++++-- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 4 += +++ IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf | 50 += +++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/Tools/SplitFspBin.py | 48 += ++++++++++++++++++++++++----------------------- 8 files changed, 383 insertions(+), 28 deletions(-) diff --git a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c b= /IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c new file mode 100644 index 0000000000..728ac4c2c1 --- /dev/null +++ b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c @@ -0,0 +1,176 @@ +/** @file=0D + Null instance of Platform Sec Lib.=0D +=0D + Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +FspMultiPhaseSwitchStack (=0D + )=0D +{=0D + SetFspApiReturnStatus (EFI_SUCCESS);=0D + Pei2LoaderSwitchStack ();=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +FspVariableRequestSwitchStack (=0D + IN FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS *FspVariableRequestPara= ms=0D + )=0D +{=0D + FSP_GLOBAL_DATA *FspData;=0D +=0D + FspData =3D GetFspGlobalDataPointer ();=0D + if (((UINTN)FspData =3D=3D 0) || ((UINTN)FspData =3D=3D 0xFFFFFFFF)) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + FspData->VariableRequestParameterPtr =3D (VOID *)FspVariableRequestParam= s;=0D + SetFspApiReturnStatus (FSP_STATUS_VARIABLE_REQUEST);=0D + Pei2LoaderSwitchStack ();=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This function supports FspMultiPhase implementation.=0D +=0D + @param[in] ApiIdx Internal index of the FSP API.=0D + @param[in] ApiParam Parameter of the FSP API.=0D +=0D + @retval EFI_SUCCESS FSP execution was successful.=0D + @retval EFI_INVALID_PARAMETER Input parameters are invalid.=0D + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met.=0D + @retval EFI_DEVICE_ERROR FSP initialization failed.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +FspMultiPhaseWorker (=0D + IN UINT32 ApiIdx,=0D + IN VOID *ApiParam=0D + )=0D +{=0D + FSP_MULTI_PHASE_PARAMS *FspMultiPhaseParams;=0D + FSP_GLOBAL_DATA *FspData;=0D + FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS *FspMultiPhaseGetNumber;=0D + BOOLEAN FspDataValid;=0D +=0D + FspDataValid =3D TRUE;=0D + FspData =3D GetFspGlobalDataPointer ();=0D + if (((UINTN)FspData =3D=3D 0) || ((UINTN)FspData =3D=3D 0xFFFFFFFF)) {=0D + FspDataValid =3D FALSE;=0D + }=0D +=0D + //=0D + // It is required that FspData->NumberOfPhases to be reset to 0 after=0D + // current FSP component finished.=0D + // The next component FspData->NumberOfPhases will only be re-initialize= d when FspData->NumberOfPhases =3D 0=0D + //=0D + if ((FspDataValid =3D=3D TRUE) && (FspData->NumberOfPhases =3D=3D 0)) {= =0D + FspData->NumberOfPhases =3D PcdGet32 (PcdMultiPhaseNumberOfPhases);=0D + FspData->PhasesExecuted =3D 0;=0D + }=0D +=0D + FspMultiPhaseParams =3D (FSP_MULTI_PHASE_PARAMS *)ApiParam;=0D +=0D + if (FspDataValid =3D=3D FALSE) {=0D + return EFI_DEVICE_ERROR;=0D + } else {=0D + switch (FspMultiPhaseParams->MultiPhaseAction) {=0D + case EnumMultiPhaseGetNumberOfPhases:=0D + if ((FspMultiPhaseParams->MultiPhaseParamPtr =3D=3D NULL) || (FspM= ultiPhaseParams->PhaseIndex !=3D 0)) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + FspMultiPhaseGetNumber =3D (FSP_MULTI_PHASE_GET_NU= MBER_OF_PHASES_PARAMS *)FspMultiPhaseParams->MultiPhaseParamPtr;=0D + FspMultiPhaseGetNumber->NumberOfPhases =3D FspData->NumberOfPhases= ;=0D + FspMultiPhaseGetNumber->PhasesExecuted =3D FspData->PhasesExecuted= ;=0D + break;=0D +=0D + case EnumMultiPhaseExecutePhase:=0D + if ((FspMultiPhaseParams->PhaseIndex > FspData->PhasesExecuted) &&= (FspMultiPhaseParams->PhaseIndex <=3D FspData->NumberOfPhases)) {=0D + FspData->PhasesExecuted =3D FspMultiPhaseParams->PhaseIndex;=0D + return Loader2PeiSwitchStack ();=0D + } else {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + break;=0D +=0D + case EnumMultiPhaseGetVariableRequestInfo:=0D + //=0D + // return variable request info=0D + //=0D + FspMultiPhaseParams->MultiPhaseParamPtr =3D FspData->VariableReque= stParameterPtr;=0D + break;=0D +=0D + case EnumMultiPhaseCompleteVariableRequest:=0D + //=0D + // retrieve complete variable request params=0D + //=0D + FspData->VariableRequestParameterPtr =3D FspMultiPhaseParams->Mult= iPhaseParamPtr;=0D + return Loader2PeiSwitchStack ();=0D + break;=0D +=0D + default:=0D + return EFI_UNSUPPORTED;=0D + }=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This function handles FspMultiPhaseMemInitApi.=0D +=0D + @param[in] ApiIdx Internal index of the FSP API.=0D + @param[in] ApiParam Parameter of the FSP API.=0D +=0D + @retval EFI_SUCCESS FSP execution was successful.=0D + @retval EFI_INVALID_PARAMETER Input parameters are invalid.=0D + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met.=0D + @retval EFI_DEVICE_ERROR FSP initialization failed.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +FspMultiPhaseMemInitApiHandler (=0D + IN UINT32 ApiIdx,=0D + IN VOID *ApiParam=0D + )=0D +{=0D + return FspMultiPhaseWorker (ApiIdx, ApiParam);=0D +}=0D +=0D +/**=0D + This function handles FspMultiPhaseSiInitApi.=0D +=0D + @param[in] ApiIdx Internal index of the FSP API.=0D + @param[in] ApiParam Parameter of the FSP API.=0D +=0D + @retval EFI_SUCCESS FSP execution was successful.=0D + @retval EFI_INVALID_PARAMETER Input parameters are invalid.=0D + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met.=0D + @retval EFI_DEVICE_ERROR FSP initialization failed.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +FspMultiPhaseSiInitApiHandlerV2 (=0D + IN UINT32 ApiIdx,=0D + IN VOID *ApiParam=0D + )=0D +{=0D + return FspMultiPhaseWorker (ApiIdx, ApiParam);=0D +}=0D diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index 361e916b5f..af42d7f707 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -487,10 +487,38 @@ typedef struct { /// Action definition for FspMultiPhaseSiInit API=0D ///=0D typedef enum {=0D - EnumMultiPhaseGetNumberOfPhases =3D 0x0,=0D - EnumMultiPhaseExecutePhase =3D 0x1=0D + EnumMultiPhaseGetNumberOfPhases =3D 0x0,=0D + EnumMultiPhaseExecutePhase =3D 0x1,=0D + EnumMultiPhaseGetVariableRequestInfo =3D 0x2,=0D + EnumMultiPhaseCompleteVariableRequest =3D 0x3=0D } FSP_MULTI_PHASE_ACTION;=0D =0D +typedef enum {=0D + EnumFspVariableRequestGetVariable =3D 0x0,=0D + EnumFspVariableRequestGetNextVariableName =3D 0x1,=0D + EnumFspVariableRequestSetVariable =3D 0x2,=0D + EnumFspVariableRequestQueryVariableInfo =3D 0x3=0D +} FSP_VARIABLE_REQUEST_TYPE;=0D +=0D +#pragma pack(16)=0D +typedef struct {=0D + IN FSP_VARIABLE_REQUEST_TYPE VariableRequest;=0D + IN OUT CHAR16 *VariableName;=0D + IN OUT UINT64 *VariableNameSize;=0D + IN OUT EFI_GUID *VariableGuid;=0D + IN OUT UINT32 *Attributes;=0D + IN OUT UINT64 *DataSize;=0D + IN OUT VOID *Data;=0D + OUT UINT64 *MaximumVariableStorageSize;=0D + OUT UINT64 *RemainingVariableStorageSize;=0D + OUT UINT64 *MaximumVariableSize;=0D +} FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS;=0D +=0D +typedef struct {=0D + EFI_STATUS VariableRequestStatus;=0D +} FSP_MULTI_PHASE_COMPLETE_VARIABLE_REQUEST_PARAMS;=0D +#pragma pack()=0D +=0D ///=0D /// Data structure returned by FSP when bootloader calling=0D /// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases= )=0D @@ -690,4 +718,34 @@ EFI_STATUS IN VOID *FspiUpdDataPtr=0D );=0D =0D +/**=0D + This FSP API provides multi-phase memory and silicon initialization, whi= ch brings greater modularity to the existing=0D + FspMemoryInit() and FspSiliconInit() API. Increased modularity is achiev= ed by adding an extra API to FSP-M and FSP-S.=0D + This allows the bootloader to add board specific initialization steps th= roughout the MemoryInit and SiliconInit flows as needed.=0D + The FspMemoryInit() API is always called before FspMultiPhaseMemInit(); = it is the first phase of memory initialization. Similarly,=0D + the FspSiliconInit() API is always called before FspMultiPhaseSiInit(); = it is the first phase of silicon initialization.=0D + After the first phase, subsequent phases are invoked by calling the FspM= ultiPhaseMem/SiInit() API.=0D + The FspMultiPhaseMemInit() API may only be called after the FspMemoryIni= t() API and before the FspSiliconInit() API;=0D + or in the case that FSP-T is being used, before the TempRamExit() API. T= he FspMultiPhaseSiInit() API may only be called after=0D + the FspSiliconInit() API and before NotifyPhase() API; or in the case th= at FSP-I is being used, before the FspSmmInit() API.=0D + The multi-phase APIs may not be called at any other time.=0D +=0D + @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNu= mberOfPhases:=0D + FSP_MULTI_PHASE_PARAMS->MultiP= haseParamPtr will contain=0D + how many phases supported by F= SP.=0D + For action - EnumMultiPhaseExecu= tePhase:=0D + FSP_MULTI_PHASE_PARAMS->MultiP= haseParamPtr shall be NULL.=0D + @retval EFI_SUCCESS FSP execution environment was in= itialized successfully.=0D + @retval EFI_INVALID_PARAMETER Input parameters are invalid.=0D + @retval EFI_UNSUPPORTED The FSP calling conditions were = not met.=0D + @retval EFI_DEVICE_ERROR FSP initialization failed.=0D + @retval FSP_STATUS_RESET_REQUIRED_* A reset is required. These statu= s codes will not be returned during S3.=0D + @retval FSP_STATUS_VARIABLE_REQUEST A variable request has been made= by FSP that needs boot loader handling.=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *FSP_MULTI_PHASE_INIT)(=0D + IN FSP_MULTI_PHASE_PARAMS *MultiPhaseInitParamPtr=0D + );=0D +=0D #endif=0D diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/Fs= pGlobalData.h index 32c6d460e4..81813df3ce 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -12,7 +12,7 @@ =0D #define FSP_IN_API_MODE 0=0D #define FSP_IN_DISPATCH_MODE 1=0D -#define FSP_GLOBAL_DATA_VERSION 0x2=0D +#define FSP_GLOBAL_DATA_VERSION 0x3=0D =0D #pragma pack(1)=0D =0D @@ -25,6 +25,7 @@ typedef enum { FspSiliconInitApiIndex,=0D FspMultiPhaseSiInitApiIndex,=0D FspSmmInitApiIndex,=0D + FspMultiPhaseMemInitApiIndex,=0D FspApiIndexMax=0D } FSP_API_INDEX;=0D =0D @@ -82,6 +83,8 @@ typedef struct { VOID *FunctionParameterPtr;=0D FSP_INFO_HEADER *FspInfoHeader;=0D VOID *UpdDataPtr;=0D + VOID *FspHobListPtr;=0D + VOID *VariableRequestParameterPtr;=0D ///=0D /// End of UINTN and pointer section=0D /// At this point, next field offset must be either *0h or *8h to=0D diff --git a/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h b/IntelFsp2Pkg= /Include/Library/FspMultiPhaseLib.h new file mode 100644 index 0000000000..7ac4e197d9 --- /dev/null +++ b/IntelFsp2Pkg/Include/Library/FspMultiPhaseLib.h @@ -0,0 +1,54 @@ +/** @file=0D +=0D + Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef _FSP_SEC_PLATFORM_LIB_H_=0D +#define _FSP_SEC_PLATFORM_LIB_H_=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +FspMultiPhaseSwitchStack (=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +FspVariableRequestSwitchStack (=0D + IN FSP_MULTI_PHASE_VARIABLE_REQUEST_INFO_PARAMS *FspVariableRequestPara= ms=0D + );=0D +=0D +/**=0D + This function handles FspMultiPhaseMemInitApi.=0D +=0D + @param[in] ApiIdx Internal index of the FSP API.=0D + @param[in] ApiParam Parameter of the FSP API.=0D +=0D + @retval EFI_SUCCESS FSP execution was successful.=0D + @retval EFI_INVALID_PARAMETER Input parameters are invalid.=0D + @retval EFI_UNSUPPORTED The FSP calling conditions were not = met.=0D + @retval EFI_DEVICE_ERROR FSP initialization failed.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +FspMultiPhaseMemInitApiHandler (=0D + IN UINT32 ApiIdx,=0D + IN VOID *ApiParam=0D + );=0D +=0D +/**=0D + This function handles FspMultiPhaseSiInitApi.=0D +=0D + @param[in] ApiIdx Internal index of the FSP API.=0D + @param[in] ApiParam Parameter of the FSP API.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +FspMultiPhaseSiInitApiHandlerV2 (=0D + IN UINT32 ApiIdx,=0D + IN VOID *ApiParam=0D + );=0D +=0D +#endif=0D diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dec b/IntelFsp2Pkg/IntelFsp2Pkg.dec index 2d3eb708b9..d1c3d3ee7b 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dec +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dec @@ -37,6 +37,9 @@ ## @libraryclass Provides FSP platform sec related actions.=0D FspSecPlatformLib|Include/Library/FspSecPlatformLib.h=0D =0D + ## @libraryclass Provides FSP MultiPhase service functions.=0D + FspMultiPhaseLib|Include/Library/FspMultiPhaseLib.h=0D +=0D [Ppis]=0D #=0D # PPI to indicate FSP is ready to enter notify phase=0D @@ -112,5 +115,10 @@ gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize |0x00000000|UI= NT32|0x10000006=0D =0D [PcdsFixedAtBuild,PcdsDynamic,PcdsDynamicEx]=0D - gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT3= 2|0x46530000=0D - gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT3= 2|0x46530100=0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedMemoryLength |0x00100000|UINT= 32|0x46530000=0D + gIntelFsp2PkgTokenSpaceGuid.PcdBootLoaderEntry |0xFFFFFFE4|UINT= 32|0x46530100=0D + #=0D + # Different FSP Components may have different NumberOfPhases which can b= e defined=0D + # by each FspSecCore module from DSC.=0D + #=0D + gIntelFsp2PkgTokenSpaceGuid.PcdMultiPhaseNumberOfPhases |0x00000000|UINT= 32|0x46530101=0D diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index b2d7867880..0713f0028d 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -45,6 +45,7 @@ FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLi= b.inf=0D FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwit= chStackLib.inf=0D FspSecPlatformLib|IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSe= cPlatformLibNull.inf=0D + FspMultiPhaseLib|IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiP= haseLib.inf=0D =0D [LibraryClasses.common.PEIM]=0D PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D @@ -64,12 +65,15 @@ IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf=0D IntelFsp2Pkg/Library/BaseDebugDeviceLibNull/BaseDebugDeviceLibNull.inf=0D IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.i= nf=0D + IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf=0D =0D IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf=0D IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf=0D + IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf=0D IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf=0D IntelFsp2Pkg/FspSecCore/FspSecCoreI.inf=0D IntelFsp2Pkg/FspSecCore/Fsp22SecCoreS.inf=0D + IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf=0D IntelFsp2Pkg/FspNotifyPhase/FspNotifyPhasePeim.inf=0D =0D [PcdsFixedAtBuild.common]=0D diff --git a/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib= .inf b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf new file mode 100644 index 0000000000..a79f6aecda --- /dev/null +++ b/IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf @@ -0,0 +1,50 @@ +## @file=0D +# FSP MultiPhase Lib.=0D +#=0D +# Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Defines Section - statements that will be processed to create a Makefile= .=0D +#=0D +##########################################################################= ######=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D BaseFspMultiPhaseLib=0D + FILE_GUID =3D C128CADC-623E-4E41-97CB-A7138E627460= =0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D FspMultiPhaseLib=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +##########################################################################= ######=0D +#=0D +# Sources Section - list of files that are required for the build to succe= ed.=0D +#=0D +##########################################################################= ######=0D +=0D +[Sources]=0D + FspMultiPhaseLib.c=0D +=0D +##########################################################################= ######=0D +#=0D +# Package Dependency Section - list of Package files that are required for= =0D +# this module.=0D +#=0D +##########################################################################= ######=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + IntelFsp2Pkg/IntelFsp2Pkg.dec=0D +=0D +[Pcd]=0D + gIntelFsp2PkgTokenSpaceGuid.PcdMultiPhaseNumberOfPhases # CONSUMES=0D diff --git a/IntelFsp2Pkg/Tools/SplitFspBin.py b/IntelFsp2Pkg/Tools/SplitFs= pBin.py index ddabab7d8c..419e5ba985 100644 --- a/IntelFsp2Pkg/Tools/SplitFspBin.py +++ b/IntelFsp2Pkg/Tools/SplitFspBin.py @@ -103,29 +103,31 @@ class FSP_COMMON_HEADER(Structure): =0D class FSP_INFORMATION_HEADER(Structure):=0D _fields_ =3D [=0D - ('Signature', ARRAY(c_char, 4)),=0D - ('HeaderLength', c_uint32),=0D - ('Reserved1', c_uint16),=0D - ('SpecVersion', c_uint8),=0D - ('HeaderRevision', c_uint8),=0D - ('ImageRevision', c_uint32),=0D - ('ImageId', ARRAY(c_char, 8)),=0D - ('ImageSize', c_uint32),=0D - ('ImageBase', c_uint32),=0D - ('ImageAttribute', c_uint16),=0D - ('ComponentAttribute', c_uint16),=0D - ('CfgRegionOffset', c_uint32),=0D - ('CfgRegionSize', c_uint32),=0D - ('Reserved2', c_uint32),=0D - ('TempRamInitEntryOffset', c_uint32),=0D - ('Reserved3', c_uint32),=0D - ('NotifyPhaseEntryOffset', c_uint32),=0D - ('FspMemoryInitEntryOffset', c_uint32),=0D - ('TempRamExitEntryOffset', c_uint32),=0D - ('FspSiliconInitEntryOffset', c_uint32),=0D - ('FspMultiPhaseSiInitEntryOffset', c_uint32),=0D - ('ExtendedImageRevision', c_uint16),=0D - ('Reserved4', c_uint16)=0D + ('Signature', ARRAY(c_char, 4)),=0D + ('HeaderLength', c_uint32),=0D + ('Reserved1', c_uint16),=0D + ('SpecVersion', c_uint8),=0D + ('HeaderRevision', c_uint8),=0D + ('ImageRevision', c_uint32),=0D + ('ImageId', ARRAY(c_char, 8)),=0D + ('ImageSize', c_uint32),=0D + ('ImageBase', c_uint32),=0D + ('ImageAttribute', c_uint16),=0D + ('ComponentAttribute', c_uint16),=0D + ('CfgRegionOffset', c_uint32),=0D + ('CfgRegionSize', c_uint32),=0D + ('Reserved2', c_uint32),=0D + ('TempRamInitEntryOffset', c_uint32),=0D + ('Reserved3', c_uint32),=0D + ('NotifyPhaseEntryOffset', c_uint32),=0D + ('FspMemoryInitEntryOffset', c_uint32),=0D + ('TempRamExitEntryOffset', c_uint32),=0D + ('FspSiliconInitEntryOffset', c_uint32),=0D + ('FspMultiPhaseSiInitEntryOffset', c_uint32),=0D + ('ExtendedImageRevision', c_uint16),=0D + ('Reserved4', c_uint16),=0D + ('FspMultiPhaseMemInitEntryOffset', c_uint32),=0D + ('FspSmmInitEntryOffset', c_uint32)=0D ]=0D =0D class FSP_PATCH_TABLE(Structure):=0D --=20 2.35.0.windows.1