From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web11.1516.1659658815265618110 for ; Thu, 04 Aug 2022 17:20:16 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=JojkeIOX; spf=pass (domain: intel.com, ip: 192.55.52.93, mailfrom: chasel.chiu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659658815; x=1691194815; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dNAhJkYz1amZGdYKQ64+ddRiFmZ+wdgGUhTjNz7z+f4=; b=JojkeIOXPBdhxNsCPJr0hSxROIT6bdWCg1iPgPcbnEN7MlGlM8QPpwO3 D75lC1rgx3U7eaDt1IUxJ4RNbPXoeRHtbX5v0eibu2qmnE6A8jVaI1OF7 3PJQGN19xFa369HhRh6RiYWkDe4lHgJD0IOGGVew2YwdPleK2gaiopFlk IPVlzTKM6rDyXARUM3zH/E5GpyclBh9szTXafm8PrleN4xRrA9GUMx+WQ 4ctgKrXuXSCvlgNYZPFLEen7tUuwUiwgLVP/luDiDQ9MCWwFrsa3AgggN yzhyJvDow1+ZeQiQh3XfF2WSv38FA8SyeHEtwbWq52wIhiYugtUaRTfhN Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="287647680" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="287647680" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:15 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="671497603" Received: from jwiegert-mobl1.amr.corp.intel.com (HELO cchiu4-mobl.gar.corp.intel.com) ([10.212.235.240]) by fmsmga004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 17:20:12 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [PATCH 4/4] IntelFsp2WrapperPkg: Implement FSP 2.4 MultiPhase wrapper handlers. Date: Thu, 4 Aug 2022 17:19:51 -0700 Message-Id: <20220805001951.3687-5-chasel.chiu@intel.com> X-Mailer: git-send-email 2.35.0.windows.1 In-Reply-To: <20220805001951.3687-1-chasel.chiu@intel.com> References: <20220805001951.3687-1-chasel.chiu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 Implement MultiPhase wrapper handlers and only call to MultiPhase handlers when FSP supports. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c | 33 +++++++++++++= ++++++++++++-------- IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c | 27 +++++++++++++= ++++++++------ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf | 1 + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf | 3 ++- 4 files changed, 49 insertions(+), 15 deletions(-) diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c b/IntelF= sp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c index ac27524d08..ea206a7960 100644 --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.c @@ -23,6 +23,7 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D =0D @@ -35,6 +36,8 @@ #include =0D #include =0D #include =0D +#include =0D +#include =0D =0D extern EFI_GUID gFspHobGuid;=0D =0D @@ -119,25 +122,39 @@ PeiFspMemoryInit ( =0D TimeStampCounterStart =3D AsmReadTsc ();=0D Status =3D CallFspMemoryInit (FspmUpdDataPtr, &FspHobList= Ptr);=0D - // Create hobs after memory initialization and not in temp RAM. Hence pa= ssing the recorded timestamp here=0D - PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, TimeStampCount= erStart, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_ST= ATUS_CODE_API_ENTRY);=0D - PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);=0D - DEBUG ((DEBUG_INFO, "Total time spent executing FspMemoryInitApi: %d mil= lisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCount= erStart), 1000000)));=0D =0D //=0D // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status= =0D //=0D if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) {=0D - DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset 0x%x\n", Status)= );=0D + DEBUG ((DEBUG_INFO, "FspMemoryInitApi requested reset %r\n", Status));= =0D CallFspWrapperResetSystem (Status);=0D }=0D =0D - if (EFI_ERROR (Status)) {=0D + if ((Status !=3D FSP_STATUS_VARIABLE_REQUEST) && EFI_ERROR (Status)) {=0D DEBUG ((DEBUG_ERROR, "ERROR - Failed to execute FspMemoryInitApi(), St= atus =3D %r\n", Status));=0D + ASSERT_EFI_ERROR (Status);=0D }=0D =0D - DEBUG ((DEBUG_INFO, "FspMemoryInit status: 0x%x\n", Status));=0D - ASSERT_EFI_ERROR (Status);=0D + DEBUG ((DEBUG_INFO, "FspMemoryInit status: %r\n", Status));=0D + if (Status =3D=3D FSP_STATUS_VARIABLE_REQUEST) {=0D + //=0D + // call to Variable request handler=0D + //=0D + FspWrapperVariableRequestHandler (&FspHobListPtr, FspMultiPhaseMemInit= ApiIndex);=0D + }=0D +=0D + //=0D + // See if MultiPhase process is required or not=0D + //=0D + FspWrapperMultiPhaseHandler (&FspHobListPtr, FspMultiPhaseMemInitApiInde= x); // FspM MultiPhase=0D +=0D + //=0D + // Create hobs after memory initialization and not in temp RAM. Hence pa= ssing the recorded timestamp here=0D + //=0D + PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, TimeStampCount= erStart, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_ST= ATUS_CODE_API_ENTRY);=0D + PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);=0D + DEBUG ((DEBUG_INFO, "Total time spent executing FspMemoryInitApi: %d mil= lisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCount= erStart), 1000000)));=0D =0D Status =3D TestFspMemoryInitApiOutput (FspmUpdDataPtr, &FspHobListPtr);= =0D if (EFI_ERROR (Status)) {=0D diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c b/IntelF= sp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c index ee48dd69d3..a41c809c62 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.c @@ -21,6 +21,7 @@ #include =0D #include =0D #include =0D +#include =0D #include =0D #include =0D #include =0D @@ -36,6 +37,7 @@ #include =0D #include =0D #include =0D +#include =0D =0D extern EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc;=0D extern EFI_GUID gFspHobGuid;=0D @@ -318,23 +320,36 @@ PeiMemoryDiscoveredNotify ( TimeStampCounterStart =3D AsmReadTsc ();=0D PERF_START_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_= CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY= );=0D Status =3D CallFspSiliconInit ((VOID *)FspsUpdDataPtr);=0D - PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);= =0D - DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d mi= llisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCoun= terStart), 1000000)));=0D =0D //=0D // Reset the system if FSP API returned FSP_STATUS_RESET_REQUIRED status= =0D //=0D if ((Status >=3D FSP_STATUS_RESET_REQUIRED_COLD) && (Status <=3D FSP_STA= TUS_RESET_REQUIRED_8)) {=0D - DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset 0x%x\n", Status= ));=0D + DEBUG ((DEBUG_INFO, "FspSiliconInitApi requested reset %r\n", Status))= ;=0D CallFspWrapperResetSystem (Status);=0D }=0D =0D - if (EFI_ERROR (Status)) {=0D + if ((Status !=3D FSP_STATUS_VARIABLE_REQUEST) && EFI_ERROR (Status)) {=0D DEBUG ((DEBUG_ERROR, "ERROR - Failed to execute FspSiliconInitApi(), S= tatus =3D %r\n", Status));=0D + ASSERT_EFI_ERROR (Status);=0D }=0D =0D - DEBUG ((DEBUG_INFO, "FspSiliconInit status: 0x%x\n", Status));=0D - ASSERT_EFI_ERROR (Status);=0D + DEBUG ((DEBUG_INFO, "FspSiliconInit status: %r\n", Status));=0D +=0D + if (Status =3D=3D FSP_STATUS_VARIABLE_REQUEST) {=0D + //=0D + // call to Variable request handler=0D + //=0D + FspWrapperVariableRequestHandler (&FspHobListPtr, FspMultiPhaseMemInit= ApiIndex);=0D + }=0D +=0D + //=0D + // See if MultiPhase process is required or not=0D + //=0D + FspWrapperMultiPhaseHandler (&FspHobListPtr, FspMultiPhaseSiInitApiIndex= ); // FspS MultiPhase=0D +=0D + PERF_END_EX (&gFspApiPerformanceGuid, "EventRec", NULL, 0, FSP_STATUS_CO= DE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);= =0D + DEBUG ((DEBUG_INFO, "Total time spent executing FspSiliconInitApi: %d mi= llisecond\n", DivU64x32 (GetTimeInNanoSecond (AsmReadTsc () - TimeStampCoun= terStart), 1000000)));=0D =0D Status =3D TestFspSiliconInitApiOutput ((VOID *)NULL);=0D if (RETURN_ERROR (Status)) {=0D diff --git a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf b/Inte= lFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf index e2262d693c..332509e0bc 100644 --- a/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +++ b/IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf @@ -46,6 +46,7 @@ FspWrapperApiLib=0D FspWrapperApiTestLib=0D FspMeasurementLib=0D + FspWrapperMultiPhaseProcessLib=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D diff --git a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf b/Inte= lFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf index 0598f85ab3..f9c2ffca1c 100644 --- a/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +++ b/IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf @@ -6,7 +6,7 @@ # register TemporaryRamDonePpi to call TempRamExit API, and register Memor= yDiscoveredPpi=0D # notify to call FspSiliconInit API.=0D #=0D -# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
= =0D +# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -46,6 +46,7 @@ FspWrapperApiLib=0D FspWrapperApiTestLib=0D FspMeasurementLib=0D + FspWrapperMultiPhaseProcessLib=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D --=20 2.35.0.windows.1