From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web08.4050.1659681568025593867 for ; Thu, 04 Aug 2022 23:39:35 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=HSZOVKSA; spf=pass (domain: intel.com, ip: 134.134.136.126, mailfrom: zhiguang.liu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659681575; x=1691217575; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AjoeqnAyDNQZvPDIFChGvO7fxqKGle0+2cQk5w57c4s=; b=HSZOVKSAf17m9bTs0JQCik8yWyhsGAJlNTZRq7KOeo84MseamJQXAMAq A5ScMn17dg7BgmGNMVS63ZXjjPpDPQSnohSdHbyMw7CxQ5CdCI3nUqzEA pMvmKbAyMn5UUsIgKdEaYFvlZqzZFFUCMBBLm4cCjU3sWb1kaD0lh3NVt 4YFqGW/bnneIZvDA56G0XSuCSOFk3xDriJx/Rn83iK3TFH7mfgnieq2WF XfImW1Rez1wzLs45phHDyNpzEg7onKUU777AibT42aLqTnq9IfoDwOEHj lHnEFzxcU2mquMlofUQ5VF2ay5RulqGe3ySY5xlptKIMMiG6jpgjzmiK+ g==; X-IronPort-AV: E=McAfee;i="6400,9594,10429"; a="273180965" X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="273180965" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:35 -0700 X-IronPort-AV: E=Sophos;i="5.93,216,1654585200"; d="scan'208";a="554011619" Received: from shwdesfp01.ccr.corp.intel.com ([10.239.158.151]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Aug 2022 23:39:33 -0700 From: "Zhiguang Liu" To: devel@edk2.groups.io Cc: Zhiguang Liu , Eric Dong , Ray Ni , Rahul Kumar Subject: [PATCH v2 3/3] UefiCpuPkg: Simplify the struct definition of CPU_EXCEPTION_INIT_DATA Date: Fri, 5 Aug 2022 14:39:12 +0800 Message-Id: <20220805063912.1347-4-zhiguang.liu@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20220805063912.1347-1-zhiguang.liu@intel.com> References: <20220805063912.1347-1-zhiguang.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit CPU_EXCEPTION_INIT_DATA is now an internal implementation of CpuExceptionHandlerLib. Union can be removed since Ia32 and X64 have the same definition Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Zhiguang Liu --- .../CpuExceptionCommon.h | 108 +++++++++--------- .../CpuExceptionHandlerLib/DxeException.c | 24 ++-- .../Ia32/ArchExceptionHandler.c | 68 +++++------ .../CpuExceptionHandlerLib/PeiCpuException.c | 24 ++-- .../X64/ArchExceptionHandler.c | 64 +++++------ 5 files changed, 143 insertions(+), 145 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 67d81d50d2..11a5624f51 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -49,61 +49,59 @@ #define CPU_TSS_GDT_SIZE (SIZE_2KB + CPU_TSS_DESC_SIZE + CPU_TSS_SIZE) -typedef union { - struct { - // - // The address of top of known good stack reserved for *ALL* exceptions - // listed in field StackSwitchExceptions. - // - UINTN KnownGoodStackTop; - // - // The size of known good stack for *ONE* exception only. - // - UINTN KnownGoodStackSize; - // - // Buffer of exception vector list for stack switch. - // - UINT8 *StackSwitchExceptions; - // - // Number of exception vectors in StackSwitchExceptions. - // - UINTN StackSwitchExceptionNumber; - // - // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. - // Normally there's no need to change IDT table size. - // - VOID *IdtTable; - // - // Size of buffer for IdtTable. - // - UINTN IdtTableSize; - // - // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. - // - VOID *GdtTable; - // - // Size of buffer for GdtTable. - // - UINTN GdtTableSize; - // - // Pointer to start address of descriptor of exception task gate in the - // GDT table. It must be type of IA32_TSS_DESCRIPTOR. - // - VOID *ExceptionTssDesc; - // - // Size of buffer for ExceptionTssDesc. - // - UINTN ExceptionTssDescSize; - // - // Buffer of task-state segment for exceptions. It must be type of - // IA32_TASK_STATE_SEGMENT. - // - VOID *ExceptionTss; - // - // Size of buffer for ExceptionTss. - // - UINTN ExceptionTssSize; - } Ia32, X64; +typedef struct { + // + // The address of top of known good stack reserved for *ALL* exceptions + // listed in field StackSwitchExceptions. + // + UINTN KnownGoodStackTop; + // + // The size of known good stack for *ONE* exception only. + // + UINTN KnownGoodStackSize; + // + // Buffer of exception vector list for stack switch. + // + UINT8 *StackSwitchExceptions; + // + // Number of exception vectors in StackSwitchExceptions. + // + UINTN StackSwitchExceptionNumber; + // + // Buffer of IDT table. It must be type of IA32_IDT_GATE_DESCRIPTOR. + // Normally there's no need to change IDT table size. + // + VOID *IdtTable; + // + // Size of buffer for IdtTable. + // + UINTN IdtTableSize; + // + // Buffer of GDT table. It must be type of IA32_SEGMENT_DESCRIPTOR. + // + VOID *GdtTable; + // + // Size of buffer for GdtTable. + // + UINTN GdtTableSize; + // + // Pointer to start address of descriptor of exception task gate in the + // GDT table. It must be type of IA32_TSS_DESCRIPTOR. + // + VOID *ExceptionTssDesc; + // + // Size of buffer for ExceptionTssDesc. + // + UINTN ExceptionTssDescSize; + // + // Buffer of task-state segment for exceptions. It must be type of + // IA32_TASK_STATE_SEGMENT. + // + VOID *ExceptionTss; + // + // Size of buffer for ExceptionTss. + // + UINTN ExceptionTssSize; } CPU_EXCEPTION_INIT_DATA; // diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c index 674029f8ac..d90c607bd7 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c @@ -190,18 +190,18 @@ InitializeSeparateExceptionStacks ( } AsmReadIdtr (&Idtr); - EssData.X64.KnownGoodStackTop = StackTop; - EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST; - EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER; - EssData.X64.IdtTable = (VOID *)Idtr.Base; - EssData.X64.IdtTableSize = Idtr.Limit + 1; - EssData.X64.GdtTable = NewGdtTable; - EssData.X64.GdtTableSize = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDesc = NewGdtTable + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize = CPU_TSS_SIZE; + EssData.KnownGoodStackTop = StackTop; + EssData.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE; + EssData.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST; + EssData.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER; + EssData.IdtTable = (VOID *)Idtr.Base; + EssData.IdtTableSize = Idtr.Limit + 1; + EssData.GdtTable = NewGdtTable; + EssData.GdtTableSize = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1; + EssData.ExceptionTssDesc = NewGdtTable + Gdtr.Limit + 1; + EssData.ExceptionTssDescSize = CPU_TSS_DESC_SIZE; + EssData.ExceptionTss = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE; + EssData.ExceptionTssSize = CPU_TSS_SIZE; return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c index fa62074023..194d3a499b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c @@ -132,15 +132,15 @@ ArchSetupExceptionStack ( EXCEPTION_HANDLER_TEMPLATE_MAP TemplateMap; if ((StackSwitchData == NULL) || - (StackSwitchData->Ia32.KnownGoodStackTop == 0) || - (StackSwitchData->Ia32.KnownGoodStackSize == 0) || - (StackSwitchData->Ia32.StackSwitchExceptions == NULL) || - (StackSwitchData->Ia32.StackSwitchExceptionNumber == 0) || - (StackSwitchData->Ia32.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || - (StackSwitchData->Ia32.GdtTable == NULL) || - (StackSwitchData->Ia32.IdtTable == NULL) || - (StackSwitchData->Ia32.ExceptionTssDesc == NULL) || - (StackSwitchData->Ia32.ExceptionTss == NULL)) + (StackSwitchData->KnownGoodStackTop == 0) || + (StackSwitchData->KnownGoodStackSize == 0) || + (StackSwitchData->StackSwitchExceptions == NULL) || + (StackSwitchData->StackSwitchExceptionNumber == 0) || + (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->GdtTable == NULL) || + (StackSwitchData->IdtTable == NULL) || + (StackSwitchData->ExceptionTssDesc == NULL) || + (StackSwitchData->ExceptionTss == NULL)) { return EFI_INVALID_PARAMETER; } @@ -150,16 +150,16 @@ ArchSetupExceptionStack ( // one or newly allocated, has enough space to hold descriptors for exception // task-state segments. // - if (((UINTN)StackSwitchData->Ia32.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) { + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) { return EFI_INVALID_PARAMETER; } - if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc < (UINTN)(StackSwitchData->Ia32.GdtTable)) { + if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->GdtTable)) { return EFI_INVALID_PARAMETER; } - if ((UINTN)StackSwitchData->Ia32.ExceptionTssDesc + StackSwitchData->Ia32.ExceptionTssDescSize > - ((UINTN)(StackSwitchData->Ia32.GdtTable) + StackSwitchData->Ia32.GdtTableSize)) + if ((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->ExceptionTssDescSize > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize)) { return EFI_INVALID_PARAMETER; } @@ -168,20 +168,20 @@ ArchSetupExceptionStack ( // We need one descriptor and one TSS for current task and every exception // specified. // - if (StackSwitchData->Ia32.ExceptionTssDescSize < - sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) + if (StackSwitchData->ExceptionTssDescSize < + sizeof (IA32_TSS_DESCRIPTOR) * (StackSwitchData->StackSwitchExceptionNumber + 1)) { return EFI_INVALID_PARAMETER; } - if (StackSwitchData->Ia32.ExceptionTssSize < - sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1)) + if (StackSwitchData->ExceptionTssSize < + sizeof (IA32_TASK_STATE_SEGMENT) * (StackSwitchData->StackSwitchExceptionNumber + 1)) { return EFI_INVALID_PARAMETER; } - TssDesc = StackSwitchData->Ia32.ExceptionTssDesc; - Tss = StackSwitchData->Ia32.ExceptionTss; + TssDesc = StackSwitchData->ExceptionTssDesc; + Tss = StackSwitchData->ExceptionTss; // // Initialize new GDT table and/or IDT table, if any @@ -191,20 +191,20 @@ ArchSetupExceptionStack ( GdtSize = (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) * - (StackSwitchData->Ia32.StackSwitchExceptionNumber + 1) - - (UINTN)(StackSwitchData->Ia32.GdtTable); - if ((UINTN)StackSwitchData->Ia32.GdtTable != Gdtr.Base) { - CopyMem (StackSwitchData->Ia32.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); - Gdtr.Base = (UINTN)StackSwitchData->Ia32.GdtTable; + (StackSwitchData->StackSwitchExceptionNumber + 1) - + (UINTN)(StackSwitchData->GdtTable); + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base = (UINTN)StackSwitchData->GdtTable; Gdtr.Limit = (UINT16)GdtSize - 1; } - if ((UINTN)StackSwitchData->Ia32.IdtTable != Idtr.Base) { - Idtr.Base = (UINTN)StackSwitchData->Ia32.IdtTable; + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) { + Idtr.Base = (UINTN)StackSwitchData->IdtTable; } - if (StackSwitchData->Ia32.IdtTableSize > 0) { - Idtr.Limit = (UINT16)(StackSwitchData->Ia32.IdtTableSize - 1); + if (StackSwitchData->IdtTableSize > 0) { + Idtr.Limit = (UINT16)(StackSwitchData->IdtTableSize - 1); } // @@ -226,10 +226,10 @@ ArchSetupExceptionStack ( // Fixup exception task descriptor and task-state segment // AsmGetTssTemplateMap (&TemplateMap); - StackTop = StackSwitchData->Ia32.KnownGoodStackTop - CPU_STACK_ALIGNMENT; + StackTop = StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT; StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); - IdtTable = StackSwitchData->Ia32.IdtTable; - for (Index = 0; Index < StackSwitchData->Ia32.StackSwitchExceptionNumber; ++Index) { + IdtTable = StackSwitchData->IdtTable; + for (Index = 0; Index < StackSwitchData->StackSwitchExceptionNumber; ++Index) { TssDesc += 1; Tss += 1; @@ -250,7 +250,7 @@ ArchSetupExceptionStack ( // // Fixup TSS // - Vector = StackSwitchData->Ia32.StackSwitchExceptions[Index]; + Vector = StackSwitchData->StackSwitchExceptions[Index]; if ((Vector >= CPU_EXCEPTION_NUM) || (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) { @@ -270,7 +270,7 @@ ArchSetupExceptionStack ( Tss->FS = AsmReadFs (); Tss->GS = AsmReadGs (); - StackTop -= StackSwitchData->Ia32.KnownGoodStackSize; + StackTop -= StackSwitchData->KnownGoodStackSize; // // Update IDT to use Task Gate for given exception @@ -290,7 +290,7 @@ ArchSetupExceptionStack ( // // Load current task // - AsmWriteTr ((UINT16)((UINTN)StackSwitchData->Ia32.ExceptionTssDesc - Gdtr.Base)); + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Base)); // // Publish IDT diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c index fe8d02d3e4..5952295126 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c @@ -236,18 +236,18 @@ InitializeSeparateExceptionStacks ( NewGdtTable = ALIGN_POINTER (StackTop, sizeof (IA32_TSS_DESCRIPTOR)); AsmReadIdtr (&Idtr); - EssData.X64.KnownGoodStackTop = StackTop; - EssData.X64.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE; - EssData.X64.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST; - EssData.X64.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER; - EssData.X64.IdtTable = (VOID *)Idtr.Base; - EssData.X64.IdtTableSize = Idtr.Limit + 1; - EssData.X64.GdtTable = NewGdtTable; - EssData.X64.GdtTableSize = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDesc = NewGdtTable + Gdtr.Limit + 1; - EssData.X64.ExceptionTssDescSize = CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTss = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE; - EssData.X64.ExceptionTssSize = CPU_TSS_SIZE; + EssData.KnownGoodStackTop = StackTop; + EssData.KnownGoodStackSize = CPU_KNOWN_GOOD_STACK_SIZE; + EssData.StackSwitchExceptions = CPU_STACK_SWITCH_EXCEPTION_LIST; + EssData.StackSwitchExceptionNumber = CPU_STACK_SWITCH_EXCEPTION_NUMBER; + EssData.IdtTable = (VOID *)Idtr.Base; + EssData.IdtTableSize = Idtr.Limit + 1; + EssData.GdtTable = NewGdtTable; + EssData.GdtTableSize = CPU_TSS_DESC_SIZE + Gdtr.Limit + 1; + EssData.ExceptionTssDesc = NewGdtTable + Gdtr.Limit + 1; + EssData.ExceptionTssDescSize = CPU_TSS_DESC_SIZE; + EssData.ExceptionTss = NewGdtTable + Gdtr.Limit + 1 + CPU_TSS_DESC_SIZE; + EssData.ExceptionTssSize = CPU_TSS_SIZE; return ArchSetupExceptionStack (&EssData); } diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c index ff0dde4f12..c14ac66c43 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c @@ -136,15 +136,15 @@ ArchSetupExceptionStack ( UINTN GdtSize; if ((StackSwitchData == NULL) || - (StackSwitchData->X64.KnownGoodStackTop == 0) || - (StackSwitchData->X64.KnownGoodStackSize == 0) || - (StackSwitchData->X64.StackSwitchExceptions == NULL) || - (StackSwitchData->X64.StackSwitchExceptionNumber == 0) || - (StackSwitchData->X64.StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || - (StackSwitchData->X64.GdtTable == NULL) || - (StackSwitchData->X64.IdtTable == NULL) || - (StackSwitchData->X64.ExceptionTssDesc == NULL) || - (StackSwitchData->X64.ExceptionTss == NULL)) + (StackSwitchData->KnownGoodStackTop == 0) || + (StackSwitchData->KnownGoodStackSize == 0) || + (StackSwitchData->StackSwitchExceptions == NULL) || + (StackSwitchData->StackSwitchExceptionNumber == 0) || + (StackSwitchData->StackSwitchExceptionNumber > CPU_EXCEPTION_NUM) || + (StackSwitchData->GdtTable == NULL) || + (StackSwitchData->IdtTable == NULL) || + (StackSwitchData->ExceptionTssDesc == NULL) || + (StackSwitchData->ExceptionTss == NULL)) { return EFI_INVALID_PARAMETER; } @@ -154,16 +154,16 @@ ArchSetupExceptionStack ( // one or newly allocated, has enough space to hold descriptors for exception // task-state segments. // - if (((UINTN)StackSwitchData->X64.GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) { + if (((UINTN)StackSwitchData->GdtTable & (IA32_GDT_ALIGNMENT - 1)) != 0) { return EFI_INVALID_PARAMETER; } - if ((UINTN)StackSwitchData->X64.ExceptionTssDesc < (UINTN)(StackSwitchData->X64.GdtTable)) { + if ((UINTN)StackSwitchData->ExceptionTssDesc < (UINTN)(StackSwitchData->GdtTable)) { return EFI_INVALID_PARAMETER; } - if (((UINTN)StackSwitchData->X64.ExceptionTssDesc + StackSwitchData->X64.ExceptionTssDescSize) > - ((UINTN)(StackSwitchData->X64.GdtTable) + StackSwitchData->X64.GdtTableSize)) + if (((UINTN)StackSwitchData->ExceptionTssDesc + StackSwitchData->ExceptionTssDescSize) > + ((UINTN)(StackSwitchData->GdtTable) + StackSwitchData->GdtTableSize)) { return EFI_INVALID_PARAMETER; } @@ -171,20 +171,20 @@ ArchSetupExceptionStack ( // // One task gate descriptor and one task-state segment are needed. // - if (StackSwitchData->X64.ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) { + if (StackSwitchData->ExceptionTssDescSize < sizeof (IA32_TSS_DESCRIPTOR)) { return EFI_INVALID_PARAMETER; } - if (StackSwitchData->X64.ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) { + if (StackSwitchData->ExceptionTssSize < sizeof (IA32_TASK_STATE_SEGMENT)) { return EFI_INVALID_PARAMETER; } // // Interrupt stack table supports only 7 vectors. // - TssDesc = StackSwitchData->X64.ExceptionTssDesc; - Tss = StackSwitchData->X64.ExceptionTss; - if (StackSwitchData->X64.StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) { + TssDesc = StackSwitchData->ExceptionTssDesc; + Tss = StackSwitchData->ExceptionTss; + if (StackSwitchData->StackSwitchExceptionNumber > ARRAY_SIZE (Tss->IST)) { return EFI_INVALID_PARAMETER; } @@ -195,19 +195,19 @@ ArchSetupExceptionStack ( AsmReadGdtr (&Gdtr); GdtSize = (UINTN)TssDesc + sizeof (IA32_TSS_DESCRIPTOR) - - (UINTN)(StackSwitchData->X64.GdtTable); - if ((UINTN)StackSwitchData->X64.GdtTable != Gdtr.Base) { - CopyMem (StackSwitchData->X64.GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); - Gdtr.Base = (UINTN)StackSwitchData->X64.GdtTable; + (UINTN)(StackSwitchData->GdtTable); + if ((UINTN)StackSwitchData->GdtTable != Gdtr.Base) { + CopyMem (StackSwitchData->GdtTable, (VOID *)Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base = (UINTN)StackSwitchData->GdtTable; Gdtr.Limit = (UINT16)GdtSize - 1; } - if ((UINTN)StackSwitchData->X64.IdtTable != Idtr.Base) { - Idtr.Base = (UINTN)StackSwitchData->X64.IdtTable; + if ((UINTN)StackSwitchData->IdtTable != Idtr.Base) { + Idtr.Base = (UINTN)StackSwitchData->IdtTable; } - if (StackSwitchData->X64.IdtTableSize > 0) { - Idtr.Limit = (UINT16)(StackSwitchData->X64.IdtTableSize - 1); + if (StackSwitchData->IdtTableSize > 0) { + Idtr.Limit = (UINT16)(StackSwitchData->IdtTableSize - 1); } // @@ -231,20 +231,20 @@ ArchSetupExceptionStack ( // Fixup exception task descriptor and task-state segment // ZeroMem (Tss, sizeof (*Tss)); - StackTop = StackSwitchData->X64.KnownGoodStackTop - CPU_STACK_ALIGNMENT; + StackTop = StackSwitchData->KnownGoodStackTop - CPU_STACK_ALIGNMENT; StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT); - IdtTable = StackSwitchData->X64.IdtTable; - for (Index = 0; Index < StackSwitchData->X64.StackSwitchExceptionNumber; ++Index) { + IdtTable = StackSwitchData->IdtTable; + for (Index = 0; Index < StackSwitchData->StackSwitchExceptionNumber; ++Index) { // // Fixup IST // Tss->IST[Index] = StackTop; - StackTop -= StackSwitchData->X64.KnownGoodStackSize; + StackTop -= StackSwitchData->KnownGoodStackSize; // // Set the IST field to enable corresponding IST // - Vector = StackSwitchData->X64.StackSwitchExceptions[Index]; + Vector = StackSwitchData->StackSwitchExceptions[Index]; if ((Vector >= CPU_EXCEPTION_NUM) || (Vector >= (Idtr.Limit + 1) / sizeof (IA32_IDT_GATE_DESCRIPTOR))) { @@ -262,7 +262,7 @@ ArchSetupExceptionStack ( // // Load current task // - AsmWriteTr ((UINT16)((UINTN)StackSwitchData->X64.ExceptionTssDesc - Gdtr.Base)); + AsmWriteTr ((UINT16)((UINTN)StackSwitchData->ExceptionTssDesc - Gdtr.Base)); // // Publish IDT -- 2.31.1.windows.1