From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web09.4115.1659992764430957668 for ; Mon, 08 Aug 2022 14:06:04 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=kDjlUSrT; spf=pass (domain: intel.com, ip: 192.55.52.120, mailfrom: ankit.sinha@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659992764; x=1691528764; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=p7vtDovtKBK8sbhfmIhBbK/ZEPk7ojNDgNtMNkVMP90=; b=kDjlUSrTC02miMX6TMwjtJEnF9GwlCk6X/Nq+vL0hd2vELH0RURQqAnh gTMTn5aiPe4NOKgpeSSExrhubR1bSby6zO9z8XVPJHQWLIBcecaU0vyy1 NNOXMzsnTymWvsZqVoWBv98SGM+5gslEmAe5rFNo3FUTzQJT/vS/ggsYS DmyDUJq27Dpzu+2CKMA4MAuPA9r+Zq+m3eab7/1P/PbDUsA59CzF3nqQT oQfnvpt7S5Zo3bPh2xne2lJG3UTIPtNZ3qYfm+o6KuB8pwF0xfJ6/sVfP UMHzPY+BH1UusivPSqdqC0vr93krF1dlRn1cMsm55cVdEBWcvgOegouwS A==; X-IronPort-AV: E=McAfee;i="6400,9594,10433"; a="289449730" X-IronPort-AV: E=Sophos;i="5.93,222,1654585200"; d="scan'208";a="289449730" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 14:05:56 -0700 X-IronPort-AV: E=Sophos;i="5.93,222,1654585200"; d="scan'208";a="730888429" Received: from ankitsin-mobl4.amr.corp.intel.com ([10.209.122.189]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 14:05:55 -0700 From: "Sinha, Ankit" To: devel@edk2.groups.io Cc: Isaac Oram , Nate DeSimone , Eric Dong Subject: [edk2-devel][edk2-platforms][PATCH V3 1/1] MinPlatformPkg/AcpiTables: Add additional thread mapping in MADT Date: Mon, 8 Aug 2022 14:05:11 -0700 Message-Id: <20220808210511.466-1-ankit.sinha@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add mapping for all enabled and disabled threads in MADT Cc: Isaac Oram Cc: Nate DeSimone Cc: Eric Dong Signed-off-by: Ankit Sinha --- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 49 +++++++++++--------- 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c index e68b6070607f..5a282e7c18f2 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c @@ -243,46 +243,54 @@ SortCpuLocalApicInTable ( } } - // - // 1. Sort TempCpuApicIdOrderTable, - // sort it by using ApicId from minimum to maximum (Socket0 to SocketN), and the BSP must in the fist location of the table. - // So, start sorting the table from the second element and total elements are mNumberOfCpus-1. - // + /* + 1. Sort TempCpuApicIdOrderTable, + Sort it by using ApicId from minimum to maximum (Socket0 to SocketN), and the BSP must be in the fist location of the table. + + 2. Sort and map all the enabled threads after BSP in CpuApicIdOrderTable + + 3. Threads that are not enabled are placed in the bottom of CpuApicIdOrderTable + + 4. Re-assign AcpiProcessorId for AcpiProcessorUid uses purpose. + */ + PerformQuickSort ((TempCpuApicIdOrderTable + 1), (mNumberOfCpus - 1), sizeof (EFI_CPU_ID_ORDER_MAP), (SORT_COMPARE) ApicIdCompareFunction); - // - // 2. Sort and map the primary threads to the front of the CpuApicIdOrderTable - // for (CurrProcessor = 0, Index = 0; Index < mNumberOfCpus; Index++) { - if ((TempCpuApicIdOrderTable[Index].Thread) == 0) { // primary thread + if ((TempCpuApicIdOrderTable[Index].Thread) == 0) { CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); CurrProcessor++; } } - // - // 3. Sort and map the second threads to the middle of the CpuApicIdOrderTable - // for (Index = 0; Index < mNumberOfCpus; Index++) { - if ((TempCpuApicIdOrderTable[Index].Thread) == 1) { //second thread + if ((TempCpuApicIdOrderTable[Index].Thread) == 1) { CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); CurrProcessor++; } } - // - // 4. Sort and map the not enabled threads to the bottom of the CpuApicIdOrderTable - // for (Index = 0; Index < mNumberOfCpus; Index++) { - if (TempCpuApicIdOrderTable[Index].Flags == 0) { // not enabled + if ((TempCpuApicIdOrderTable[Index].Thread) == 2) { + CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); + CurrProcessor++; + } + } + + for (Index = 0; Index < mNumberOfCpus; Index++) { + if ((TempCpuApicIdOrderTable[Index].Thread) == 3) { + CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); + CurrProcessor++; + } + } + + for (Index = 0; Index < mNumberOfCpus; Index++) { + if (TempCpuApicIdOrderTable[Index].Flags == 0) { CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); CurrProcessor++; } } - // - // 5. Re-assign AcpiProcessorId for AcpiProcessorUid uses purpose. - // for (Socket = 0; Socket < FixedPcdGet32 (PcdMaxCpuSocketCount); Socket++) { for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) { if (mCpuApicIdOrderTable[CurrProcessor].Flags && (mCpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) { @@ -292,7 +300,6 @@ SortCpuLocalApicInTable ( } } - //keep for debug purpose DEBUG ((DEBUG_INFO, "APIC ID Order Table ReOrdered\n")); DebugDisplayReOrderTable (mCpuApicIdOrderTable); -- 2.27.0.windows.1