From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web09.546.1660092515667682186 for ; Tue, 09 Aug 2022 17:48:35 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=S04LZL36; spf=pass (domain: intel.com, ip: 192.55.52.43, mailfrom: chasel.chiu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660092515; x=1691628515; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xtDcnyCWEp2OPH2Yx/VqkYbg6caDRPdETz9zmuOveTU=; b=S04LZL36fZJuMzNXORzgOUOSQwIROQiUSwf5FHtxdW3gZp0DiTegTCvV dFFUIK8RuAyybYOhJSKurIJLr0wQpwGLKfV91nfbwl6yjZXmUiPO+mMel LANCY6Eb2wVsHR413tAgPBqx6nfltSwnYcKibqFwBA0c/qaO6z+4RCW98 YyU/UaZ6zsn8I9Vkvjg5EI0vLZCAT+Ex28o8inzs2Zf06wdlk4LGvQi89 zHeLAoop+qq/BgekhbbSQZ8s05yq82V6MZ0p7rxKDqwpLzEFK51u5Etas rHxMJewvdU2pkzDUXoJHieBmEcDdc7KahFtCZlkWIOJPeap6ybh6YMMh9 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10434"; a="377257846" X-IronPort-AV: E=Sophos;i="5.93,225,1654585200"; d="scan'208";a="377257846" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 17:48:34 -0700 X-IronPort-AV: E=Sophos;i="5.93,225,1654585200"; d="scan'208";a="555542631" Received: from cchiu4-mobl.gar.corp.intel.com ([10.212.149.229]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 17:48:34 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [PATCH v2 3/4] IntelFsp2Pkg: Adopt FSP 2.4 MultiPhase functions. Date: Tue, 9 Aug 2022 17:48:21 -0700 Message-Id: <20220810004822.1499-4-chasel.chiu@intel.com> X-Mailer: git-send-email 2.35.0.windows.1 In-Reply-To: <20220810004822.1499-1-chasel.chiu@intel.com> References: <20220810004822.1499-1-chasel.chiu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3916 Adopt MultiPhase functions for both FspSecCoreS and FspSecCoreM. For backward compatibility, new INF are created for new modules. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/SecFsp.c | 4 ++++ IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 9 +++++++++ IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf | 75 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf | 59 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm | 304 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm | 101 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++ IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm | 3 +++ IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm | 303 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm | 108 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm | 3 +++ 10 files changed, 969 insertions(+) diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.c index d9085ef51f..11be1f97ca 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -135,6 +135,10 @@ FspGlobalDataInit ( PeiFspData->CoreStack =3D BootLoaderStack;=0D PeiFspData->PerfIdx =3D 2;=0D PeiFspData->PerfSig =3D FSP_PERFORMANCE_DATA_SIGNATURE;=0D + //=0D + // Cache FspHobList pointer passed by bootloader via ApiParameter2=0D + //=0D + PeiFspData->FspHobListPtr =3D (VOID **)GetFspApiParameter2 ();=0D =0D SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY);=0D =0D diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index 35d223a404..a44fbf2a50 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -69,8 +69,17 @@ FspApiCallingCheck ( Status =3D EFI_UNSUPPORTED;=0D } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, = ApiParam))) {=0D Status =3D EFI_INVALID_PARAMETER;=0D + } else if (ApiIdx =3D=3D FspSiliconInitApiIndex) {=0D + //=0D + // Reset MultiPhase NumberOfPhases to zero=0D + //=0D + FspData->NumberOfPhases =3D 0;=0D }=0D }=0D + } else if (ApiIdx =3D=3D FspMultiPhaseMemInitApiIndex) {=0D + if ((FspData =3D=3D NULL) || ((UINTN)FspData =3D=3D MAX_ADDRESS) || ((= UINTN)FspData =3D=3D MAX_UINT32)) {=0D + Status =3D EFI_UNSUPPORTED;=0D + }=0D } else if (ApiIdx =3D=3D FspSmmInitApiIndex) {=0D //=0D // FspSmmInitApiIndex check=0D diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf b/IntelFsp2Pkg/FspSe= cCore/Fsp24SecCoreM.inf new file mode 100644 index 0000000000..e93e176f15 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreM.inf @@ -0,0 +1,75 @@ +## @file=0D +# Sec Core for FSP to support MultiPhase (SeparatePhase) MemInitializatio= n.=0D +#=0D +# Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D Fsp24SecCoreM=0D + FILE_GUID =3D C5BC0719-4A23-4F6E-94DA-05FB6A0DFA9C= =0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[Sources]=0D + SecMain.c=0D + SecMain.h=0D + SecFsp.c=0D + SecFsp.h=0D + SecFspApiChk.c=0D +=0D +[Sources.IA32]=0D + Ia32/Stack.nasm=0D + Ia32/Fsp24ApiEntryM.nasm=0D + Ia32/FspApiEntryCommon.nasm=0D + Ia32/FspHelper.nasm=0D + Ia32/ReadEsp.nasm=0D +=0D +[Sources.X64]=0D + X64/Stack.nasm=0D + X64/Fsp24ApiEntryM.nasm=0D + X64/FspApiEntryCommon.nasm=0D + X64/FspHelper.nasm=0D + X64/ReadRsp.nasm=0D +=0D +[Binaries.Ia32]=0D + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + IntelFsp2Pkg/IntelFsp2Pkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseMemoryLib=0D + DebugLib=0D + BaseLib=0D + PciCf8Lib=0D + SerialPortLib=0D + FspSwitchStackLib=0D + FspCommonLib=0D + FspSecPlatformLib=0D + CpuLib=0D + UefiCpuLib=0D + FspMultiPhaseLib=0D +=0D +[Pcd]=0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspHeapSizePercentage ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspMaxInterruptSupported ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspPrivateTemporaryRamSize ## CONSUMES= =0D +=0D +[Ppis]=0D + gEfiTemporaryRamSupportPpiGuid ## PRODUCES= =0D + gFspInApiModePpiGuid ## PRODUCES= =0D diff --git a/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf b/IntelFsp2Pkg/FspSe= cCore/Fsp24SecCoreS.inf new file mode 100644 index 0000000000..1d44fb67b5 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Fsp24SecCoreS.inf @@ -0,0 +1,59 @@ +## @file=0D +# Sec Core for FSP to support MultiPhase (SeparatePhase) SiInitialization= .=0D +#=0D +# Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D Fsp24SecCoreS=0D + FILE_GUID =3D E039988B-0F21-4D95-AE34-C469B10E13F8= =0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[Sources]=0D + SecFspApiChk.c=0D + SecFsp.h=0D +=0D +[Sources.IA32]=0D + Ia32/Stack.nasm=0D + Ia32/Fsp24ApiEntryS.nasm=0D + Ia32/FspApiEntryCommon.nasm=0D + Ia32/FspHelper.nasm=0D +=0D +[Sources.X64]=0D + X64/Stack.nasm=0D + X64/Fsp24ApiEntryS.nasm=0D + X64/FspApiEntryCommon.nasm=0D + X64/FspHelper.nasm=0D +=0D +[Binaries.Ia32]=0D + RAW|Vtf0/Bin/ResetVec.ia32.raw |GCC=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + IntelFsp2Pkg/IntelFsp2Pkg.dec=0D +=0D +[LibraryClasses]=0D + BaseMemoryLib=0D + DebugLib=0D + BaseLib=0D + PciCf8Lib=0D + SerialPortLib=0D + FspSwitchStackLib=0D + FspCommonLib=0D + FspSecPlatformLib=0D + FspMultiPhaseLib=0D +=0D +[Ppis]=0D + gEfiTemporaryRamSupportPpiGuid ## PRODUCES= =0D +=0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/Fsp24ApiEntryM.nasm new file mode 100644 index 0000000000..997b9c0bff --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryM.nasm @@ -0,0 +1,304 @@ +;; @file=0D +; Provide FSP API entry points.=0D +;=0D +; Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;;=0D +=0D + SECTION .text=0D +=0D +;=0D +; Following are fixed PCDs=0D +;=0D +extern ASM_PFX(PcdGet32(PcdTemporaryRamBase))=0D +extern ASM_PFX(PcdGet32(PcdTemporaryRamSize))=0D +extern ASM_PFX(PcdGet32(PcdFspTemporaryRamSize))=0D +extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))=0D +=0D +struc FSPM_UPD_COMMON=0D + ; FSP_UPD_HEADER {=0D + .FspUpdHeader: resd 8=0D + ; }=0D + ; FSPM_ARCH_UPD {=0D + .Revision: resb 1=0D + .Reserved: resb 3=0D + .NvsBufferPtr: resd 1=0D + .StackBase: resd 1=0D + .StackSize: resd 1=0D + .BootLoaderTolumSize: resd 1=0D + .BootMode: resd 1=0D + .Reserved1: resb 8=0D + ; }=0D + .size:=0D +endstruc=0D +=0D +struc FSPM_UPD_COMMON_FSP24=0D + ; FSP_UPD_HEADER {=0D + .FspUpdHeader: resd 8=0D + ; }=0D + ; FSPM_ARCH2_UPD {=0D + .Revision: resb 1=0D + .Reserved: resb 3=0D + .Length resd 1=0D + .StackBase: resq 1=0D + .StackSize: resq 1=0D + .BootLoaderTolumSize: resd 1=0D + .BootMode: resd 1=0D + .FspEventHandler resq 1=0D + .Reserved1: resb 24=0D + ; }=0D + .size:=0D +endstruc=0D +=0D +;=0D +; Following functions will be provided in C=0D +;=0D +extern ASM_PFX(SecStartup)=0D +extern ASM_PFX(FspApiCommon)=0D +=0D +;=0D +; Following functions will be provided in PlatformSecLib=0D +;=0D +extern ASM_PFX(AsmGetFspBaseAddress)=0D +extern ASM_PFX(AsmGetFspInfoHeader)=0D +extern ASM_PFX(FspMultiPhaseMemInitApiHandler)=0D +=0D +STACK_SAVED_EAX_OFFSET EQU 4 * 7 ; size of a general purpose regis= ter * eax index=0D +API_PARAM1_OFFSET EQU 34h ; ApiParam1 [ sub esp,8 + pushad += pushfd + push eax + call]=0D +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch=0D +FSP_HEADER_CFGREG_OFFSET EQU 24h=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspMemoryInit API=0D +;=0D +; This FSP API is called after TempRamInit and initializes the memory.=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspMemoryInitApi)=0D +ASM_PFX(FspMemoryInitApi):=0D + mov eax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspMultiPhaseMemoryInitApi API=0D +;=0D +; This FSP API provides multi-phase Memory initialization, which brings gr= eater=0D +; modularity beyond the existing FspMemoryInit() API.=0D +; Increased modularity is achieved by adding an extra API to FSP-M.=0D +; This allows the bootloader to add board specific initialization steps th= roughout=0D +; the MemoryInit flow as needed.=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspMultiPhaseMemoryInitApi)=0D +ASM_PFX(FspMultiPhaseMemoryInitApi):=0D + mov eax, 8 ; FSP_API_INDEX.FspMultiPhaseMemInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +;-------------------------------------------------------------------------= ---=0D +; TempRamExitApi API=0D +;=0D +; This API tears down temporary RAM=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(TempRamExitApi)=0D +ASM_PFX(TempRamExitApi):=0D + mov eax, 4 ; FSP_API_INDEX.TempRamExitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspApiCommonContinue API=0D +;=0D +; This is the FSP API common entry point to resume the FSP execution=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspApiCommonContinue)=0D +ASM_PFX(FspApiCommonContinue):=0D + ;=0D + ; Handle FspMultiPhaseMemInitApiIndex API=0D + ;=0D + cmp eax, 8 ; FspMultiPhaseMemInitApiIndex=0D + jnz NotMultiPhaseMemoryInitApi=0D +=0D + pushad=0D + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam=0D + push eax ; push ApiIdx=0D + call ASM_PFX(FspMultiPhaseMemInitApiHandler)=0D + add esp, 8=0D + mov dword [esp + STACK_SAVED_EAX_OFFSET], eax=0D + popad=0D + ret=0D +=0D +NotMultiPhaseMemoryInitApi:=0D +=0D + ;=0D + ; FspMemoryInit API setup the initial stack frame=0D + ;=0D +=0D + ;=0D + ; Place holder to store the FspInfoHeader pointer=0D + ;=0D + push eax=0D +=0D + ;=0D + ; Update the FspInfoHeader pointer=0D + ;=0D + push eax=0D + call ASM_PFX(AsmGetFspInfoHeader)=0D + mov [esp + 4], eax=0D + pop eax=0D +=0D + ;=0D + ; Create a Task Frame in the stack for the Boot Loader=0D + ;=0D + pushfd ; 2 pushf for 4 byte alignment=0D + cli=0D + pushad=0D +=0D + ; Reserve 8 bytes for IDT save/restore=0D + sub esp, 8=0D + sidt [esp]=0D +=0D +=0D + ; Get Stackbase and StackSize from FSPM_UPD Param=0D + mov edx, [esp + API_PARAM1_OFFSET]=0D + cmp edx, 0=0D + jnz FspStackSetup=0D +=0D + ; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null=0D + push eax=0D + call ASM_PFX(AsmGetFspInfoHeader)=0D + mov edx, [eax + FSP_HEADER_IMGBASE_OFFSET]=0D + add edx, [eax + FSP_HEADER_CFGREG_OFFSET]=0D + pop eax=0D +=0D +FspStackSetup:=0D + mov ecx, [edx + FSPM_UPD_COMMON.Revision]=0D + cmp ecx, 3=0D + jae FspmUpdCommon2=0D +=0D + ;=0D + ; StackBase =3D temp memory base, StackSize =3D temp memory size=0D + ;=0D + mov edi, [edx + FSPM_UPD_COMMON.StackBase]=0D + mov ecx, [edx + FSPM_UPD_COMMON.StackSize]=0D + jmp ChkFspHeapSize=0D +=0D +FspmUpdCommon2:=0D + mov edi, [edx + FSPM_UPD_COMMON_FSP24.StackBase]=0D + mov ecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize]=0D +=0D +ChkFspHeapSize:=0D + ;=0D + ; Keep using bootloader stack if heap size % is 0=0D + ;=0D + mov bl, BYTE [ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))]=0D + cmp bl, 0=0D + jz SkipStackSwitch=0D +=0D + ;=0D + ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't e= qual 0=0D + ;=0D + add edi, ecx=0D + ;=0D + ; Switch to new FSP stack=0D + ;=0D + xchg edi, esp ; Exchange edi and esp, e= di will be assigned to the current esp pointer and esp will be Stack base += Stack size=0D +=0D +SkipStackSwitch:=0D + ;=0D + ; If heap size % is 0:=0D + ; EDI is FSPM_UPD_COMMON.StackBase and will hold ESP later (boot loade= r stack pointer)=0D + ; ECX is FSPM_UPD_COMMON.StackSize=0D + ; ESP is boot loader stack pointer (no stack switch)=0D + ; BL is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON.= StackBase later)=0D + ;=0D + ; If heap size % is not 0=0D + ; EDI is boot loader stack pointer=0D + ; ECX is FSPM_UPD_COMMON.StackSize=0D + ; ESP is new stack (FSPM_UPD_COMMON.StackBase + FSPM_UPD_COMMON.StackS= ize)=0D + ; BL is NOT 0 to indicate stack has switched=0D + ;=0D + cmp bl, 0=0D + jnz StackHasBeenSwitched=0D +=0D + mov ebx, edi ; Put FSPM_UPD_COMMON.Sta= ckBase to ebx as temp memory base=0D + mov edi, esp ; Put boot loader stack p= ointer to edi=0D + jmp StackSetupDone=0D +=0D +StackHasBeenSwitched:=0D + mov ebx, esp ; Put Stack base + Stack = size in ebx=0D + sub ebx, ecx ; Stack base + Stack size= - Stack size as temp memory base=0D +=0D +StackSetupDone:=0D +=0D + ;=0D + ; Pass the API Idx to SecStartup=0D + ;=0D + push eax=0D +=0D + ;=0D + ; Pass the BootLoader stack to SecStartup=0D + ;=0D + push edi=0D +=0D + ;=0D + ; Pass entry point of the PEI core=0D + ;=0D + call ASM_PFX(AsmGetFspBaseAddress)=0D + mov edi, eax=0D + call ASM_PFX(AsmGetPeiCoreOffset)=0D + add edi, eax=0D + push edi=0D +=0D + ;=0D + ; Pass BFV into the PEI Core=0D + ; It uses relative address to calculate the actual boot FV base=0D + ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase an= d=0D + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,=0D + ; they are different. The code below can handle both cases.=0D + ;=0D + call ASM_PFX(AsmGetFspBaseAddress)=0D + push eax=0D +=0D + ;=0D + ; Pass stack base and size into the PEI Core=0D + ;=0D + push ebx=0D + push ecx=0D +=0D + ;=0D + ; Pass Control into the PEI Core=0D + ;=0D + call ASM_PFX(SecStartup)=0D + add esp, 4=0D +exit:=0D + ret=0D +=0D +global ASM_PFX(FspPeiCoreEntryOff)=0D +ASM_PFX(FspPeiCoreEntryOff):=0D + ;=0D + ; This value will be patched by the build script=0D + ;=0D + DD 0x12345678=0D +=0D +global ASM_PFX(AsmGetPeiCoreOffset)=0D +ASM_PFX(AsmGetPeiCoreOffset):=0D + mov eax, dword [ASM_PFX(FspPeiCoreEntryOff)]=0D + ret=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; TempRamInit API=0D +;=0D +; Empty function for WHOLEARCHIVE build option=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(TempRamInitApi)=0D +ASM_PFX(TempRamInitApi):=0D + jmp $=0D + ret=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; Module Entrypoint API=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(_ModuleEntryPoint)=0D +ASM_PFX(_ModuleEntryPoint):=0D + jmp $=0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm b/IntelFsp2Pk= g/FspSecCore/Ia32/Fsp24ApiEntryS.nasm new file mode 100644 index 0000000000..bda99cdd80 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/Ia32/Fsp24ApiEntryS.nasm @@ -0,0 +1,101 @@ +;; @file=0D +; Provide FSP API entry points.=0D +;=0D +; Copyright (c) 2020, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;;=0D +=0D + SECTION .text=0D +=0D +;=0D +; Following functions will be provided in C=0D +;=0D +extern ASM_PFX(FspApiCommon)=0D +extern ASM_PFX(FspMultiPhaseSiInitApiHandlerV2)=0D +=0D +STACK_SAVED_EAX_OFFSET EQU 4 * 7 ; size of a general purpose regis= ter * eax index=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; NotifyPhase API=0D +;=0D +; This FSP API will notify the FSP about the different phases in the boot= =0D +; process=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(NotifyPhaseApi)=0D +ASM_PFX(NotifyPhaseApi):=0D + mov eax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspSiliconInit API=0D +;=0D +; This FSP API initializes the CPU and the chipset including the IO=0D +; controllers in the chipset to enable normal operation of these devices.= =0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspSiliconInitApi)=0D +ASM_PFX(FspSiliconInitApi):=0D + mov eax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspMultiPhaseSiInitApi API=0D +;=0D +; This FSP API provides multi-phase silicon initialization, which brings g= reater=0D +; modularity beyond the existing FspSiliconInit() API.=0D +; Increased modularity is achieved by adding an extra API to FSP-S.=0D +; This allows the bootloader to add board specific initialization steps th= roughout=0D +; the SiliconInit flow as needed.=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspMultiPhaseSiInitApi)=0D +ASM_PFX(FspMultiPhaseSiInitApi):=0D + mov eax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspApiCommonContinue API=0D +;=0D +; This is the FSP API common entry point to resume the FSP execution=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspApiCommonContinue)=0D +ASM_PFX(FspApiCommonContinue):=0D + ;=0D + ; Handle FspMultiPhaseSiInitApiIndex API=0D + ;=0D + cmp eax, 6 ; FspMultiPhaseSiInitApiIndex=0D + jnz NotMultiPhaseSiInitApi=0D +=0D + pushad=0D + push DWORD [esp + (4 * 8 + 4)] ; push ApiParam=0D + push eax ; push ApiIdx=0D + call ASM_PFX(FspMultiPhaseSiInitApiHandlerV2)=0D + add esp, 8=0D + mov dword [esp + STACK_SAVED_EAX_OFFSET], eax=0D + popad=0D + ret=0D +=0D +NotMultiPhaseSiInitApi:=0D + jmp $=0D + ret=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; TempRamInit API=0D +;=0D +; Empty function for WHOLEARCHIVE build option=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(TempRamInitApi)=0D +ASM_PFX(TempRamInitApi):=0D + jmp $=0D + ret=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; Module Entrypoint API=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(_ModuleEntryPoint)=0D +ASM_PFX(_ModuleEntryPoint):=0D + jmp $=0D +=0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm b/IntelFsp= 2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm index 8d8deba28a..87446be779 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryCommon.nasm @@ -67,6 +67,9 @@ FspApiCommon2: cmp eax, 6 ; FspMultiPhaseSiInitApiIndex API=0D jz FspApiCommon3=0D =0D + cmp eax, 8 ; FspMultiPhaseMemInitApiIndex API=0D + jz FspApiCommon3=0D +=0D call ASM_PFX(AsmGetFspInfoHeader)=0D jmp ASM_PFX(Loader2PeiSwitchStack)=0D =0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm b/IntelFsp2Pkg= /FspSecCore/X64/Fsp24ApiEntryM.nasm new file mode 100644 index 0000000000..8880721f29 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryM.nasm @@ -0,0 +1,303 @@ +;; @file=0D +; Provide FSP API entry points.=0D +;=0D +; Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;;=0D +=0D + SECTION .text=0D +=0D +%include "PushPopRegsNasm.inc"=0D +=0D +;=0D +; Following are fixed PCDs=0D +;=0D +extern ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))=0D +=0D +struc FSPM_UPD_COMMON_FSP24=0D + ; FSP_UPD_HEADER {=0D + .FspUpdHeader: resd 8=0D + ; }=0D + ; FSPM_ARCH2_UPD {=0D + .Revision: resb 1=0D + .Reserved: resb 3=0D + .Length resd 1=0D + .StackBase: resq 1=0D + .StackSize: resq 1=0D + .BootLoaderTolumSize: resd 1=0D + .BootMode: resd 1=0D + .FspEventHandler resq 1=0D + .Reserved1: resb 24=0D + ; }=0D + .size:=0D +endstruc=0D +=0D +;=0D +; Following functions will be provided in C=0D +;=0D +extern ASM_PFX(SecStartup)=0D +extern ASM_PFX(FspApiCommon)=0D +=0D +;=0D +; Following functions will be provided in PlatformSecLib=0D +;=0D +extern ASM_PFX(AsmGetFspBaseAddress)=0D +extern ASM_PFX(AsmGetFspInfoHeader)=0D +extern ASM_PFX(FspMultiPhaseMemInitApiHandler)=0D +=0D +STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose regis= ter * rax index=0D +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch=0D +FSP_HEADER_CFGREG_OFFSET EQU 24h=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspMemoryInit API=0D +;=0D +; This FSP API is called after TempRamInit and initializes the memory.=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspMemoryInitApi)=0D +ASM_PFX(FspMemoryInitApi):=0D + mov rax, 3 ; FSP_API_INDEX.FspMemoryInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspMultiPhaseMemoryInitApi API=0D +;=0D +; This FSP API provides multi-phase Memory initialization, which brings gr= eater=0D +; modularity beyond the existing FspMemoryInit() API.=0D +; Increased modularity is achieved by adding an extra API to FSP-M.=0D +; This allows the bootloader to add board specific initialization steps th= roughout=0D +; the MemoryInit flow as needed.=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspMultiPhaseMemoryInitApi)=0D +ASM_PFX(FspMultiPhaseMemoryInitApi):=0D + mov rax, 8 ; FSP_API_INDEX.FspMultiPhaseMemInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +;-------------------------------------------------------------------------= ---=0D +; TempRamExitApi API=0D +;=0D +; This API tears down temporary RAM=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(TempRamExitApi)=0D +ASM_PFX(TempRamExitApi):=0D + mov rax, 4 ; FSP_API_INDEX.TempRamExitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspApiCommonContinue API=0D +;=0D +; This is the FSP API common entry point to resume the FSP execution=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspApiCommonContinue)=0D +ASM_PFX(FspApiCommonContinue):=0D + ;=0D + ; Handle FspMultiPhaseMemoInitApiIndex API=0D + ;=0D + push rdx ; Push a QWORD data for stack alignment=0D +=0D + cmp rax, 8 ; FspMultiPhaseMemInitApiIndex=0D + jnz NotMultiPhaseMemoryInitApi=0D +=0D + PUSHA_64=0D + mov rdx, rcx ; move ApiParam to rdx=0D + mov rcx, rax ; move ApiIdx to rcx=0D + sub rsp, 0x20 ; calling C function may need shadow space=0D + call ASM_PFX(FspMultiPhaseMemInitApiHandler)=0D + add rsp, 0x20 ; restore shadow space=0D + mov qword [rsp + STACK_SAVED_RAX_OFFSET], rax=0D + POPA_64=0D + add rsp, 0x08=0D + ret=0D +=0D +NotMultiPhaseMemoryInitApi:=0D + ; Push RDX and RCX to form CONTEXT_STACK_64=0D + push rdx ; Push API Parameter2 on stack=0D + push rcx ; Push API Parameter1 on stack=0D +=0D + ;=0D + ; FspMemoryInit API setup the initial stack frame=0D + ;=0D +=0D + ;=0D + ; Place holder to store the FspInfoHeader pointer=0D + ;=0D + push rax=0D +=0D + ;=0D + ; Update the FspInfoHeader pointer=0D + ;=0D + push rax=0D + call ASM_PFX(AsmGetFspInfoHeader)=0D + mov [rsp + 8], rax=0D + pop rax=0D +=0D + ;=0D + ; Create a Task Frame in the stack for the Boot Loader=0D + ;=0D + pushfq=0D + cli=0D + PUSHA_64=0D +=0D + ; Reserve 16 bytes for IDT save/restore=0D + sub rsp, 16=0D + sidt [rsp]=0D +=0D + ; Get Stackbase and StackSize from FSPM_UPD Param=0D + mov rdx, rcx ; Put FSPM_UPD Param to r= dx=0D + cmp rdx, 0=0D + jnz FspStackSetup=0D +=0D + ; Get UPD default values if FspmUpdDataPtr (ApiParam1) is null=0D + xchg rbx, rax=0D + call ASM_PFX(AsmGetFspInfoHeader)=0D + mov edx, [rax + FSP_HEADER_IMGBASE_OFFSET]=0D + add edx, [rax + FSP_HEADER_CFGREG_OFFSET]=0D + xchg rbx, rax=0D +=0D +FspStackSetup:=0D + mov cl, [rdx + FSPM_UPD_COMMON_FSP24.Revision]=0D + cmp cl, 3=0D + jae FspmUpdCommonFsp24=0D +=0D + mov rax, 08000000000000002h ; RETURN_INVALID_PARAMETE= R=0D + sub rsp, 0b8h=0D + ret=0D +=0D +FspmUpdCommonFsp24:=0D + ;=0D + ; StackBase =3D temp memory base, StackSize =3D temp memory size=0D + ;=0D + mov rdi, [rdx + FSPM_UPD_COMMON_FSP24.StackBase]=0D + mov ecx, [rdx + FSPM_UPD_COMMON_FSP24.StackSize]=0D +=0D + ;=0D + ; Keep using bootloader stack if heap size % is 0=0D + ;=0D + mov rbx, ASM_PFX(PcdGet8 (PcdFspHeapSizePercentage))=0D + mov bl, BYTE [rbx]=0D + cmp bl, 0=0D + jz SkipStackSwitch=0D +=0D + ;=0D + ; Set up a dedicated temp ram stack for FSP if FSP heap size % doesn't e= qual 0=0D + ;=0D + add rdi, rcx=0D + ;=0D + ; Switch to new FSP stack=0D + ;=0D + xchg rdi, rsp ; Exchange rdi and rsp, r= di will be assigned to the current rsp pointer and rsp will be Stack base += Stack size=0D +=0D +SkipStackSwitch:=0D + ;=0D + ; If heap size % is 0:=0D + ; EDI is FSPM_UPD_COMMON_FSP24.StackBase and will hold ESP later (boot= loader stack pointer)=0D + ; ECX is FSPM_UPD_COMMON_FSP24.StackSize=0D + ; ESP is boot loader stack pointer (no stack switch)=0D + ; BL is 0 to indicate no stack switch (EBX will hold FSPM_UPD_COMMON_= FSP24.StackBase later)=0D + ;=0D + ; If heap size % is not 0=0D + ; EDI is boot loader stack pointer=0D + ; ECX is FSPM_UPD_COMMON_FSP24.StackSize=0D + ; ESP is new stack (FSPM_UPD_COMMON_FSP24.StackBase + FSPM_UPD_COMMON_= FSP24.StackSize)=0D + ; BL is NOT 0 to indicate stack has switched=0D + ;=0D + cmp bl, 0=0D + jnz StackHasBeenSwitched=0D +=0D + mov rbx, rdi ; Put FSPM_UPD_COMMON_FSP= 24.StackBase to rbx as temp memory base=0D + mov rdi, rsp ; Put boot loader stack p= ointer to rdi=0D + jmp StackSetupDone=0D +=0D +StackHasBeenSwitched:=0D + mov rbx, rsp ; Put Stack base + Stack = size in ebx=0D + sub rbx, rcx ; Stack base + Stack size= - Stack size as temp memory base=0D +=0D +StackSetupDone:=0D +=0D + ;=0D + ; Per X64 calling convention, make sure RSP is 16-byte aligned.=0D + ;=0D + mov rdx, rsp=0D + and rdx, 0fh=0D + sub rsp, rdx=0D +=0D + ;=0D + ; Pass the API Idx to SecStartup=0D + ;=0D + push rax=0D +=0D + ;=0D + ; Pass the BootLoader stack to SecStartup=0D + ;=0D + push rdi=0D +=0D + ;=0D + ; Pass BFV into the PEI Core=0D + ; It uses relative address to calculate the actual boot FV base=0D + ; For FSP implementation with single FV, PcdFspBootFirmwareVolumeBase an= d=0D + ; PcdFspAreaBaseAddress are the same. For FSP with multiple FVs,=0D + ; they are different. The code below can handle both cases.=0D + ;=0D + call ASM_PFX(AsmGetFspBaseAddress)=0D + mov r8, rax=0D +=0D + ;=0D + ; Pass entry point of the PEI core=0D + ;=0D + call ASM_PFX(AsmGetPeiCoreOffset)=0D + lea r9, [r8 + rax]=0D +=0D + ;=0D + ; Pass stack base and size into the PEI Core=0D + ;=0D + mov rcx, rcx=0D + mov rdx, rbx=0D +=0D + ;=0D + ; Pass Control into the PEI Core=0D + ; RCX =3D SizeOfRam, RDX =3D TempRamBase, R8 =3D BFV, R9 =3D PeiCoreEntr= y, Last 1 Stack =3D BL stack, Last 2 Stack =3D API index=0D + ; According to X64 calling convention, caller has to allocate 32 bytes a= s a shadow store on call stack right before=0D + ; calling the function.=0D + ;=0D + sub rsp, 20h=0D + call ASM_PFX(SecStartup)=0D + add rsp, 20h=0D +exit:=0D + ret=0D +=0D +global ASM_PFX(FspPeiCoreEntryOff)=0D +ASM_PFX(FspPeiCoreEntryOff):=0D + ;=0D + ; This value will be patched by the build script=0D + ;=0D + DD 0x12345678=0D +=0D +global ASM_PFX(AsmGetPeiCoreOffset)=0D +ASM_PFX(AsmGetPeiCoreOffset):=0D + push rbx=0D + mov rbx, ASM_PFX(FspPeiCoreEntryOff)=0D + mov eax, dword[ebx]=0D + pop rbx=0D + ret=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; TempRamInit API=0D +;=0D +; Empty function for WHOLEARCHIVE build option=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(TempRamInitApi)=0D +ASM_PFX(TempRamInitApi):=0D + jmp $=0D + ret=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; Module Entrypoint API=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(_ModuleEntryPoint)=0D +ASM_PFX(_ModuleEntryPoint):=0D + jmp $=0D +=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm b/IntelFsp2Pkg= /FspSecCore/X64/Fsp24ApiEntryS.nasm new file mode 100644 index 0000000000..5bbbc5d1d0 --- /dev/null +++ b/IntelFsp2Pkg/FspSecCore/X64/Fsp24ApiEntryS.nasm @@ -0,0 +1,108 @@ +;; @file=0D +; Provide FSP API entry points.=0D +;=0D +; Copyright (c) 2022, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;;=0D +=0D + SECTION .text=0D +=0D +;=0D +; Following functions will be provided in C=0D +;=0D +extern ASM_PFX(FspApiCommon)=0D +extern ASM_PFX(FspMultiPhaseSiInitApiHandlerV2)=0D +=0D +STACK_SAVED_RAX_OFFSET EQU 8 * 7 ; size of a general purpose regis= ter * rax index=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; NotifyPhase API=0D +;=0D +; This FSP API will notify the FSP about the different phases in the boot= =0D +; process=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(NotifyPhaseApi)=0D +ASM_PFX(NotifyPhaseApi):=0D + mov rax, 2 ; FSP_API_INDEX.NotifyPhaseApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspSiliconInit API=0D +;=0D +; This FSP API initializes the CPU and the chipset including the IO=0D +; controllers in the chipset to enable normal operation of these devices.= =0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspSiliconInitApi)=0D +ASM_PFX(FspSiliconInitApi):=0D + mov rax, 5 ; FSP_API_INDEX.FspSiliconInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspMultiPhaseSiInitApi API=0D +;=0D +; This FSP API provides multi-phase silicon initialization, which brings g= reater=0D +; modularity beyond the existing FspSiliconInit() API.=0D +; Increased modularity is achieved by adding an extra API to FSP-S.=0D +; This allows the bootloader to add board specific initialization steps th= roughout=0D +; the SiliconInit flow as needed.=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +=0D +%include "PushPopRegsNasm.inc"=0D +=0D +global ASM_PFX(FspMultiPhaseSiInitApi)=0D +ASM_PFX(FspMultiPhaseSiInitApi):=0D + mov rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex=0D + jmp ASM_PFX(FspApiCommon)=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; FspApiCommonContinue API=0D +;=0D +; This is the FSP API common entry point to resume the FSP execution=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(FspApiCommonContinue)=0D +ASM_PFX(FspApiCommonContinue):=0D + ;=0D + ; Handle FspMultiPhaseSiInitApiIndex API=0D + ;=0D + push rdx ; Push a QWORD data for stack alignment=0D +=0D + cmp rax, 6 ; FSP_API_INDEX.FspMultiPhaseSiInitApiIndex=0D + jnz NotMultiPhaseSiInitApi=0D +=0D + PUSHA_64=0D + mov rdx, rcx ; move ApiParam to rdx=0D + mov rcx, rax ; move ApiIdx to rcx=0D + sub rsp, 0x20 ; calling C function may need shadow space=0D + call ASM_PFX(FspMultiPhaseSiInitApiHandlerV2)=0D + add rsp, 0x20 ; restore shadow space=0D + mov qword [rsp + STACK_SAVED_RAX_OFFSET], rax=0D + POPA_64=0D + add rsp, 0x08=0D + ret=0D +=0D +NotMultiPhaseSiInitApi:=0D + jmp $=0D + ret=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; TempRamInit API=0D +;=0D +; Empty function for WHOLEARCHIVE build option=0D +;=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(TempRamInitApi)=0D +ASM_PFX(TempRamInitApi):=0D + jmp $=0D + ret=0D +=0D +;-------------------------------------------------------------------------= ---=0D +; Module Entrypoint API=0D +;-------------------------------------------------------------------------= ---=0D +global ASM_PFX(_ModuleEntryPoint)=0D +ASM_PFX(_ModuleEntryPoint):=0D + jmp $=0D +=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm b/IntelFsp2= Pkg/FspSecCore/X64/FspApiEntryCommon.nasm index 718e672e02..dc6b8c99a1 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryCommon.nasm @@ -68,6 +68,9 @@ FspApiCommon2: cmp rax, 6 ; FspMultiPhaseSiInitApiIndex API=0D jz FspApiCommon3=0D =0D + cmp rax, 8 ; FspMultiPhaseMemInitApiIndex API=0D + jz FspApiCommon3=0D +=0D call ASM_PFX(AsmGetFspInfoHeader)=0D jmp ASM_PFX(Loader2PeiSwitchStack)=0D =0D --=20 2.35.0.windows.1