From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.2557.1660109910932314511 for ; Tue, 09 Aug 2022 22:38:34 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=aIUuGQkQ; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: dun.tan@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1660109913; x=1691645913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=n5p+7QujBUGkoyY5NNP4qa/IVd64rhYgE1516UBQ7fs=; b=aIUuGQkQIeT5LzG/TQghCE/jOMOEqbdC+wvJM5IB+H8dLbXoN3D6oD+p wUUO94o9EvcevsuNWGD9TQu4Od0Aau3RaRUpfBWNjV8FHGy9Y7D9skOZH E6XNbklRszceDOW02rEbxO9hVEDo5G8vJ3mFs89r8epjoupRuy9gIrC0D zMvGfetb3LrJ+Gz4B1Vh4XvUZZgi8scS40Ddd1LWWak8VeXssFPDe+tJ7 svY0SBez8rsdHkpwalRj9QHIRM0wP20Jub35hA71H80LCirEZfJjnD7jf 9oWZUiTsXrK6ChZgzYgVx/I1TbL0u1+9mejenYsVQdpU6u5uI7HRAJPkt Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10434"; a="277940669" X-IronPort-AV: E=Sophos;i="5.93,226,1654585200"; d="scan'208";a="277940669" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 22:38:33 -0700 X-IronPort-AV: E=Sophos;i="5.93,226,1654585200"; d="scan'208";a="581094663" Received: from duntan-mobl.ccr.corp.intel.com ([10.239.157.47]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Aug 2022 22:38:32 -0700 From: "duntan" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar Subject: [Patch V2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flag Date: Wed, 10 Aug 2022 13:37:12 +0800 Message-Id: <20220810053713.378-2-dun.tan@intel.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20220810053713.378-1-dun.tan@intel.com> References: <20220810053713.378-1-dun.tan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This patch is code refactoring and doesn't change any functionality. Add a new IsShadowStack flag to identify whether current memory is shadow stack. Previous smm code logic regards a RO range as shadow stack and set the dirty bit in corresponding page table entry if mInternalCr3 is not 0, which may be confusing. Signed-off-by: Dun Tan Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar --- UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c index 1f7cc15727..237742d7e6 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c @@ -33,6 +33,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = { }; UINTN mInternalCr3; +UINTN mIsShadowStack = FALSE; /** Set the internal page table base address. @@ -249,7 +250,7 @@ ConvertPageEntryAttribute ( if ((Attributes & EFI_MEMORY_RO) != 0) { if (IsSet) { NewPageEntry &= ~(UINT64)IA32_PG_RW; - if (mInternalCr3 != 0) { + if (mIsShadowStack) { // Environment setup // ReadOnly page need set Dirty bit for shadow stack NewPageEntry |= IA32_PG_D; @@ -734,10 +735,11 @@ SetShadowStack ( EFI_STATUS Status; SetPageTableBase (Cr3); - - Status = SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO); + mIsShadowStack = TRUE; + Status = SmmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO); SetPageTableBase (0); + mIsShadowStack = FALSE; return Status; } -- 2.31.1.windows.1