From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web12.22740.1662367784835192573 for ; Mon, 05 Sep 2022 01:49:45 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=BF+k9EsA; spf=permerror, err=too many SPF records (domain: intel.com, ip: 192.55.52.115, mailfrom: w.sheng@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662367784; x=1693903784; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=AvZQvIhChif0SxlzcZjwUDTPbwkjJTIDWSbWZNqsXNI=; b=BF+k9EsA5DgaKKMnMzPRAJylWoUheam4zl6i5bw26KVivOXyiIrY6rA4 JpfSl1sudmuzhyQ7Zlu/zlJywG3Y3FkKqRi+/yb08fUST62/OhwUXcrjD z+DkzIPwVEkA0noHCESDBkxrPz5cUsD7CCAFT+vtrQCfK2pv20d6fwKDb pVuTSiERWCB4ik4AKXjs2IynkCKGRQiTwGFfyG5pR9DtwoJJymWFGXJS0 A9kIqmI19sMQBUQsk31IIiIXYSQ0Zz1y9bsdQZDU3Wzn2l3rLVTjZAWBI Df8qIPr6XD+mNDamt6u/EOZjjNaFZHb3FmOvFw+K92YeKIEUdDFlPpm9p w==; X-IronPort-AV: E=McAfee;i="6500,9779,10460"; a="296345763" X-IronPort-AV: E=Sophos;i="5.93,290,1654585200"; d="scan'208";a="296345763" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Sep 2022 01:49:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,290,1654585200"; d="scan'208";a="590839558" Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.43]) by orsmga006.jf.intel.com with ESMTP; 05 Sep 2022 01:49:42 -0700 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Jenny Huang , Ray Ni , Rangasai V Chaganty , Robert Kowalewski Subject: [PATCH] IntelSiliconPkg/VTd: Enable ADM when change TTM Date: Mon, 5 Sep 2022 16:49:28 +0800 Message-Id: <20220905084928.636-1-w.sheng@intel.com> X-Mailer: git-send-email 2.26.2.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In Abort DMA Mode(ADM), hardware will abort all DMA operations without the need to set up a roottable. Enable Abort DMA Mode, when change Translation Table Mode(TTM) Change-Id: I74207fe96ef7a57d89a355d40dfbdd36186f06c3 Signed-off-by: Sheng Wei Cc: Jenny Huang Cc: Ray Ni Cc: Rangasai V Chaganty =0D Cc: Robert Kowalewski --- .../VTd/IntelVTdDmarPei/IntelVTdDmar.c | 157 +++++++++++----- .../Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf | 1 + .../Feature/VTd/IntelVTdDxe/VtdReg.c | 169 +++++++++++++----- .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 12 +- 4 files changed, 245 insertions(+), 94 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Inte= lVTdDmar.c index b5b78f779..24beccd26 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/IntelVTdDma= r.c @@ -361,6 +361,68 @@ InvalidateIOTLB ( return EFI_SUCCESS;=0D }=0D =0D +/**=0D + Clear Global Command Register Bits=0D +=0D + @param[in] VtdUnitBaseAddress The base address of the VTd engine.=0D + @param[in] BitMask Bit mask.=0D +**/=0D +VOID=0D +ClearGlobalCommandRegisterBits (=0D + IN UINTN VtdUnitBaseAddress,=0D + IN UINT32 BitMask=0D + )=0D +{=0D + UINT32 Reg32;=0D + UINT32 Status;=0D + UINT32 Command;=0D +=0D + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D + Command =3D (Status & (~BitMask));=0D + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);=0D +=0D + DEBUG((DEBUG_INFO, "Clear GCMD_REG bits 0x%x.\n", BitMask));=0D +=0D + //=0D + // Poll on Status bit of Global status register to become zero=0D + //=0D + do {=0D + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + } while ((Reg32 & BitMask) =3D=3D BitMask);=0D +}=0D +=0D +/**=0D + Set Global Command Register Bits=0D +=0D + @param[in] VtdUnitBaseAddress The base address of the VTd engine.=0D + @param[in] BitMask Bit mask.=0D +**/=0D +VOID=0D +SetGlobalCommandRegisterBits (=0D + IN UINTN VtdUnitBaseAddress,=0D + IN UINT32 BitMask=0D + )=0D +{=0D + UINT32 Reg32;=0D + UINT32 Status;=0D + UINT32 Command;=0D +=0D + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D + Command =3D (Status | BitMask);=0D + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);=0D +=0D + DEBUG((DEBUG_INFO, "Set GCMD_REG bits 0x%x.\n", BitMask));=0D +=0D + //=0D + // Poll on Status bit of Global status register to become not zero=0D + //=0D + do {=0D + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + } while ((Reg32 & BitMask) =3D=3D 0);=0D +}=0D +=0D /**=0D Enable DMAR translation in pre-mem phase.=0D =0D @@ -383,13 +445,10 @@ EnableDmarPreMem ( DEBUG ((DEBUG_INFO, "RTADDR_REG : 0x%016lx \n", RtaddrRegValue));=0D MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, RtaddrRegValue);=0D =0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_SRTP);= =0D -=0D DEBUG ((DEBUG_INFO, "EnableDmarPreMem: waiting for RTPS bit to be set...= \n"));=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0);=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP);=0D +=0D + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D DEBUG ((DEBUG_INFO, "EnableDmarPreMem: R_GSTS_REG =3D 0x%x \n", Reg32));= =0D =0D //=0D @@ -405,12 +464,7 @@ EnableDmarPreMem ( //=0D // Enable VTd=0D //=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_TE);=0D - DEBUG ((DEBUG_INFO, "EnableDmarPreMem: Waiting B_GSTS_REG_TE ...\n"));=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0);=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE);=0D =0D DEBUG ((DEBUG_INFO, "VTD () enabled!<<<<<<\n"));=0D =0D @@ -434,22 +488,43 @@ EnableDmar ( {=0D UINT32 Reg32;=0D UINTN VtdUnitBaseAddress;=0D + BOOLEAN TEWasEnabled;=0D =0D VtdUnitBaseAddress =3D VTdUnitInfo->VtdUnitBaseAddress;=0D =0D DEBUG ((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%x] \n", VtdUnitBase= Address));=0D =0D - DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable));=0D - MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) RootEntryTable)= ;=0D + //=0D + // Check TE was enabled or not.=0D + //=0D + TEWasEnabled =3D ((MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG) & B_GSTS= _REG_TE) =3D=3D B_GSTS_REG_TE);=0D =0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_SRTP);= =0D + if (TEWasEnabled && (VTdUnitInfo->ECapReg.Bits.ADMS =3D=3D 1) && PcdGetB= ool (PcdVTdSupportAbortDmaMode)) {=0D + //=0D + // For implementations reporting Enhanced SRTP Support (ESRTPS) field = as=0D + // Clear in the Capability register, software must not modify this fie= ld while=0D + // DMA remapping is active (TES=3D1 in Global Status register).=0D + //=0D + if (VTdUnitInfo->CapReg.Bits.ESRTPS =3D=3D 0) {=0D + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE);= =0D + }=0D +=0D + //=0D + // Enable ADM=0D + //=0D + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) (RootEntryTab= le | V_RTADDR_REG_TTM_ADM));=0D +=0D + DEBUG((DEBUG_INFO, "Enable Abort DMA Mode...\n"));=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE);=0D +=0D + } else {=0D + DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable));=0D + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) RootEntryTabl= e);=0D +=0D + }=0D =0D DEBUG ((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n"))= ;=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0);=0D - DEBUG ((DEBUG_INFO, "EnableDmar: R_GSTS_REG =3D 0x%x \n", Reg32));=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP);=0D =0D //=0D // Init DMAr Fault Event and Data registers=0D @@ -471,15 +546,19 @@ EnableDmar ( //=0D InvalidateIOTLB (VTdUnitInfo);=0D =0D + if (TEWasEnabled && (VTdUnitInfo->ECapReg.Bits.ADMS =3D=3D 1) && PcdGetB= ool (PcdVTdSupportAbortDmaMode)) {=0D + if (VTdUnitInfo->CapReg.Bits.ESRTPS =3D=3D 0) {=0D + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE);= =0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable));=0D + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64) RootEntryTabl= e);=0D + }=0D +=0D //=0D // Enable VTd=0D //=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_TE);=0D - DEBUG ((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n"));=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0);=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE);=0D =0D DEBUG ((DEBUG_INFO, "VTD () enabled!<<<<<<\n"));=0D =0D @@ -500,8 +579,6 @@ DisableDmar ( )=0D {=0D UINT32 Reg32;=0D - UINT32 Status;=0D - UINT32 Command;=0D =0D DEBUG ((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", VtdUnitBas= eAddress));=0D =0D @@ -516,28 +593,12 @@ DisableDmar ( //=0D // Set TE (Translation Enable: BIT31) of Global command register to zero= =0D //=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D - Command =3D (Status & ~B_GMCD_REG_TE);=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);=0D -=0D - //=0D - // Poll on TE Status bit of Global status register to become zero=0D - //=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE);=0D + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE);=0D =0D //=0D // Set SRTP (Set Root Table Pointer: BIT30) of Global command register i= n order to update the root table pointerDisable VTd=0D //=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D - Command =3D (Status | B_GMCD_REG_SRTP);=0D - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);=0D - do {=0D - Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0);=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP);=0D =0D Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32));=0D @@ -568,12 +629,12 @@ EnableVTdTranslationProtectionBlockDma ( =0D DEBUG ((DEBUG_INFO, "EnableVTdTranslationProtectionBlockDma - 0x%08x\n",= VtdUnitBaseAddress));=0D =0D - DEBUG ((DEBUG_INFO, "PcdVTdSupportAbortDmaMode : %d\n", FixedPcdGetBool = (PcdVTdSupportAbortDmaMode)));=0D + DEBUG ((DEBUG_INFO, "PcdVTdSupportAbortDmaMode : %d\n", PcdGetBool (PcdV= TdSupportAbortDmaMode)));=0D =0D ECapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_ECAP_REG);=0D DEBUG ((DEBUG_INFO, "ECapReg.ADMS : %d\n", ECapReg.Bits.ADMS));=0D =0D - if ((ECapReg.Bits.ADMS =3D=3D 1) && FixedPcdGetBool (PcdVTdSupportAbortD= maMode)) {=0D + if ((ECapReg.Bits.ADMS =3D=3D 1) && PcdGetBool (PcdVTdSupportAbortDmaMod= e)) {=0D //=0D // Use Abort DMA Mode=0D //=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTd= Dxe.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe= .inf index 387f90e37..b152831c0 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf @@ -75,6 +75,7 @@ [Pcd]=0D gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask ## CONSUMES=0D gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError ## CONSUMES=0D + gIntelSiliconPkgTokenSpaceGuid.PcdVTdSupportAbortDmaMode ## CONSUMES=0D =0D [Depex]=0D gEfiPciRootBridgeIoProtocolGuid=0D diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index c7a56cf57..396aa4a70 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -475,6 +475,92 @@ DisablePmr ( return ;=0D }=0D =0D +/**=0D + Clear Global Command Register Bits=0D +=0D + @param[in] VtdUnitBaseAddress The base address of the VTd engine.=0D + @param[in] BitMask Bit mask.=0D +**/=0D +VOID=0D +ClearGlobalCommandRegisterBits (=0D + IN UINTN VtdUnitBaseAddress,=0D + IN UINT32 BitMask=0D + )=0D +{=0D + UINT32 Reg32;=0D + UINT32 Status;=0D + UINT32 Command;=0D +=0D + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D + Command =3D (Status & (~BitMask));=0D + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);=0D +=0D + DEBUG((DEBUG_INFO, "Clear GCMD_REG bits 0x%x.\n", BitMask));=0D +=0D + //=0D + // Poll on Status bit of Global status register to become zero=0D + //=0D + do {=0D + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + } while ((Reg32 & BitMask) =3D=3D BitMask);=0D +}=0D +=0D +/**=0D + Set Global Command Register Bits=0D +=0D + @param[in] VtdUnitBaseAddress The base address of the VTd engine.=0D + @param[in] BitMask Bit mask.=0D +**/=0D +VOID=0D +SetGlobalCommandRegisterBits (=0D + IN UINTN VtdUnitBaseAddress,=0D + IN UINT32 BitMask=0D + )=0D +{=0D + UINT32 Reg32;=0D + UINT32 Status;=0D + UINT32 Command;=0D +=0D + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D + Command =3D (Status | BitMask);=0D + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command);=0D +=0D + DEBUG((DEBUG_INFO, "Set GCMD_REG bits 0x%x.\n", BitMask));=0D +=0D + //=0D + // Poll on Status bit of Global status register to become not zero=0D + //=0D + do {=0D + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG);=0D + } while ((Reg32 & BitMask) =3D=3D 0);=0D +}=0D +=0D +/**=0D + Update Root Table Address Register=0D +=0D + @param[in] VtdIndex The index used to identify a VTd engine.=0D + @param[in] EnableADM TRUE - Enable ADM in TTM bits=0D +**/=0D +VOID=0D +UpdateRootTableAddressRegister (=0D + IN UINTN VtdIndex,=0D + IN BOOLEAN EnableADM=0D + )=0D +{=0D + UINT64 Reg64;=0D +=0D + if (mVtdUnitInformation[VtdIndex].ExtRootEntryTable !=3D NULL) {=0D + DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[Vt= dIndex].ExtRootEntryTable));=0D + Reg64 =3D (UINT64)(UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTab= le | (EnableADM ? V_RTADDR_REG_TTM_ADM : BIT11);=0D + } else {=0D + DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[VtdIn= dex].RootEntryTable));=0D + Reg64 =3D (UINT64)(UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable = | (EnableADM ? V_RTADDR_REG_TTM_ADM : 0);=0D + }=0D + MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_RTADDR= _REG, Reg64);=0D +}=0D +=0D /**=0D Enable DMAR translation.=0D =0D @@ -488,25 +574,43 @@ EnableDmar ( {=0D UINTN Index;=0D UINT32 Reg32;=0D + UINTN VtdUnitBaseAddress;=0D + BOOLEAN TEWasEnabled;=0D =0D for (Index =3D 0; Index < mVtdUnitNumber; Index++) {=0D - DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] \n", Index));=0D + VtdUnitBaseAddress =3D mVtdUnitInformation[Index].VtdUnitBaseAddress;= =0D + DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] BAR [0x%x]\n", = Index, VtdUnitBaseAddress));=0D +=0D + //=0D + // Check TE was enabled or not.=0D + //=0D + TEWasEnabled =3D ((MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG) & B_GS= TS_REG_TE) =3D=3D B_GSTS_REG_TE);=0D +=0D + if (TEWasEnabled && (mVtdUnitInformation[Index].ECapReg.Bits.ADMS =3D= =3D 1) && PcdGetBool (PcdVTdSupportAbortDmaMode)) {=0D + //=0D + // For implementations reporting Enhanced SRTP Support (ESRTPS) fiel= d as=0D + // Clear in the Capability register, software must not modify this f= ield while=0D + // DMA remapping is active (TES=3D1 in Global Status register).=0D + //=0D + if (mVtdUnitInformation[Index].CapReg.Bits.ESRTPS =3D=3D 0) {=0D + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE)= ;=0D + }=0D +=0D + //=0D + // Enable ADM=0D + //=0D + UpdateRootTableAddressRegister (Index, TRUE);=0D +=0D + DEBUG((DEBUG_INFO, "Enable Abort DMA Mode...\n"));=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE);=0D =0D - if (mVtdUnitInformation[Index].ExtRootEntryTable !=3D NULL) {=0D - DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[= Index].ExtRootEntryTable));=0D - MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADD= R_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].ExtRootEntryTable | BIT11)= ;=0D } else {=0D - DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[Ind= ex].RootEntryTable));=0D - MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADD= R_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].RootEntryTable);=0D - }=0D + UpdateRootTableAddressRegister (Index, FALSE);=0D =0D - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG);=0D - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Reg32 | B_GMCD_REG_SRTP);=0D + }=0D =0D DEBUG((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n")= );=0D - do {=0D - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG);=0D - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0);=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_SRTP);=0D =0D //=0D // Init DMAr Fault Event and Data registers=0D @@ -528,15 +632,19 @@ EnableDmar ( //=0D InvalidateIOTLB (Index);=0D =0D + if (TEWasEnabled && (mVtdUnitInformation[Index].ECapReg.Bits.ADMS =3D= =3D 1) && PcdGetBool (PcdVTdSupportAbortDmaMode)) {=0D + if (mVtdUnitInformation[Index].CapReg.Bits.ESRTPS =3D=3D 0) {=0D + ClearGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE)= ;=0D + }=0D +=0D + UpdateRootTableAddressRegister (Index, FALSE);=0D + }=0D +=0D //=0D // Enable VTd=0D //=0D - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG);=0D - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Reg32 | B_GMCD_REG_TE);=0D - DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n"));=0D - do {=0D - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0);=0D + DEBUG ((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n"));=0D + SetGlobalCommandRegisterBits (VtdUnitBaseAddress, B_GMCD_REG_TE);=0D =0D DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index));=0D }=0D @@ -565,8 +673,6 @@ DisableDmar ( UINTN Index;=0D UINTN SubIndex;=0D UINT32 Reg32;=0D - UINT32 Status;=0D - UINT32 Command;=0D =0D for (Index =3D 0; Index < mVtdUnitNumber; Index++) {=0D DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index));= =0D @@ -582,32 +688,15 @@ DisableDmar ( //=0D // Set TE (Translation Enable: BIT31) of Global command register to ze= ro=0D //=0D - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG);=0D - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D - Command =3D (Status & ~B_GMCD_REG_TE);=0D - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command);=0D -=0D - //=0D - // Poll on TE Status bit of Global status register to become zero=0D - //=0D - do {=0D - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG);=0D - } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE);=0D + ClearGlobalCommandRegisterBits (mVtdUnitInformation[Index].VtdUnitBase= Address, B_GMCD_REG_TE);=0D =0D //=0D // Set SRTP (Set Root Table Pointer: BIT30) of Global command register= in order to update the root table pointerDisable VTd=0D //=0D - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG);=0D - Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits=0D - Command =3D (Status | B_GMCD_REG_SRTP);=0D - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command);=0D -=0D - do {=0D - Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG);=0D - } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0);=0D + SetGlobalCommandRegisterBits (mVtdUnitInformation[Index].VtdUnitBaseAd= dress, B_GSTS_REG_RTPS);=0D =0D Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG);=0D - DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32));=0D + DEBUG ((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32));=0D =0D DEBUG ((DEBUG_INFO,"VTD (%d) Disabled!<<<<<<\n",Index));=0D =0D diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index c36d130a0..9166e599a 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -135,12 +135,6 @@ gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32= |0x0000000A=0D gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|0x00660000|UINT= 32|0x0000000B=0D =0D - ## Indicates if VTd Abort DMA Mode is supported.

=0D - # TRUE - Support VTd abort DMA mode.=0D - # FALSE - Not support VTd abort DMA mode.=0D - # @Prompt VTd abort DMA mode support.=0D - gIntelSiliconPkgTokenSpaceGuid.PcdVTdSupportAbortDmaMode|FALSE|BOOLEAN|0= x0000000C=0D -=0D [PcdsFixedAtBuild, PcdsPatchableInModule]=0D ## Error code for VTd error.

=0D # EDKII_ERROR_CODE_VTD_ERROR =3D (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPE= CIFIC | 0x00000000)) =3D 0x02008000
=0D @@ -178,3 +172,9 @@ # @Prompt The VTd PEI DMA buffer size for S3.=0D gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000|UINT3= 2|0x00000004=0D =0D + ## Indicates if VTd Abort DMA Mode is supported.

=0D + # TRUE - Support VTd abort DMA mode.=0D + # FALSE - Not support VTd abort DMA mode.=0D + # @Prompt VTd abort DMA mode support.=0D + gIntelSiliconPkgTokenSpaceGuid.PcdVTdSupportAbortDmaMode|FALSE|BOOLEAN|0= x0000000C=0D +=0D --=20 2.26.2.windows.1