From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web08.240.1662476812674215756 for ; Tue, 06 Sep 2022 08:06:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=LB68U0HP; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id DFA2061561; Tue, 6 Sep 2022 15:06:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C492C433C1; Tue, 6 Sep 2022 15:06:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662476811; bh=DF3EeJWuWWcp4NnEzYbeC3QUQd3sdkGBN4Vr3vmbXl0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LB68U0HP6VUZ6cF7l993OV1xnZPR7aY4+Dv8UU2f3yPXV9UJhJVVkw7azLS6nmVce ng0el5Bq4cREQ7OF9Vmdjx/H1NZRWVMztP6sfgD8ujZ7+vCM3RwL4xK2wZ7lfHAvUD hgqNsYVgfYuRjAGma8Vc2CAIkJyq43j31K3bATwjzBzglJ61Mcs5uKR3jSVhBKVYIk 5Zujpw7BmQ2lkfoTPMPYDiWJ3JN/ya4pGDXLMIhL3I9Qgcf0p/7AW0W9JojZ5v9byh xUVT5LNw7gXWOfth/ymKYSAYgyPOQQNrnmGeiI+BuGUVUmVUPe+FkYmS8pAJyy+q9Q MhpToiVIqHxKg== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [PATCH v2 3/7] ArmPkg/ArmMmuLib: permit initial configuration with MMU enabled Date: Tue, 6 Sep 2022 17:06:35 +0200 Message-Id: <20220906150639.157227-4-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220906150639.157227-1-ardb@kernel.org> References: <20220906150639.157227-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Permit the use of this library with the MMU and caches already enabled. This removes the need for any cache maintenance for coherency, and is generally better for robustness and performance, especially when running under virtualization. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 30 +++++++++++--------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 747ebc533511..ebd39ab4a657 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -689,14 +689,16 @@ ArmConfigureMmu ( *TranslationTableSize =3D RootTableEntryCount * sizeof (UINT64);=0D }=0D =0D - //=0D - // Make sure we are not inadvertently hitting in the caches=0D - // when populating the page tables.=0D - //=0D - InvalidateDataCacheRange (=0D - TranslationTable,=0D - RootTableEntryCount * sizeof (UINT64)=0D - );=0D + if (!ArmMmuEnabled ()) {=0D + //=0D + // Make sure we are not inadvertently hitting in the caches=0D + // when populating the page tables.=0D + //=0D + InvalidateDataCacheRange (=0D + TranslationTable,=0D + RootTableEntryCount * sizeof (UINT64)=0D + );=0D + }=0D =0D ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));=0D =0D @@ -722,12 +724,14 @@ ArmConfigureMmu ( =0D ArmSetTTBR0 (TranslationTable);=0D =0D - ArmDisableAlignmentCheck ();=0D - ArmEnableStackAlignmentCheck ();=0D - ArmEnableInstructionCache ();=0D - ArmEnableDataCache ();=0D + if (!ArmMmuEnabled ()) {=0D + ArmDisableAlignmentCheck ();=0D + ArmEnableStackAlignmentCheck ();=0D + ArmEnableInstructionCache ();=0D + ArmEnableDataCache ();=0D =0D - ArmEnableMmu ();=0D + ArmEnableMmu ();=0D + }=0D =0D if (NumRootPages > 1) {=0D //=0D --=20 2.35.1