From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web11.249.1662476813719122373 for ; Tue, 06 Sep 2022 08:06:53 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=HZ22LwBZ; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E440C61584; Tue, 6 Sep 2022 15:06:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B53A0C433B5; Tue, 6 Sep 2022 15:06:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1662476812; bh=yQm2T86Pe9CM6RwF6HnFRpze7cr5TYDR8iiOPX9tcDQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HZ22LwBZpisdRYzjSa9J7mTZ49j5ZrZiHwXnBud6xatFYDF8vqZ9p4oNZdIhpaIAh GR3fmkZWQ9SajZAmvIcMHy8yawKaizZUWu/wz+44N56qbwAgNFvmBH2bK/NMzQNCFv ZJ6ugQPXNUd75V+MItkZ9KJptXThGLATWo/FZ66WGl8CNkPayT/nGk++z/LHJH7lnv 2NE1CFzrt94fU2gXH1mQ7BbUnTH2mwFJDk8XZWkMMaex8Hn6v6TiPZ3TbMOqEqhvKI xTSp0dqT6IPyPZWeJlLO7oSyJA7H9R/Ke0WEQXZeY9xo21LSH+E5jioEOJQbKOqqtt cfF1xvdKKYUfA== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: quic_llindhol@quicinc.com, sami.mujawar@arm.com, Ard Biesheuvel Subject: [PATCH v2 4/7] ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled Date: Tue, 6 Sep 2022 17:06:36 +0200 Message-Id: <20220906150639.157227-5-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220906150639.157227-1-ardb@kernel.org> References: <20220906150639.157227-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Some platforms may set up a preliminary ID map in flash and enter EFI with the MMU and caches enabled, as this removes a lot of the complexity around cache coherency. Let's take this into account, and avoid touching the MMU controls or perform cache invalidation when the MMU is enabled at entry. Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 22 +++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePei= Core/PrePeiCore.c index 9c4b25df953d..8b86c6e69abd 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -58,17 +58,19 @@ CEntryPoint ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint=0D )=0D {=0D - // Data Cache enabled on Primary core when MMU is enabled.=0D - ArmDisableDataCache ();=0D - // Invalidate instruction cache=0D - ArmInvalidateInstructionCache ();=0D - // Enable Instruction Caches on all cores.=0D - ArmEnableInstructionCache ();=0D + if (!ArmMmuEnabled ()) {=0D + // Data Cache enabled on Primary core when MMU is enabled.=0D + ArmDisableDataCache ();=0D + // Invalidate instruction cache=0D + ArmInvalidateInstructionCache ();=0D + // Enable Instruction Caches on all cores.=0D + ArmEnableInstructionCache ();=0D =0D - InvalidateDataCacheRange (=0D - (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),=0D - PcdGet32 (PcdCPUCorePrimaryStackSize)=0D - );=0D + InvalidateDataCacheRange (=0D + (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),=0D + PcdGet32 (PcdCPUCorePrimaryStackSize)=0D + );=0D + }=0D =0D //=0D // Note: Doesn't have to Enable CPU interface in non-secure world,=0D --=20 2.35.1