From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) by mx.groups.io with SMTP id smtpd.web12.1920.1662484196270131114 for ; Tue, 06 Sep 2022 10:09:56 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=jm5mjC9W; spf=pass (domain: ventanamicro.com, ip: 209.85.216.52, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f52.google.com with SMTP id q3so11978493pjg.3 for ; Tue, 06 Sep 2022 10:09:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=3Mr3nWwZcAYbMy0odOeICZjvxLHX2Qwv7hqghHefuCU=; b=jm5mjC9WDsD12vkmv5djkIIrT5L7JcdcnzFZgru2fRdyERT5i0Gr6u7oLkzYHgxRoR Fr7D1VJ+wopgsLRYXrHTOEx/BippSoZig02WvVFrWV/06Ll3F4dSIrHl1/mO8ilJkrUs HEv213aosgPM3yoQv2Uwd0Wu9BVbMMhtFbhVj8H0fkh+m1EqAJDlpdjL62QPApY6llIX f1zB5V5QIlyrF85yyrzVhA4oNBgo1pBrrKMR4Zups9ybjznLHnvGw1LmlIh1pHSzquHj EBaPU5O8d0eTlkhJyEUW28++V1+TG/WafDR4gDKUWGM06HmaI7Vss3Ex3ynzx0GrB35I 8yzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=3Mr3nWwZcAYbMy0odOeICZjvxLHX2Qwv7hqghHefuCU=; b=JpRppkin019aUS6fBpwufsvOExFPN9GJawbu0jl+0KUl0F2bOAaBli+Bv5HCOn4fxV 1kbUcGQaO1S5dMarj9pqoUqgvtP2+4Akk0RmbRVt9uvoUPSCnw7kUz2JjHe9mQ+a8MyF sxzTgeGnQ5Fm4hzq6T+IBYYla6lx/6ylgSdaI41WpbLikDQwaN0733ouJllYT4Cvjpjg voFeCwNsvl3O2s3wzaarI8BvV44pXZQ8kKXfUsdvw9jsK4W56bA6GwRfXVjwan7sFn9j OhInB2mfassMDXZX18BYvjv0+I9B530L8rjuSZjQLXLVlhJeIi325JQOC/PWdSeVfiA5 VdVQ== X-Gm-Message-State: ACgBeo1XrLK+eP9mbd856XPRSbEqYWAV93lCG0b7z0IgglSIZKrqEmwE HDtRBnHYYJVjxTpXRv+AWT/lWcROzSBNpdB6 X-Google-Smtp-Source: AA6agR6s2S72ZcileFGaOS2ZCO4IvFpqR0NwkKDrUJjNP1HxZ6xhDHqfzqTL35VUg4YYbeeDHrcAXQ== X-Received: by 2002:a17:90b:33c9:b0:200:9ec2:f2eb with SMTP id lk9-20020a17090b33c900b002009ec2f2ebmr4377226pjb.29.1662484194992; Tue, 06 Sep 2022 10:09:54 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:54 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [RFC PATCH 14/17] MdeModulePkg/Universal: Add PlatformPei module for RISC-V Date: Tue, 6 Sep 2022 22:38:34 +0530 Message-Id: <20220906170837.491525-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Thie PEIM is required to do platform specific initialization like detecting the permanent memory and install memory HOB, install the FDT Hob etc. Signed-off-by: Sunil V L --- .../Universal/PlatformPei/PlatformPei.inf | 65 +++ .../Universal/PlatformPei/RiscV64/Fv.c | 83 ++++ .../Universal/PlatformPei/RiscV64/MemDetect.c | 179 +++++++++ .../Universal/PlatformPei/RiscV64/Platform.c | 372 ++++++++++++++++++ .../Universal/PlatformPei/RiscV64/Platform.h | 97 +++++ 5 files changed, 796 insertions(+) create mode 100644 MdeModulePkg/Universal/PlatformPei/PlatformPei.inf create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h diff --git a/MdeModulePkg/Universal/PlatformPei/PlatformPei.inf b/MdeModule= Pkg/Universal/PlatformPei/PlatformPei.inf new file mode 100644 index 0000000000..220f4a7ee5 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/PlatformPei.inf @@ -0,0 +1,65 @@ +## @file=0D +# Platform PEI driver=0D +#=0D +# This module provides platform specific functions=0D +#=0D +# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x0001001b=0D + BASE_NAME =3D PlatformPei=0D + FILE_GUID =3D 0F26B9AF-3E38-46E8-9D35-0318E903E049= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D InitializePlatform=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D RISCV64=0D +#=0D +=0D +[Sources]=0D + RiscV64/Fv.c=0D + RiscV64/MemDetect.c=0D + RiscV64/Platform.c=0D + RiscV64/Platform.h=0D +=0D +[Packages]=0D + EmbeddedPkg/EmbeddedPkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MdePkg/MdePkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D +=0D +[Guids]=0D + gEfiMemoryTypeInformationGuid=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + HobLib=0D + FdtLib=0D + IoLib=0D + PcdLib=0D + PeimEntryPoint=0D + PeiResourcePublicationLib=0D + PlatformPeiLib=0D +=0D +[LibraryClasses.RISCV64]=0D + RiscVSbiLib=0D +=0D +[Pcd.RISCV64]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvBase=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiMemFvSize=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvBase=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeMemFvSize=0D +=0D +[Ppis]=0D + gEfiPeiMasterBootModePpiGuid=0D +=0D +[Depex]=0D + TRUE=0D diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c b/MdeModulePkg= /Universal/PlatformPei/RiscV64/Fv.c new file mode 100644 index 0000000000..15e77fcf7e --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c @@ -0,0 +1,83 @@ +/** @file=0D + Build FV related hobs for platform.=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "PiPei.h"=0D +#include "Platform.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Publish PEI & DXE (Decompressed) Memory based FVs to let PEI=0D + and DXE know about them.=0D +=0D + @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +PeiFvInitialization (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n"));=0D +=0D + // Create a memory allocation HOB for the DXE FV.=0D + //=0D + // If "secure" S3 is needed, then SEC will decompress both PEI and DXE=0D + // firmware volumes at S3 resume too, hence we need to keep away the OS = from=0D + // DXEFV as well. Otherwise we only need to keep away DXE itself from th= e=0D + // DXEFV area.=0D + //=0D + BuildMemoryAllocationHob (=0D + PcdGet32 (PcdPeiMemFvBase),=0D + PcdGet32 (PcdPeiMemFvSize),=0D + EfiBootServicesData=0D + );=0D +=0D +=0D + //=0D + // Let DXE know about the DXE FV=0D + //=0D + BuildFvHob (PcdGet32 (PcdDxeMemFvBase), PcdGet32 (PcdDxeMemFvSize));=0D + DEBUG ((=0D + DEBUG_INFO,=0D + "Platform builds DXE FV at %x, size %x.\n",=0D + PcdGet32 (PcdDxeMemFvBase),=0D + PcdGet32 (PcdDxeMemFvSize)=0D + ));=0D +=0D + // Create a memory allocation HOB for the DXE FV.=0D + //=0D + // If "secure" S3 is needed, then SEC will decompress both PEI and DXE=0D + // firmware volumes at S3 resume too, hence we need to keep away the OS = from=0D + // DXEFV as well. Otherwise we only need to keep away DXE itself from th= e=0D + // DXEFV area.=0D + //=0D + BuildMemoryAllocationHob (=0D + PcdGet32 (PcdDxeMemFvBase),=0D + PcdGet32 (PcdDxeMemFvSize),=0D + EfiBootServicesData=0D + );=0D +=0D + //=0D + // Let PEI know about the DXE FV so it can find the DXE Core=0D + //=0D + PeiServicesInstallFvInfoPpi (=0D + NULL,=0D + (VOID *)(UINTN)PcdGet32 (PcdDxeMemFvBase),=0D + PcdGet32 (PcdDxeMemFvSize),=0D + NULL,=0D + NULL=0D + );=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c b/MdeMo= dulePkg/Universal/PlatformPei/RiscV64/MemDetect.c new file mode 100644 index 0000000000..3ebd29eba6 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c @@ -0,0 +1,179 @@ +/** @file=0D + Memory Detection for Virtual Machines.=0D +=0D + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +Module Name:=0D +=0D + MemDetect.c=0D +=0D +**/=0D +=0D +//=0D +// The package level header files this module uses=0D +//=0D +#include =0D +=0D +//=0D +// The Library classes this module consumes=0D +//=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +#include =0D +=0D +#include "Platform.h"=0D +=0D +STATIC EFI_PHYSICAL_ADDRESS SystemMemoryBase;=0D +STATIC UINT64 SystemMemorySize;=0D +STATIC EFI_PHYSICAL_ADDRESS MmodeResvBase;=0D +STATIC UINT64 MmodeResvSize;=0D +=0D +/**=0D + Publish PEI core memory.=0D +=0D + @return EFI_SUCCESS The PEIM initialized successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +PublishPeiMemory (=0D + VOID=0D + )=0D +{=0D + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;=0D + EFI_PHYSICAL_ADDRESS MemoryBase;=0D + CONST UINT64 *RegProp;=0D + CONST CHAR8 *Type;=0D + EFI_STATUS Status;=0D + UINT64 CurBase, CurSize;=0D + UINT64 NewBase =3D 0, NewSize =3D 0;=0D + UINT64 MemorySize;=0D + INT32 Node, Prev;=0D + INT32 Len;=0D + VOID *FdtPointer;=0D +=0D + FirmwareContext =3D NULL;=0D + GetFirmwareContextPointer (&FirmwareContext);=0D +=0D + if (FirmwareContext =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "%a: Firmware Context is NULL\n", __FUNCTION__));= =0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + FdtPointer =3D (VOID *)FirmwareContext->FlattenedDeviceTree;=0D + if (FdtPointer =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __FUNCTION__));=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + // Look for the lowest memory node=0D + for (Prev =3D 0;; Prev =3D Node) {=0D + Node =3D fdt_next_node (FdtPointer, Prev, NULL);=0D + if (Node < 0) {=0D + break;=0D + }=0D + // Check for memory node=0D + Type =3D fdt_getprop (FdtPointer, Node, "device_type", &Len);=0D + if (Type && AsciiStrnCmp (Type, "memory", Len) =3D=3D 0) {=0D + // Get the 'reg' property of this node. For now, we will assume=0D + // two 8 byte quantities for base and size, respectively.=0D + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len);=0D + if (RegProp !=3D 0 && Len =3D=3D (2 * sizeof (UINT64))) {=0D +=0D + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp));=0D + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));=0D +=0D + DEBUG ((DEBUG_INFO, "%a: System RAM @ 0x%lx - 0x%lx\n",=0D + __FUNCTION__, CurBase, CurBase + CurSize - 1));=0D +=0D + if (NewBase > CurBase || NewBase =3D=3D 0) {=0D + NewBase =3D CurBase;=0D + NewSize =3D CurSize;=0D + }=0D + } else {=0D + DEBUG ((DEBUG_ERROR, "%a: Failed to parse FDT memory node\n",=0D + __FUNCTION__));=0D + }=0D + }=0D + }=0D +=0D + SystemMemoryBase =3D NewBase;=0D + SystemMemorySize =3D NewSize;=0D +=0D + /* try to locate the reserved memory opensbi node */=0D + Node =3D fdt_path_offset(FdtPointer, "/reserved-memory/mmode_resv0");=0D + if (Node >=3D 0) {=0D + RegProp =3D fdt_getprop (FdtPointer, Node, "reg", &Len);=0D + if (RegProp !=3D 0 && Len =3D=3D (2 * sizeof (UINT64))) {=0D + NewBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp));=0D + NewSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1));=0D + DEBUG ((DEBUG_INFO, "%a: M-mode Base =3D 0x%lx, M-mode Size =3D 0x%l= x\n",=0D + __FUNCTION__, NewBase, NewSize));=0D + MmodeResvBase =3D NewBase;=0D + MmodeResvSize =3D NewSize;=0D + }=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "%a: SystemMemoryBase:0x%x SystemMemorySize:%x\n",=0D + __FUNCTION__, SystemMemoryBase, SystemMemorySize));=0D +=0D + //=0D + // Initial 16MB needs to be reserved=0D + //=0D + MemoryBase =3D SystemMemoryBase + SIZE_16MB;=0D + MemorySize =3D SystemMemorySize - SIZE_16MB;=0D +=0D + //=0D + // Publish this memory to the PEI Core=0D + //=0D + Status =3D PublishSystemMemory (MemoryBase, MemorySize);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Publish system RAM and reserve memory regions.=0D +=0D +**/=0D +VOID=0D +InitializeRamRegions (=0D + VOID=0D + )=0D +{=0D + /*=0D + * M-mode FW can be loaded anywhere in memory but should not overlap=0D + * with the EDK2. This can happen if some other boot code loads the=0D + * M-mode firmware.=0D + *=0D + * The M-mode firmware memory should be marked as reserved memory=0D + * so that OS doesn't use it.=0D + */=0D + DEBUG ((DEBUG_INFO, "%a: M-mode FW Memory Start:0x%lx End:0x%lx\n",=0D + __FUNCTION__, MmodeResvBase, MmodeResvBase + MmodeResvSize));= =0D + AddReservedMemoryBaseSizeHob(MmodeResvBase, MmodeResvSize);=0D +=0D + if (MmodeResvBase > SystemMemoryBase) {=0D + DEBUG ((DEBUG_INFO, "%a: Free Memory Start:0x%lx End:0x%lx\n",=0D + __FUNCTION__, SystemMemoryBase, MmodeResvBase));=0D + AddMemoryRangeHob(SystemMemoryBase, MmodeResvBase);=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "%a: Free Memory Start:0x%lx End:0x%lx\n",=0D + __FUNCTION__, MmodeResvBase + MmodeResvSize,=0D + SystemMemoryBase + SystemMemorySize));=0D + AddMemoryRangeHob(MmodeResvBase + MmodeResvSize,=0D + SystemMemoryBase + SystemMemorySize);=0D +}=0D diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c b/MdeMod= ulePkg/Universal/PlatformPei/RiscV64/Platform.c new file mode 100644 index 0000000000..27d50a0e56 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c @@ -0,0 +1,372 @@ +/** @file=0D + Platform PEI driver=0D +=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
=0D + Copyright (c) 2011, Andrei Warkentin =0D + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +//=0D +// The package level header files this module uses=0D +//=0D +#include =0D +=0D +//=0D +// The Library classes this module consumes=0D +//=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "Platform.h"=0D +=0D +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] =3D {=0D + { EfiACPIMemoryNVS, 0x004 },=0D + { EfiACPIReclaimMemory, 0x008 },=0D + { EfiReservedMemoryType, 0x004 },=0D + { EfiRuntimeServicesData, 0x024 },=0D + { EfiRuntimeServicesCode, 0x030 },=0D + { EfiBootServicesCode, 0x180 },=0D + { EfiBootServicesData, 0xF00 },=0D + { EfiMaxMemoryType, 0x000 }=0D +};=0D +=0D +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D {=0D + {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,=0D + &gEfiPeiMasterBootModePpiGuid,=0D + NULL=0D + }=0D +};=0D +=0D +STATIC EFI_BOOT_MODE mBootMode =3D BOOT_WITH_FULL_CONFIGURATION;=0D +=0D +/**=0D + Build memory map I/O range resource HOB using the=0D + base address and size.=0D +=0D + @param MemoryBase Memory map I/O base.=0D + @param MemorySize Memory map I/O size.=0D +=0D +**/=0D +VOID=0D +AddIoMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_MAPPED_IO,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +/**=0D + Build reserved memory range resource HOB.=0D +=0D + @param MemoryBase Reserved memory range base address.=0D + @param MemorySize Reserved memory range size.=0D +=0D +**/=0D +VOID=0D +AddReservedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_RESERVED,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +/**=0D + Build memory map I/O resource using the base address=0D + and the top address of memory range.=0D +=0D + @param MemoryBase Memory map I/O range base address.=0D + @param MemoryLimit The top address of memory map I/O range=0D +=0D +**/=0D +VOID=0D +AddIoMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + )=0D +{=0D + AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));= =0D +}=0D +=0D +/**=0D + Create memory range resource HOB using the memory base=0D + address and size.=0D +=0D + @param MemoryBase Memory range base address.=0D + @param MemorySize Memory range size.=0D +=0D +**/=0D +VOID=0D +AddMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_SYSTEM_MEMORY,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +/**=0D + Create memory range resource HOB using memory base=0D + address and top address of the memory range.=0D +=0D + @param MemoryBase Memory range base address.=0D + @param MemoryLimit Memory range size.=0D +=0D +**/=0D +VOID=0D +AddMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + )=0D +{=0D + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));=0D +}=0D +=0D +/**=0D + Create untested memory range resource HOB using memory base=0D + address and top address of the memory range.=0D +=0D + @param MemoryBase Memory range base address.=0D + @param MemorySize Memory range size.=0D +=0D +**/=0D +VOID=0D +AddUntestedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + )=0D +{=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_SYSTEM_MEMORY,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE,=0D + MemoryBase,=0D + MemorySize=0D + );=0D +}=0D +=0D +/**=0D + Create untested memory range resource HOB using memory base=0D + address and top address of the memory range.=0D +=0D + @param MemoryBase Memory range base address.=0D + @param MemoryLimit Memory range size.=0D +=0D +**/=0D +VOID=0D +AddUntestedMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + )=0D +{=0D + AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase));=0D +}=0D +=0D +/**=0D + Add PCI resource.=0D +=0D +**/=0D +VOID=0D +AddPciResource (=0D + VOID=0D + )=0D +{=0D + //=0D + // Platform-specific=0D + //=0D +}=0D +=0D +/**=0D + Platform memory map initialization.=0D +=0D +**/=0D +VOID=0D +MemMapInitialization (=0D + VOID=0D + )=0D +{=0D + //=0D + // Create Memory Type Information HOB=0D + //=0D + BuildGuidDataHob (=0D + &gEfiMemoryTypeInformationGuid,=0D + mDefaultMemoryTypeInformation,=0D + sizeof (mDefaultMemoryTypeInformation)=0D + );=0D +=0D + //=0D + // Add PCI IO Port space available for PCI resource allocations.=0D + //=0D + AddPciResource ();=0D +}=0D +=0D +/**=0D + Platform misc initialization.=0D +=0D +**/=0D +VOID=0D +MiscInitialization (=0D + VOID=0D + )=0D +{=0D + //=0D + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits=0D + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing=0D + // S3 resume as well, so we build it unconditionally.)=0D + //=0D + // TODO: Determine this dynamically from the platform=0D + // setting or the HART configuration.=0D + //=0D + BuildCpuHob (56, 32);=0D +}=0D +=0D +/**=0D + Check if system returns from S3.=0D +=0D + @return BOOLEAN TRUE, system returned from S3=0D + FALSE, system is not returned from S3=0D +=0D +**/=0D +BOOLEAN=0D +CheckResumeFromS3 (=0D + VOID=0D + )=0D +{=0D + //=0D + // Platform implementation-specific=0D + //=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Platform boot mode initialization.=0D +=0D +**/=0D +VOID=0D +BootModeInitialization (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + if (CheckResumeFromS3()) {=0D + DEBUG ((DEBUG_INFO, "This is wake from S3\n"));=0D + } else {=0D + DEBUG ((DEBUG_INFO, "This is normal boot\n"));=0D + }=0D +=0D + Status =3D PeiServicesSetBootMode (mBootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D PeiServicesInstallPpi (mPpiBootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +}=0D +=0D +/**=0D + Build processor information for U54 Coreplex processor.=0D +=0D + @return EFI_SUCCESS Status.=0D +=0D +**/=0D +EFI_STATUS=0D +BuildCoreInformationHob (=0D + VOID=0D + )=0D +{=0D +// return BuildRiscVSmbiosHobs ();=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Perform Platform PEI initialization.=0D +=0D + @param FileHandle Handle of the file being invoked.=0D + @param PeiServices Describes the list of possible PEI Services.=0D +=0D + @return EFI_SUCCESS The PEIM initialized successfully.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializePlatform (=0D + IN EFI_PEI_FILE_HANDLE FileHandle,=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n"));=0D + Status =3D PlatformPeim();=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "PlatformPeim failed\n"));=0D + ASSERT (FALSE);=0D + }=0D + BootModeInitialization ();=0D + DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n"));=0D + PublishPeiMemory ();=0D + DEBUG ((DEBUG_INFO, "PEI memory published.\n"));=0D + InitializeRamRegions ();=0D + DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n"));=0D +=0D + if (mBootMode !=3D BOOT_ON_S3_RESUME) {=0D + PeiFvInitialization ();=0D + MemMapInitialization ();=0D + }=0D +=0D + MiscInitialization ();=0D + Status =3D BuildCoreInformationHob ();=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "Fail to build processor information HOB.\n"));=0D + ASSERT (FALSE);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h b/MdeMod= ulePkg/Universal/PlatformPei/RiscV64/Platform.h new file mode 100644 index 0000000000..6c23c722a3 --- /dev/null +++ b/MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h @@ -0,0 +1,97 @@ +/** @file=0D + Platform PEI module include file.=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef PLATFORM_PEI_H_INCLUDED_=0D +#define PLATFORM_PEI_H_INCLUDED_=0D +=0D +VOID=0D +AddIoMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddIoMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + );=0D +=0D +VOID=0D +AddMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + );=0D +=0D +VOID=0D +AddUntestedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddReservedMemoryBaseSizeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + UINT64 MemorySize=0D + );=0D +=0D +VOID=0D +AddUntestedMemoryRangeHob (=0D + EFI_PHYSICAL_ADDRESS MemoryBase,=0D + EFI_PHYSICAL_ADDRESS MemoryLimit=0D + );=0D +=0D +VOID=0D +AddressWidthInitialization (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +PublishPeiMemory (=0D + VOID=0D + );=0D +=0D +UINT32=0D +GetSystemMemorySizeBelow4gb (=0D + VOID=0D + );=0D +=0D +VOID=0D +InitializeRamRegions (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +PeiFvInitialization (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +InitializeXen (=0D + VOID=0D + );=0D +=0D +/**=0D + Build processor and platform information for the U5 platform=0D +=0D + @return EFI_SUCCESS Status.=0D +=0D +**/=0D +EFI_STATUS=0D +BuildRiscVSmbiosHobs (=0D + VOID=0D + );=0D +=0D +#endif // _PLATFORM_PEI_H_INCLUDED_=0D --=20 2.25.1