From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) by mx.groups.io with SMTP id smtpd.web12.1928.1662484206141079667 for ; Tue, 06 Sep 2022 10:10:06 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=FPjVfmCW; spf=pass (domain: ventanamicro.com, ip: 209.85.216.52, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f52.google.com with SMTP id z9-20020a17090a468900b001ffff693b27so10651906pjf.2 for ; Tue, 06 Sep 2022 10:10:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=29gBgOWtiElR9JZ1ubSEnCweuC4ofU/KfE5aBliXrUo=; b=FPjVfmCWgLT5+gjefm+HKTs33rI+aJxyruGh7rFlsMqhWVdrn1BfrCLKEUr4/cpzPY 6uTQPPTptxPo8yTGXDraV/EiJTwmpkkruDwDgctQkEDB8K4iTcK7l7vqMpuJ3jrELhyl ChsypjMQ4aZcGkmjPDqLsHZv9rr5pJ9cIxD2Qw2DrdmNUCt2PIYOrZJjZo2CYXt+zN9e r1R3wcPPAa51byVky9tTDhmLFneSwPPMcDceW/9L4BJPFjxAGg2PRGTU2yoZ942i4Oje VuKFYuddG+8Dm29Jqu8P7gUqiNFyoF31Wm2WJ/UbYzZ/4oiPU+XdWROjGtLZ6JruYqq1 kgkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=29gBgOWtiElR9JZ1ubSEnCweuC4ofU/KfE5aBliXrUo=; b=F4lqTJy/xlJXo+DVz0sMhHrkEC8DQCid8Rfq4sL079J8JMq2NxN8KwA+GGkuXHZZOd ZM9V93NJ9QNuux3Zv4jkNO7PPkgMxNpJW248+s+a1SIz9pXziqXSUGRXwJVt//SL2U39 1QMLSQOQx4ef6/T61Ih/6oMeAo+1Q5rkDxW1HuUQM3o1GFtBXL6wnPOW5MBr6EAXGA2Z Jlru0/MqwwYZvjtZAai66c98uAdNPN04fgdAV/1T0jl69S1c5qpgsrDWrZt2lOhrJAQR f7dG2N9/Wfg8nnunTNkOpIePWj3XJRg6yd1E0ce3mxW1smI4vKfJswrnVSnLoyfJmdze YbZQ== X-Gm-Message-State: ACgBeo2BuJ5CnLvPTWJdtVepFqL7bsEXghgR3Nv+B3izCaMsY2lFzKHh NdZHBiFCADz414b5Fkc81/2bsbaHmCcTSrWM X-Google-Smtp-Source: AA6agR7irAA5piJJIF+NiBRlna5BZQrrhV4/5EMrd+RmKBcdnfGF1sLm5HjGlJiuTeYVZkRr0xKogw== X-Received: by 2002:a17:90b:3b92:b0:200:ad6a:d762 with SMTP id pc18-20020a17090b3b9200b00200ad6ad762mr1799928pjb.227.1662484205073; Tue, 06 Sep 2022 10:10:05 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.10.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:10:04 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Date: Tue, 6 Sep 2022 22:38:36 +0530 Message-Id: <20220906170837.491525-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This DXE module initializes the RISC-V CPU by installing the CPU specific ARCH protocol handlers. This also initializes the RISCV_EFI_BOOT_PROTOCOL which is required on RISC-V platforms. Signed-off-by: Sunil V L --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 16 +- UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337 +++++++++++++++++++++++++++++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++++++++++++++ 3 files changed, 552 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 4f2ea42f16..17cf2b1ecd 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -1,8 +1,12 @@ ## @file=0D -# CPU driver installs CPU Architecture Protocol and CPU MP protocol.=0D +# On X86, CPU driver installs CPU Architecture Protocol and CPU MP protoc= ol.=0D +#=0D +# On RISC-V, CPU driver installs CPU Architecture Protocol and RISC-V boo= t=0D +# protocol=0D #=0D # Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
= =0D # Copyright (c) 2017, AMD Incorporated. All rights reserved.
=0D +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -44,6 +48,9 @@ MtrrLib=0D UefiCpuLib=0D =0D +[LibraryClasses.RISCV64]=0D + RiscVSbiLib=0D +=0D [Sources.IA32, Sources.X64]=0D CpuDxe.c=0D CpuDxe.h=0D @@ -62,11 +69,18 @@ X64/CpuAsm.nasm=0D X64/PagingAttribute.c=0D =0D +[Sources.RISCV64]=0D + RiscV64/CpuDxe.c=0D + RiscV64/CpuDxe.h=0D +=0D [Protocols]=0D gEfiCpuArchProtocolGuid ## PRODUCES=0D gEfiMpServiceProtocolGuid ## PRODUCES=0D gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES=0D =0D +[Protocols.RISCV64]=0D + gRiscVEfiBootProtocolGuid ## PRODUCES=0D +=0D [Guids]=0D gIdleLoopEventGuid ## CONSUMES ## E= vent=0D gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ## S= ystemTable=0D diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.c new file mode 100644 index 0000000000..4112b6b8c6 --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -0,0 +1,337 @@ +/** @file=0D + RISC-V CPU DXE driver.=0D +=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include "CpuDxe.h"=0D +=0D +//=0D +// Global Variables=0D +//=0D +STATIC BOOLEAN mInterruptState =3D FALSE;=0D +STATIC EFI_HANDLE mCpuHandle =3D NULL;=0D +STATIC UINTN mBootHartId;=0D +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol;=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +RiscvGetBootHartId (=0D + IN RISCV_EFI_BOOT_PROTOCOL *This,=0D + OUT UINTN *BootHartId=0D + )=0D +{=0D + if((This !=3D &gRiscvBootProtocol) || (BootHartId =3D=3D NULL)) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + *BootHartId =3D mBootHartId;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol =3D {=0D + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,=0D + RiscvGetBootHartId=0D +};=0D +=0D +EFI_CPU_ARCH_PROTOCOL gCpu =3D {=0D + CpuFlushCpuDataCache,=0D + CpuEnableInterrupt,=0D + CpuDisableInterrupt,=0D + CpuGetInterruptState,=0D + CpuInit,=0D + CpuRegisterInterruptHandler,=0D + CpuGetTimerValue,=0D + CpuSetMemoryAttributes,=0D + 1, // NumberOfTimers=0D + 4 // DmaBufferAlignment=0D +};=0D +=0D +//=0D +// CPU Arch Protocol Functions=0D +//=0D +=0D +/**=0D + Flush CPU data cache. If the instruction cache is fully coherent=0D + with all DMA operations then function can just return EFI_SUCCESS.=0D +=0D + @param This Protocol instance structure=0D + @param Start Physical address to start flushing from.=0D + @param Length Number of bytes to flush. Round up to chipset= =0D + granularity.=0D + @param FlushType Specifies the type of flush operation to perfo= rm.=0D +=0D + @retval EFI_SUCCESS If cache was flushed=0D + @retval EFI_UNSUPPORTED If flush type is not supported.=0D + @retval EFI_DEVICE_ERROR If requested range could not be flushed.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuFlushCpuDataCache (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS Start,=0D + IN UINT64 Length,=0D + IN EFI_CPU_FLUSH_TYPE FlushType=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Enables CPU interrupts.=0D +=0D + @param This Protocol instance structure=0D +=0D + @retval EFI_SUCCESS If interrupts were enabled in the CPU=0D + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.= =0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuEnableInterrupt (=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D + )=0D +{=0D + EnableInterrupts ();=0D + mInterruptState =3D TRUE;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Disables CPU interrupts.=0D +=0D + @param This Protocol instance structure=0D +=0D + @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU= .=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuDisableInterrupt (=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D + )=0D +{=0D + DisableInterrupts ();=0D + mInterruptState =3D FALSE;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Return the state of interrupts.=0D +=0D + @param This Protocol instance structure=0D + @param State Pointer to the CPU's current interrupt st= ate=0D +=0D + @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D + @retval EFI_INVALID_PARAMETER State is NULL.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuGetInterruptState (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + OUT BOOLEAN *State=0D + )=0D +{=0D + if (State =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + *State =3D mInterruptState;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Generates an INIT to the CPU.=0D +=0D + @param This Protocol instance structure=0D + @param InitType Type of CPU INIT to perform=0D +=0D + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be=0D + seen.=0D + @retval EFI_DEVICE_ERROR If CPU INIT failed.=0D + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuInit (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_CPU_INIT_TYPE InitType=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + Registers a function to be called from the CPU interrupt handler.=0D +=0D + @param This Protocol instance structure=0D + @param InterruptType Defines which interrupt to hook. IA-32=0D + valid range is 0x00 through 0xFF=0D + @param InterruptHandler A pointer to a function of type=0D + EFI_CPU_INTERRUPT_HANDLER that is called= =0D + when a processor interrupt occurs. A nul= l=0D + pointer is an error condition.=0D +=0D + @retval EFI_SUCCESS If handler installed or uninstalled.=0D + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er=0D + for InterruptType was previously installe= d.=0D + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or=0D + InterruptType was not previously installe= d.=0D + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType= =0D + is not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuRegisterInterruptHandler (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D + )=0D +{=0D + return RegisterCpuInterruptHandler (InterruptType, InterruptHandler);=0D +}=0D +=0D +/**=0D + Returns a timer value from one of the CPU's internal timers. There is no= =0D + inherent time interval between ticks but is a function of the CPU freque= ncy.=0D +=0D + @param This - Protocol instance structure.=0D + @param TimerIndex - Specifies which CPU timer is requested.=0D + @param TimerValue - Pointer to the returned timer value.=0D + @param TimerPeriod - A pointer to the amount of time that passe= s=0D + in femtoseconds (10-15) for each increment= =0D + of TimerValue. If TimerValue does not=0D + increment at a predictable rate, then 0 is= =0D + returned. The amount of time that has=0D + passed between two calls to GetTimerValue(= )=0D + can be calculated with the formula=0D + (TimerValue2 - TimerValue1) * TimerPeriod.= =0D + This parameter is optional and may be NULL= .=0D +=0D + @retval EFI_SUCCESS - If the CPU timer count was returned.=0D + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers.=0D + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer.=0D + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuGetTimerValue (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN UINT32 TimerIndex,=0D + OUT UINT64 *TimerValue,=0D + OUT UINT64 *TimerPeriod OPTIONAL=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + Implementation of SetMemoryAttributes() service of CPU Architecture Prot= ocol.=0D +=0D + This function modifies the attributes for the memory region specified by= BaseAddress and=0D + Length from their current attributes to the attributes specified by Attr= ibutes.=0D +=0D + @param This The EFI_CPU_ARCH_PROTOCOL instance.=0D + @param BaseAddress The physical address that is the start address = of a memory region.=0D + @param Length The size in bytes of the memory region.=0D + @param Attributes The bit mask of attributes to set for the memor= y region.=0D +=0D + @retval EFI_SUCCESS The attributes were set for the memory reg= ion.=0D + @retval EFI_ACCESS_DENIED The attributes for the memory resource ran= ge specified by=0D + BaseAddress and Length cannot be modified.= =0D + @retval EFI_INVALID_PARAMETER Length is zero.=0D + Attributes specified an illegal combinatio= n of attributes that=0D + cannot be set together.=0D + @retval EFI_OUT_OF_RESOURCES There are not enough system resources to m= odify the attributes of=0D + the memory resource range.=0D + @retval EFI_UNSUPPORTED The processor does not support one or more= bytes of the memory=0D + resource range specified by BaseAddress an= d Length.=0D + The bit mask of attributes is not support = for the memory resource=0D + range specified by BaseAddress and Length.= =0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuSetMemoryAttributes (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D + IN UINT64 Length,=0D + IN UINT64 Attributes=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "%a: Set memory attributes not supported yet\n", __F= UNCTION__));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Initialize the state information for the CPU Architectural Protocol.=0D +=0D + @param ImageHandle Image handle this driver.=0D + @param SystemTable Pointer to the System Table.=0D +=0D + @retval EFI_SUCCESS Thread can be successfully created=0D + @retval EFI_OUT_OF_RESOURCES Cannot allocate protocol data structure=0D + @retval EFI_DEVICE_ERROR Cannot create the thread=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializeCpu (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext;=0D +=0D + GetFirmwareContextPointer (&FirmwareContext);=0D + ASSERT (FirmwareContext !=3D NULL);=0D + if (FirmwareContext =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_= CONTEXT\n"));=0D + return EFI_NOT_FOUND;=0D + }=0D + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__,= FirmwareContext));=0D +=0D + mBootHartId =3D FirmwareContext->BootHartId;=0D + DEBUG ((DEBUG_INFO, " %a: mBootHartId =3D 0x%x.\n", __FUNCTION__, mBootH= artId));=0D +=0D +=0D + InitializeCpuExceptionHandlers(NULL);=0D +=0D + //=0D + // Make sure interrupts are disabled=0D + //=0D + DisableInterrupts ();=0D +=0D + Status =3D gBS->InstallProtocolInterface (&ImageHandle,=0D + &gRiscVEfiBootProtocolGuid,=0D + EFI_NATIVE_INTERFACE,=0D + &gRiscvBootProtocol=0D + );=0D +=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Install CPU Architectural Protocol=0D + //=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &mCpuHandle,=0D + &gEfiCpuArchProtocolGuid,=0D + &gCpu,=0D + NULL=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D +}=0D diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h b/UefiCpuPkg/CpuDxe/RiscV64= /CpuDxe.h new file mode 100644 index 0000000000..f039759dbd --- /dev/null +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h @@ -0,0 +1,200 @@ +/** @file=0D + RISC-V CPU DXE module header file.=0D +=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef CPU_DXE_H_=0D +#define CPU_DXE_H_=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Flush CPU data cache. If the instruction cache is fully coherent=0D + with all DMA operations then function can just return EFI_SUCCESS.=0D +=0D + @param This Protocol instance structure=0D + @param Start Physical address to start flushing from.=0D + @param Length Number of bytes to flush. Round up to chipset= =0D + granularity.=0D + @param FlushType Specifies the type of flush operation to perfo= rm.=0D +=0D + @retval EFI_SUCCESS If cache was flushed=0D + @retval EFI_UNSUPPORTED If flush type is not supported.=0D + @retval EFI_DEVICE_ERROR If requested range could not be flushed.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuFlushCpuDataCache (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS Start,=0D + IN UINT64 Length,=0D + IN EFI_CPU_FLUSH_TYPE FlushType=0D + );=0D +=0D +/**=0D + Enables CPU interrupts.=0D +=0D + @param This Protocol instance structure=0D +=0D + @retval EFI_SUCCESS If interrupts were enabled in the CPU=0D + @retval EFI_DEVICE_ERROR If interrupts could not be enabled on the CPU.= =0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuEnableInterrupt (=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D + );=0D +=0D +/**=0D + Disables CPU interrupts.=0D +=0D + @param This Protocol instance structure=0D +=0D + @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D + @retval EFI_DEVICE_ERROR If interrupts could not be disabled on the CPU= .=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuDisableInterrupt (=0D + IN EFI_CPU_ARCH_PROTOCOL *This=0D + );=0D +=0D +/**=0D + Return the state of interrupts.=0D +=0D + @param This Protocol instance structure=0D + @param State Pointer to the CPU's current interrupt st= ate=0D +=0D + @retval EFI_SUCCESS If interrupts were disabled in the CPU.=0D + @retval EFI_INVALID_PARAMETER State is NULL.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuGetInterruptState (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + OUT BOOLEAN *State=0D + );=0D +=0D +/**=0D + Generates an INIT to the CPU.=0D +=0D + @param This Protocol instance structure=0D + @param InitType Type of CPU INIT to perform=0D +=0D + @retval EFI_SUCCESS If CPU INIT occurred. This value should never = be=0D + seen.=0D + @retval EFI_DEVICE_ERROR If CPU INIT failed.=0D + @retval EFI_UNSUPPORTED Requested type of CPU INIT not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuInit (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_CPU_INIT_TYPE InitType=0D + );=0D +=0D +/**=0D + Registers a function to be called from the CPU interrupt handler.=0D +=0D + @param This Protocol instance structure=0D + @param InterruptType Defines which interrupt to hook. IA-32=0D + valid range is 0x00 through 0xFF=0D + @param InterruptHandler A pointer to a function of type=0D + EFI_CPU_INTERRUPT_HANDLER that is called= =0D + when a processor interrupt occurs. A nul= l=0D + pointer is an error condition.=0D +=0D + @retval EFI_SUCCESS If handler installed or uninstalled.=0D + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handl= er=0D + for InterruptType was previously installe= d.=0D + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler f= or=0D + InterruptType was not previously installe= d.=0D + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType= =0D + is not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuRegisterInterruptHandler (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D + );=0D +=0D +/**=0D + Returns a timer value from one of the CPU's internal timers. There is no= =0D + inherent time interval between ticks but is a function of the CPU freque= ncy.=0D +=0D + @param This - Protocol instance structure.=0D + @param TimerIndex - Specifies which CPU timer is requested.=0D + @param TimerValue - Pointer to the returned timer value.=0D + @param TimerPeriod - A pointer to the amount of time that passe= s=0D + in femtoseconds (10-15) for each increment= =0D + of TimerValue. If TimerValue does not=0D + increment at a predictable rate, then 0 is= =0D + returned. The amount of time that has=0D + passed between two calls to GetTimerValue(= )=0D + can be calculated with the formula=0D + (TimerValue2 - TimerValue1) * TimerPeriod.= =0D + This parameter is optional and may be NULL= .=0D +=0D + @retval EFI_SUCCESS - If the CPU timer count was returned.=0D + @retval EFI_UNSUPPORTED - If the CPU does not have any readable ti= mers.=0D + @retval EFI_DEVICE_ERROR - If an error occurred while reading the t= imer.=0D + @retval EFI_INVALID_PARAMETER - TimerIndex is not valid or TimerValue is= NULL.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuGetTimerValue (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN UINT32 TimerIndex,=0D + OUT UINT64 *TimerValue,=0D + OUT UINT64 *TimerPeriod OPTIONAL=0D + );=0D +=0D +/**=0D + Set memory cacheability attributes for given range of memeory.=0D +=0D + @param This Protocol instance structure=0D + @param BaseAddress Specifies the start address of the=0D + memory range=0D + @param Length Specifies the length of the memory range= =0D + @param Attributes The memory cacheability for the memory ra= nge=0D +=0D + @retval EFI_SUCCESS If the cacheability of that memory range = is=0D + set successfully=0D + @retval EFI_UNSUPPORTED If the desired operation cannot be done=0D + @retval EFI_INVALID_PARAMETER The input parameter is not correct,=0D + such as Length =3D 0=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CpuSetMemoryAttributes (=0D + IN EFI_CPU_ARCH_PROTOCOL *This,=0D + IN EFI_PHYSICAL_ADDRESS BaseAddress,=0D + IN UINT64 Length,=0D + IN UINT64 Attributes=0D + );=0D +=0D +#endif=0D --=20 2.25.1