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From: "Sunil V L" <sunilvl@ventanamicro.com>
To: devel@edk2.groups.io
Cc: Jian J Wang <jian.j.wang@intel.com>,
	Liming Gao <gaoliming@byosoft.com.cn>,
	Eric Dong <eric.dong@intel.com>, Ray Ni <ray.ni@intel.com>,
	Rahul Kumar <rahul1.kumar@intel.com>,
	Debkumar De <debkumar.de@intel.com>,
	Catharine West <catharine.west@intel.com>,
	Daniel Schaefer <git@danielschaefer.me>,
	Abner Chang <Abner.Chang@amd.com>,
	Leif Lindholm <quic_llindhol@quicinc.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Sunil V L <sunilvl@ventanamicro.com>
Subject: [RFC PATCH 01/17] MdePkg/Register: Add register definition header files for RISC-V
Date: Tue,  6 Sep 2022 22:38:21 +0530	[thread overview]
Message-ID: <20220906170837.491525-2-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com>

Add register definitions and access routines for RISC-V. These
headers are leveraged from opensbi repo.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 MdePkg/Include/Register/RiscV64/RiscVAsm.h    | 104 ++++++++++++++
 MdePkg/Include/Register/RiscV64/RiscVConst.h  |  46 +++++++
 .../Include/Register/RiscV64/RiscVEncoding.h  | 129 ++++++++++++++++++
 MdePkg/Include/Register/RiscV64/RiscVImpl.h   |  24 ++++
 4 files changed, 303 insertions(+)
 create mode 100644 MdePkg/Include/Register/RiscV64/RiscVAsm.h
 create mode 100644 MdePkg/Include/Register/RiscV64/RiscVConst.h
 create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h
 create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h

diff --git a/MdePkg/Include/Register/RiscV64/RiscVAsm.h b/MdePkg/Include/Register/RiscV64/RiscVAsm.h
new file mode 100644
index 0000000000..e566061b73
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVAsm.h
@@ -0,0 +1,104 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __RISCV_ASM_H__
+#define __RISCV_ASM_H__
+
+#include <Register/RiscV64/RiscVEncoding.h>
+
+#ifdef __ASSEMBLER__
+#define __ASM_STR(x)    x
+#else
+#define __ASM_STR(x)    #x
+#endif
+
+#ifndef __ASSEMBLER__
+
+#define csr_swap(csr, val)                                  \
+  ({                                                        \
+    unsigned long __v = (unsigned long)(val);               \
+    __asm__ __volatile__("csrrw %0, " __ASM_STR(csr) ", %1" \
+                         : "=r"(__v)                        \
+                         : "rK"(__v)                        \
+                         : "memory");                       \
+    __v;                                                    \
+  })
+
+#define csr_read(csr)                               \
+  ({                                                \
+    register unsigned long __v;                     \
+    __asm__ __volatile__("csrr %0, " __ASM_STR(csr) \
+                         : "=r"(__v)                \
+                         :                          \
+                         : "memory");               \
+    __v;                                            \
+  })
+
+#define csr_write(csr, val)                            \
+  ({                                                   \
+    unsigned long __v = (unsigned long)(val);          \
+    __asm__ __volatile__("csrw " __ASM_STR(csr) ", %0" \
+                         :                             \
+                         : "rK"(__v)                   \
+                         : "memory");                  \
+  })
+
+#define csr_read_set(csr, val)                              \
+  ({                                                        \
+    unsigned long __v = (unsigned long)(val);               \
+    __asm__ __volatile__("csrrs %0, " __ASM_STR(csr) ", %1" \
+                         : "=r"(__v)                        \
+                         : "rK"(__v)                        \
+                         : "memory");                       \
+    __v;                                                    \
+  })
+
+#define csr_set(csr, val)                              \
+  ({                                                   \
+    unsigned long __v = (unsigned long)(val);          \
+    __asm__ __volatile__("csrs " __ASM_STR(csr) ", %0" \
+                         :                             \
+                         : "rK"(__v)                   \
+                         : "memory");                  \
+  })
+
+#define csr_read_clear(csr, val)                            \
+  ({                                                        \
+    unsigned long __v = (unsigned long)(val);               \
+    __asm__ __volatile__("csrrc %0, " __ASM_STR(csr) ", %1" \
+                         : "=r"(__v)                        \
+                         : "rK"(__v)                        \
+                         : "memory");                       \
+    __v;                                                    \
+  })
+
+#define csr_clear(csr, val)                            \
+  ({                                                   \
+    unsigned long __v = (unsigned long)(val);          \
+    __asm__ __volatile__("csrc " __ASM_STR(csr) ", %0" \
+                         :                             \
+                         : "rK"(__v)                   \
+                         : "memory");                  \
+  })
+
+#define wfi()                                 \
+  do {                                        \
+    __asm__ __volatile__("wfi" ::: "memory"); \
+  } while (0)
+
+#define ebreak()                                 \
+  do {                                           \
+    __asm__ __volatile__("ebreak" ::: "memory"); \
+  } while (0)
+
+
+#endif /* !__ASSEMBLER__ */
+
+#endif
diff --git a/MdePkg/Include/Register/RiscV64/RiscVConst.h b/MdePkg/Include/Register/RiscV64/RiscVConst.h
new file mode 100644
index 0000000000..ea7e151191
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVConst.h
@@ -0,0 +1,46 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc. All rights reserved.<BR>
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ * This is leveraged from sbi_const.h in opensbi.
+ */
+
+#ifndef __RISCV_CONST_H__
+#define __RISCV_CONST_H__
+
+/*
+ * Some constant macros are used in both assembler and
+ * C code.  Therefore we cannot annotate them always with
+ * 'UL' and other type specifiers unilaterally.  We
+ * use the following macros to deal with this.
+ *
+ * Similarly, _AT() will cast an expression with a type in C, but
+ * leave it unchanged in asm.
+ */
+
+#ifdef __ASSEMBLER__
+#define _AC(X,Y)        X
+#define _AT(T,X)        X
+#else
+#define __AC(X,Y)       (X##Y)
+#define _AC(X,Y)        __AC(X,Y)
+#define _AT(T,X)        ((T)(X))
+#endif
+
+#define _UL(x)          (_AC(x, UL))
+#define _ULL(x)         (_AC(x, ULL))
+
+#define _BITUL(x)       (_UL(1) << (x))
+#define _BITULL(x)      (_ULL(1) << (x))
+
+#define UL(x)           (_UL(x))
+#define ULL(x)          (_ULL(x))
+
+#define __STR(s)        #s
+#define STRINGIFY(s)    __STR(s)
+
+#endif
diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
new file mode 100644
index 0000000000..5ad66ee7e7
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h
@@ -0,0 +1,129 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2022 Ventana Micro Systems Inc.
+ *
+ * Authors:
+ *   Anup Patel <anup.patel@wdc.com>
+ */
+
+#ifndef __RISCV_ENCODING_H__
+#define __RISCV_ENCODING_H__
+
+#include <Register/RiscV64/RiscVConst.h>
+
+/* clang-format off */
+#define MSTATUS_SIE                     _UL(0x00000002)
+#define MSTATUS_MIE                     _UL(0x00000008)
+#define MSTATUS_SPIE_SHIFT              5
+#define MSTATUS_SPIE                    (_UL(1) << MSTATUS_SPIE_SHIFT)
+#define MSTATUS_UBE                     _UL(0x00000040)
+#define MSTATUS_MPIE                    _UL(0x00000080)
+#define MSTATUS_SPP_SHIFT               8
+#define MSTATUS_SPP                     (_UL(1) << MSTATUS_SPP_SHIFT)
+#define MSTATUS_MPP_SHIFT               11
+#define MSTATUS_MPP                     (_UL(3) << MSTATUS_MPP_SHIFT)
+
+#define SSTATUS_SIE                     MSTATUS_SIE
+#define SSTATUS_SPIE_SHIFT              MSTATUS_SPIE_SHIFT
+#define SSTATUS_SPIE                    MSTATUS_SPIE
+#define SSTATUS_SPP_SHIFT               MSTATUS_SPP_SHIFT
+#define SSTATUS_SPP                     MSTATUS_SPP
+
+#define IRQ_S_SOFT                      1
+#define IRQ_VS_SOFT                     2
+#define IRQ_M_SOFT                      3
+#define IRQ_S_TIMER                     5
+#define IRQ_VS_TIMER                    6
+#define IRQ_M_TIMER                     7
+#define IRQ_S_EXT                       9
+#define IRQ_VS_EXT                      10
+#define IRQ_M_EXT                       11
+#define IRQ_S_GEXT                      12
+#define IRQ_PMU_OVF                     13
+
+#define MIP_SSIP                        (_UL(1) << IRQ_S_SOFT)
+#define MIP_VSSIP                       (_UL(1) << IRQ_VS_SOFT)
+#define MIP_MSIP                        (_UL(1) << IRQ_M_SOFT)
+#define MIP_STIP                        (_UL(1) << IRQ_S_TIMER)
+#define MIP_VSTIP                       (_UL(1) << IRQ_VS_TIMER)
+#define MIP_MTIP                        (_UL(1) << IRQ_M_TIMER)
+#define MIP_SEIP                        (_UL(1) << IRQ_S_EXT)
+#define MIP_VSEIP                       (_UL(1) << IRQ_VS_EXT)
+#define MIP_MEIP                        (_UL(1) << IRQ_M_EXT)
+#define MIP_SGEIP                       (_UL(1) << IRQ_S_GEXT)
+#define MIP_LCOFIP                      (_UL(1) << IRQ_PMU_OVF)
+
+#define SIP_SSIP                        MIP_SSIP
+#define SIP_STIP                        MIP_STIP
+
+#define PRV_U                           _UL(0)
+#define PRV_S                           _UL(1)
+#define PRV_M                           _UL(3)
+
+#define SATP64_MODE                     _ULL(0xF000000000000000)
+#define SATP64_ASID                     _ULL(0x0FFFF00000000000)
+#define SATP64_PPN                      _ULL(0x00000FFFFFFFFFFF)
+
+#define SATP_MODE_OFF                   _UL(0)
+#define SATP_MODE_SV32                  _UL(1)
+#define SATP_MODE_SV39                  _UL(8)
+#define SATP_MODE_SV48                  _UL(9)
+#define SATP_MODE_SV57                  _UL(10)
+#define SATP_MODE_SV64                  _UL(11)
+
+
+#define SATP_MODE                       SATP64_MODE
+
+/* ===== User-level CSRs ===== */
+
+/* User Counters/Timers */
+#define CSR_CYCLE                       0xc00
+#define CSR_TIME                        0xc01
+
+/* ===== Supervisor-level CSRs ===== */
+
+/* Supervisor Trap Setup */
+#define CSR_SSTATUS                     0x100
+#define CSR_SEDELEG                     0x102
+#define CSR_SIDELEG                     0x103
+#define CSR_SIE                         0x104
+#define CSR_STVEC                       0x105
+
+/* Supervisor Configuration */
+#define CSR_SENVCFG                     0x10a
+
+/* Supervisor Trap Handling */
+#define CSR_SSCRATCH                    0x140
+#define CSR_SEPC                        0x141
+#define CSR_SCAUSE                      0x142
+#define CSR_STVAL                       0x143
+#define CSR_SIP                         0x144
+
+/* Supervisor Protection and Translation */
+#define CSR_SATP                        0x180
+
+/* ===== Trap/Exception Causes ===== */
+
+#define CAUSE_MISALIGNED_FETCH          0x0
+#define CAUSE_FETCH_ACCESS              0x1
+#define CAUSE_ILLEGAL_INSTRUCTION       0x2
+#define CAUSE_BREAKPOINT                0x3
+#define CAUSE_MISALIGNED_LOAD           0x4
+#define CAUSE_LOAD_ACCESS               0x5
+#define CAUSE_MISALIGNED_STORE          0x6
+#define CAUSE_STORE_ACCESS              0x7
+#define CAUSE_USER_ECALL                0x8
+#define CAUSE_SUPERVISOR_ECALL          0x9
+#define CAUSE_VIRTUAL_SUPERVISOR_ECALL  0xa
+#define CAUSE_MACHINE_ECALL             0xb
+#define CAUSE_FETCH_PAGE_FAULT          0xc
+#define CAUSE_LOAD_PAGE_FAULT           0xd
+#define CAUSE_STORE_PAGE_FAULT          0xf
+#define CAUSE_FETCH_GUEST_PAGE_FAULT    0x14
+#define CAUSE_LOAD_GUEST_PAGE_FAULT     0x15
+#define CAUSE_VIRTUAL_INST_FAULT        0x16
+#define CAUSE_STORE_GUEST_PAGE_FAULT    0x17
+
+#endif
diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
new file mode 100644
index 0000000000..e9ccd34039
--- /dev/null
+++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h
@@ -0,0 +1,24 @@
+/** @file
+  RISC-V package definitions.
+
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __RISCV_IMPL_H_
+#define __RISCV_IMPL_H_
+
+#define _ASM_FUNC(Name, Section)    \
+  .global   Name                  ; \
+  .section  #Section, "ax"        ; \
+  .type     Name, %function       ; \
+  .p2align  2                     ; \
+  Name:
+
+#define ASM_FUNC(Name)  _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
+#define RISCV_TIMER_COMPARE_BITS  32
+
+#endif
-- 
2.25.1


  reply	other threads:[~2022-09-06 17:08 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
2022-09-06 17:08 ` Sunil V L [this message]
2022-09-06 17:08 ` [RFC PATCH 02/17] MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID Sunil V L
2022-09-06 17:08 ` [RFC PATCH 03/17] MdePkg/Protocol: Add RiscVBootProtocol.h Sunil V L
2022-09-06 17:08 ` [RFC PATCH 04/17] MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 05/17] UefiCpuPkg.dec: Add PCD variable " Sunil V L
2022-09-06 17:08 ` [RFC PATCH 06/17] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Sunil V L
2022-09-06 17:08 ` [RFC PATCH 07/17] MdePkg: Add ArchTimerLib library Sunil V L
2022-09-06 17:08 ` [RFC PATCH 08/17] MdePkg: Add RiscVSbiLib Library for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 09/17] UefiCpuPkg/DxeCpuExceptionHandlerLib: Refactor to add other architectures Sunil V L
2022-09-06 17:08 ` [RFC PATCH 10/17] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib Sunil V L
2022-09-06 17:08 ` [RFC PATCH 11/17] MdePkg/Library: Add ResetSystemLib library Sunil V L
2022-09-06 17:08 ` [RFC PATCH 12/17] UefiCpuPkg/SecCore: Add SEC startup code for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 13/17] MdePkg: Add PlatformPeiLib library Sunil V L
2022-09-06 17:08 ` [RFC PATCH 14/17] MdeModulePkg/Universal: Add PlatformPei module for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 15/17] UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures Sunil V L
2022-09-06 17:08 ` [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Sunil V L
2022-09-07  9:32   ` Chang, Abner
2022-09-07 11:22     ` Sunil V L
2022-09-07 12:46       ` Chang, Abner
2022-09-08 10:53         ` Sunil V L
2022-09-08 12:02           ` Chang, Abner
2022-09-06 17:08 ` [RFC PATCH 17/17] MdeModulePkg/Universal: Add TimerDxe module Sunil V L
2022-09-07  5:54 ` [edk2-devel] [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Gerd Hoffmann

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