From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f170.google.com (mail-pl1-f170.google.com [209.85.214.170]) by mx.groups.io with SMTP id smtpd.web12.1904.1662484132293121015 for ; Tue, 06 Sep 2022 10:08:52 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=RC29+5iP; spf=pass (domain: ventanamicro.com, ip: 209.85.214.170, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pl1-f170.google.com with SMTP id s14so2336652plr.4 for ; Tue, 06 Sep 2022 10:08:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=tBDwBI97BcFAwQ0vihWd1lIaw7tCBL/wM9P1MOmjDmE=; b=RC29+5iPPdXF1FjaDhenwaZWDB4U31iCTmXI8yAajx6TFP4sg/jl7ZHtj1PD+c3GF7 fqlR0yliq6ah3RDAbVrkvWiChJHGpEPKOE/81KdgIIsiWXTwx7navrb2gGY1ntQOYXCz 4EPnHpJBdSbWWy95GRkrkpCS70VUDpuax47y0988Zt0GNb0K01JsLgh0wv9UCzpooCNM RdR17PIJ2SZ/Jio0GrwDAmbefd6p72ozONgrz7J2bUFGsehL8KSje9BK/hPKrtYVFE9+ yf3JrKXYg6uhs03PKOR9hUAFrz3l2uzwzvkKj2/k9s0S1mKjRIqgzXLgi3L2PV5AJkzk Lx8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=tBDwBI97BcFAwQ0vihWd1lIaw7tCBL/wM9P1MOmjDmE=; b=NAlfBu4Cx0RoSI5BN/+EWH+/vz8AUCr8fRcX0zZIusm652qt+g8ZDigshKCee3pbRo IIqKWH807M/wBp0X0GfPpV61Zs3aXW3RCDkzedoyGMFxRjzkVDAOltgawX22Zm3GPkve JHQkpqESGHzYwiJ/SIRT1bM+zURpZJNW9SwYJe6P5ngpjLcEP6hR2Am/SMczJKFZcHqP BWr//yuDT3PdnqMup6GI/1E04UP53uWdY2MlxADUuBNP0zK5bU0nBgsu6khJyBW/dkd0 vOeassLHzsl+QIyjaw639R5KdsED0jFWU24J45F7h1Lq8iWQGiXbetvCBBEtr1aaCVuQ 1Z6A== X-Gm-Message-State: ACgBeo2jUXbxW++veA107D52tCSITNd2LK/MihHJapHmBansdRHjvXEJ QNv6Eyxh/fbNNlY+j9S5IPZ1nmZMfK67qiJK X-Google-Smtp-Source: AA6agR7kEgMUO0poX7VlHtd6Z+POjuv7513qw+gylEotQFeVbvtGIFp3NsnKjz9R3y0kAYkZ7upvpA== X-Received: by 2002:a17:902:d505:b0:175:5313:2a3f with SMTP id b5-20020a170902d50500b0017553132a3fmr29246142plg.70.1662484130848; Tue, 06 Sep 2022 10:08:50 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:08:50 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [RFC PATCH 01/17] MdePkg/Register: Add register definition header files for RISC-V Date: Tue, 6 Sep 2022 22:38:21 +0530 Message-Id: <20220906170837.491525-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Signed-off-by: Sunil V L --- MdePkg/Include/Register/RiscV64/RiscVAsm.h | 104 ++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVConst.h | 46 +++++++ .../Include/Register/RiscV64/RiscVEncoding.h | 129 ++++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 24 ++++ 4 files changed, 303 insertions(+) create mode 100644 MdePkg/Include/Register/RiscV64/RiscVAsm.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVConst.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h diff --git a/MdePkg/Include/Register/RiscV64/RiscVAsm.h b/MdePkg/Include/Re= gister/RiscV64/RiscVAsm.h new file mode 100644 index 0000000000..e566061b73 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVAsm.h @@ -0,0 +1,104 @@ +/*=0D + * SPDX-License-Identifier: BSD-2-Clause=0D + *=0D + * Copyright (c) 2019 Western Digital Corporation or its affiliates.=0D + * Copyright (c) 2022 Ventana Micro Systems Inc.=0D + *=0D + * Authors:=0D + * Anup Patel =0D + */=0D +=0D +#ifndef __RISCV_ASM_H__=0D +#define __RISCV_ASM_H__=0D +=0D +#include =0D +=0D +#ifdef __ASSEMBLER__=0D +#define __ASM_STR(x) x=0D +#else=0D +#define __ASM_STR(x) #x=0D +#endif=0D +=0D +#ifndef __ASSEMBLER__=0D +=0D +#define csr_swap(csr, val) \=0D + ({ \=0D + unsigned long __v =3D (unsigned long)(val); \=0D + __asm__ __volatile__("csrrw %0, " __ASM_STR(csr) ", %1" \=0D + : "=3Dr"(__v) \=0D + : "rK"(__v) \=0D + : "memory"); \=0D + __v; \=0D + })=0D +=0D +#define csr_read(csr) \=0D + ({ \=0D + register unsigned long __v; \=0D + __asm__ __volatile__("csrr %0, " __ASM_STR(csr) \=0D + : "=3Dr"(__v) \=0D + : \=0D + : "memory"); \=0D + __v; \=0D + })=0D +=0D +#define csr_write(csr, val) \=0D + ({ \=0D + unsigned long __v =3D (unsigned long)(val); \=0D + __asm__ __volatile__("csrw " __ASM_STR(csr) ", %0" \=0D + : \=0D + : "rK"(__v) \=0D + : "memory"); \=0D + })=0D +=0D +#define csr_read_set(csr, val) \=0D + ({ \=0D + unsigned long __v =3D (unsigned long)(val); \=0D + __asm__ __volatile__("csrrs %0, " __ASM_STR(csr) ", %1" \=0D + : "=3Dr"(__v) \=0D + : "rK"(__v) \=0D + : "memory"); \=0D + __v; \=0D + })=0D +=0D +#define csr_set(csr, val) \=0D + ({ \=0D + unsigned long __v =3D (unsigned long)(val); \=0D + __asm__ __volatile__("csrs " __ASM_STR(csr) ", %0" \=0D + : \=0D + : "rK"(__v) \=0D + : "memory"); \=0D + })=0D +=0D +#define csr_read_clear(csr, val) \=0D + ({ \=0D + unsigned long __v =3D (unsigned long)(val); \=0D + __asm__ __volatile__("csrrc %0, " __ASM_STR(csr) ", %1" \=0D + : "=3Dr"(__v) \=0D + : "rK"(__v) \=0D + : "memory"); \=0D + __v; \=0D + })=0D +=0D +#define csr_clear(csr, val) \=0D + ({ \=0D + unsigned long __v =3D (unsigned long)(val); \=0D + __asm__ __volatile__("csrc " __ASM_STR(csr) ", %0" \=0D + : \=0D + : "rK"(__v) \=0D + : "memory"); \=0D + })=0D +=0D +#define wfi() \=0D + do { \=0D + __asm__ __volatile__("wfi" ::: "memory"); \=0D + } while (0)=0D +=0D +#define ebreak() \=0D + do { \=0D + __asm__ __volatile__("ebreak" ::: "memory"); \=0D + } while (0)=0D +=0D +=0D +#endif /* !__ASSEMBLER__ */=0D +=0D +#endif=0D diff --git a/MdePkg/Include/Register/RiscV64/RiscVConst.h b/MdePkg/Include/= Register/RiscV64/RiscVConst.h new file mode 100644 index 0000000000..ea7e151191 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVConst.h @@ -0,0 +1,46 @@ +/*=0D + * SPDX-License-Identifier: BSD-2-Clause=0D + *=0D + * Copyright (c) 2019 Western Digital Corporation or its affiliates.=0D + * Copyright (c) 2022 Ventana Micro Systems Inc. All rights reserved.
= =0D + *=0D + * Authors:=0D + * Anup Patel =0D + * This is leveraged from sbi_const.h in opensbi.=0D + */=0D +=0D +#ifndef __RISCV_CONST_H__=0D +#define __RISCV_CONST_H__=0D +=0D +/*=0D + * Some constant macros are used in both assembler and=0D + * C code. Therefore we cannot annotate them always with=0D + * 'UL' and other type specifiers unilaterally. We=0D + * use the following macros to deal with this.=0D + *=0D + * Similarly, _AT() will cast an expression with a type in C, but=0D + * leave it unchanged in asm.=0D + */=0D +=0D +#ifdef __ASSEMBLER__=0D +#define _AC(X,Y) X=0D +#define _AT(T,X) X=0D +#else=0D +#define __AC(X,Y) (X##Y)=0D +#define _AC(X,Y) __AC(X,Y)=0D +#define _AT(T,X) ((T)(X))=0D +#endif=0D +=0D +#define _UL(x) (_AC(x, UL))=0D +#define _ULL(x) (_AC(x, ULL))=0D +=0D +#define _BITUL(x) (_UL(1) << (x))=0D +#define _BITULL(x) (_ULL(1) << (x))=0D +=0D +#define UL(x) (_UL(x))=0D +#define ULL(x) (_ULL(x))=0D +=0D +#define __STR(s) #s=0D +#define STRINGIFY(s) __STR(s)=0D +=0D +#endif=0D diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Inclu= de/Register/RiscV64/RiscVEncoding.h new file mode 100644 index 0000000000..5ad66ee7e7 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -0,0 +1,129 @@ +/*=0D + * SPDX-License-Identifier: BSD-2-Clause=0D + *=0D + * Copyright (c) 2019 Western Digital Corporation or its affiliates.=0D + * Copyright (c) 2022 Ventana Micro Systems Inc.=0D + *=0D + * Authors:=0D + * Anup Patel =0D + */=0D +=0D +#ifndef __RISCV_ENCODING_H__=0D +#define __RISCV_ENCODING_H__=0D +=0D +#include =0D +=0D +/* clang-format off */=0D +#define MSTATUS_SIE _UL(0x00000002)=0D +#define MSTATUS_MIE _UL(0x00000008)=0D +#define MSTATUS_SPIE_SHIFT 5=0D +#define MSTATUS_SPIE (_UL(1) << MSTATUS_SPIE_SHIFT)=0D +#define MSTATUS_UBE _UL(0x00000040)=0D +#define MSTATUS_MPIE _UL(0x00000080)=0D +#define MSTATUS_SPP_SHIFT 8=0D +#define MSTATUS_SPP (_UL(1) << MSTATUS_SPP_SHIFT)=0D +#define MSTATUS_MPP_SHIFT 11=0D +#define MSTATUS_MPP (_UL(3) << MSTATUS_MPP_SHIFT)=0D +=0D +#define SSTATUS_SIE MSTATUS_SIE=0D +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT=0D +#define SSTATUS_SPIE MSTATUS_SPIE=0D +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT=0D +#define SSTATUS_SPP MSTATUS_SPP=0D +=0D +#define IRQ_S_SOFT 1=0D +#define IRQ_VS_SOFT 2=0D +#define IRQ_M_SOFT 3=0D +#define IRQ_S_TIMER 5=0D +#define IRQ_VS_TIMER 6=0D +#define IRQ_M_TIMER 7=0D +#define IRQ_S_EXT 9=0D +#define IRQ_VS_EXT 10=0D +#define IRQ_M_EXT 11=0D +#define IRQ_S_GEXT 12=0D +#define IRQ_PMU_OVF 13=0D +=0D +#define MIP_SSIP (_UL(1) << IRQ_S_SOFT)=0D +#define MIP_VSSIP (_UL(1) << IRQ_VS_SOFT)=0D +#define MIP_MSIP (_UL(1) << IRQ_M_SOFT)=0D +#define MIP_STIP (_UL(1) << IRQ_S_TIMER)=0D +#define MIP_VSTIP (_UL(1) << IRQ_VS_TIMER)=0D +#define MIP_MTIP (_UL(1) << IRQ_M_TIMER)=0D +#define MIP_SEIP (_UL(1) << IRQ_S_EXT)=0D +#define MIP_VSEIP (_UL(1) << IRQ_VS_EXT)=0D +#define MIP_MEIP (_UL(1) << IRQ_M_EXT)=0D +#define MIP_SGEIP (_UL(1) << IRQ_S_GEXT)=0D +#define MIP_LCOFIP (_UL(1) << IRQ_PMU_OVF)=0D +=0D +#define SIP_SSIP MIP_SSIP=0D +#define SIP_STIP MIP_STIP=0D +=0D +#define PRV_U _UL(0)=0D +#define PRV_S _UL(1)=0D +#define PRV_M _UL(3)=0D +=0D +#define SATP64_MODE _ULL(0xF000000000000000)=0D +#define SATP64_ASID _ULL(0x0FFFF00000000000)=0D +#define SATP64_PPN _ULL(0x00000FFFFFFFFFFF)=0D +=0D +#define SATP_MODE_OFF _UL(0)=0D +#define SATP_MODE_SV32 _UL(1)=0D +#define SATP_MODE_SV39 _UL(8)=0D +#define SATP_MODE_SV48 _UL(9)=0D +#define SATP_MODE_SV57 _UL(10)=0D +#define SATP_MODE_SV64 _UL(11)=0D +=0D +=0D +#define SATP_MODE SATP64_MODE=0D +=0D +/* =3D=3D=3D=3D=3D User-level CSRs =3D=3D=3D=3D=3D */=0D +=0D +/* User Counters/Timers */=0D +#define CSR_CYCLE 0xc00=0D +#define CSR_TIME 0xc01=0D +=0D +/* =3D=3D=3D=3D=3D Supervisor-level CSRs =3D=3D=3D=3D=3D */=0D +=0D +/* Supervisor Trap Setup */=0D +#define CSR_SSTATUS 0x100=0D +#define CSR_SEDELEG 0x102=0D +#define CSR_SIDELEG 0x103=0D +#define CSR_SIE 0x104=0D +#define CSR_STVEC 0x105=0D +=0D +/* Supervisor Configuration */=0D +#define CSR_SENVCFG 0x10a=0D +=0D +/* Supervisor Trap Handling */=0D +#define CSR_SSCRATCH 0x140=0D +#define CSR_SEPC 0x141=0D +#define CSR_SCAUSE 0x142=0D +#define CSR_STVAL 0x143=0D +#define CSR_SIP 0x144=0D +=0D +/* Supervisor Protection and Translation */=0D +#define CSR_SATP 0x180=0D +=0D +/* =3D=3D=3D=3D=3D Trap/Exception Causes =3D=3D=3D=3D=3D */=0D +=0D +#define CAUSE_MISALIGNED_FETCH 0x0=0D +#define CAUSE_FETCH_ACCESS 0x1=0D +#define CAUSE_ILLEGAL_INSTRUCTION 0x2=0D +#define CAUSE_BREAKPOINT 0x3=0D +#define CAUSE_MISALIGNED_LOAD 0x4=0D +#define CAUSE_LOAD_ACCESS 0x5=0D +#define CAUSE_MISALIGNED_STORE 0x6=0D +#define CAUSE_STORE_ACCESS 0x7=0D +#define CAUSE_USER_ECALL 0x8=0D +#define CAUSE_SUPERVISOR_ECALL 0x9=0D +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa=0D +#define CAUSE_MACHINE_ECALL 0xb=0D +#define CAUSE_FETCH_PAGE_FAULT 0xc=0D +#define CAUSE_LOAD_PAGE_FAULT 0xd=0D +#define CAUSE_STORE_PAGE_FAULT 0xf=0D +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14=0D +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15=0D +#define CAUSE_VIRTUAL_INST_FAULT 0x16=0D +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17=0D +=0D +#endif=0D diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/R= egister/RiscV64/RiscVImpl.h new file mode 100644 index 0000000000..e9ccd34039 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -0,0 +1,24 @@ +/** @file=0D + RISC-V package definitions.=0D +=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef __RISCV_IMPL_H_=0D +#define __RISCV_IMPL_H_=0D +=0D +#define _ASM_FUNC(Name, Section) \=0D + .global Name ; \=0D + .section #Section, "ax" ; \=0D + .type Name, %function ; \=0D + .p2align 2 ; \=0D + Name:=0D +=0D +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)=0D +#define RISCV_TIMER_COMPARE_BITS 32=0D +=0D +#endif=0D --=20 2.25.1