From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) by mx.groups.io with SMTP id smtpd.web08.1929.1662484155893154707 for ; Tue, 06 Sep 2022 10:09:15 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=hr1AIbSk; spf=pass (domain: ventanamicro.com, ip: 209.85.216.47, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f47.google.com with SMTP id o2-20020a17090a9f8200b0020025a22208so8416907pjp.2 for ; Tue, 06 Sep 2022 10:09:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=+7uuPcRYLmhqOk/toVPiRZOT2kZ4ke4ct3vCl0AVIU4=; b=hr1AIbSkM+Ba0L/XoIuZPT9KAOuQRw3lv8Z8b/XIe/1Hx1AqN+VNkkXyKSEU2SrLxw UFweXHaqeIwNd6hj2ZZk6lSYDOI8jNWLNl1aNBgvD9AGmH9exzNIF3g3KIiDW+cjoTXC 8wju9tqjZ63fuJAarok/dcV2hbHXAQqMpOxbYOJN4B+M+3c6kw2st9tqQjMuG8QEkLhw lluNGZXW+t1qTN3bfRJrcecww3U1QPbHkgK33jZZbJBvJnb+CriQhtw9vduvRqfm5TPU 2eH84PHcMo/OJgklWGSGSs+9ZHSTZXisLNKLuKtkMZ91Dl9038ykcgge9rI4WuiyAS9Z I0rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=+7uuPcRYLmhqOk/toVPiRZOT2kZ4ke4ct3vCl0AVIU4=; b=3hvfqCzaBP7jEplPD7dAXYJPKLSXvAhVKRbejwE8V7qhshszWeZQidn5u6zJs5z8VL IFaANZFmR0LCYO+CQ0tipOkzUuyhVTCJGUF/ww4QR+vcd3I1h9jxN+lFqqgrJ2HKnpQV BBXrnSmabm8vBeHVrM2p8RwoI3jKY2rUSOL8A8I3fZuFNKlHkbJhdaGGOAiNA9t+p6Zf w6yHrefoOJ3MRaLFiMDYZeXZc/76afPZwibTTbQL5kiOjvomskLZG6RQ25zYoT8TGaB0 wdxblFg1rfcYoNPbb1m/NRY8VHwJKuDyN8G7Hoxmwl7GC71j60Qd1xLJ9o6HZb3IAIC9 C4Iw== X-Gm-Message-State: ACgBeo2FE8ctaqhNEwHIrSoCPTPJHQ7Rstkh56Gnc6G2OmuqQc3M0INo qqRwR93queUCdIFrUM+kLBqf4yFLGv9FeeJn X-Google-Smtp-Source: AA6agR7pTHoWuXPL8wO0PDBjfMDf4MDU4OV5Nr9/DagduSsoMGhLQ2Y4Mk/xhKPAxe6OyEVMfTB9xQ== X-Received: by 2002:a17:903:245:b0:172:bf22:fc5 with SMTP id j5-20020a170903024500b00172bf220fc5mr55371089plh.101.1662484155138; Tue, 06 Sep 2022 10:09:15 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id b17-20020a170903229100b00176be258f41sm3806567plh.91.2022.09.06.10.09.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:09:13 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [RFC PATCH 06/17] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Date: Tue, 6 Sep 2022 22:38:26 +0530 Message-Id: <20220906170837.491525-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com> References: <20220906170837.491525-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable EDK2 in S-mode needs to use SSCRATCH register. Implement functions to set/get the SSCRATCH register. Signed-off-by: Sunil V L --- MdePkg/Include/Library/BaseLib.h | 10 ++++++++ MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 +++++++++++++++++++++++++ 3 files changed, 44 insertions(+) create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuGen.S diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index a6f9a194ef..a742de61a4 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -150,6 +150,16 @@ typedef struct { =0D #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8=0D =0D +VOID=0D +RiscVSetSupervisorScratch (=0D + UINT64=0D + );=0D +=0D +UINT64=0D +RiscVGetSupervisorScratch (=0D + VOID=0D + );=0D +=0D #endif // defined (MDE_CPU_RISCV64)=0D =0D //=0D diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 6be5be9428..5429329e39 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,7 @@ RiscV64/RiscVCpuPause.S | GCC=0D RiscV64/RiscVInterrupt.S | GCC=0D RiscV64/FlushCache.S | GCC=0D + RiscV64/CpuGen.S | GCC=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuGen.S b/MdePkg/Library/BaseL= ib/RiscV64/CpuGen.S new file mode 100644 index 0000000000..d11929cf32 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// Generic CPU related functions for RISC-V=0D +//=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +=0D +#include =0D +#include =0D +=0D +.data=0D +.align 3=0D +.section .text=0D +=0D +//=0D +// Set Supervisor mode scratch.=0D +// @param a0 : Value set to Supervisor mode scratch=0D +//=0D +ASM_FUNC (RiscVSetSupervisorScratch)=0D + csrrw a1, CSR_SSCRATCH, a0=0D + ret=0D +=0D +//=0D +// Get Supervisor mode scratch.=0D +// @retval a0 : Value in Supervisor mode scratch=0D +//=0D +ASM_FUNC (RiscVGetSupervisorScratch)=0D + csrr a0, CSR_SSCRATCH=0D + ret=0D --=20 2.25.1