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From: "Sunil V L" <sunilvl@ventanamicro.com>
To: devel@edk2.groups.io
Cc: Jian J Wang <jian.j.wang@intel.com>,
	Liming Gao <gaoliming@byosoft.com.cn>,
	Eric Dong <eric.dong@intel.com>, Ray Ni <ray.ni@intel.com>,
	Rahul Kumar <rahul1.kumar@intel.com>,
	Debkumar De <debkumar.de@intel.com>,
	Catharine West <catharine.west@intel.com>,
	Daniel Schaefer <git@danielschaefer.me>,
	Abner Chang <Abner.Chang@amd.com>,
	Leif Lindholm <quic_llindhol@quicinc.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	Heinrich Schuchardt <heinrich.schuchardt@canonical.com>,
	Anup Patel <apatel@ventanamicro.com>,
	Sunil V L <sunilvl@ventanamicro.com>
Subject: [RFC PATCH 08/17] MdePkg: Add RiscVSbiLib Library for RISC-V
Date: Tue,  6 Sep 2022 22:38:28 +0530	[thread overview]
Message-ID: <20220906170837.491525-9-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20220906170837.491525-1-sunilvl@ventanamicro.com>

This library is required to make SBI ecalls from the S-mode EDK2.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 MdePkg/Include/Library/RiscVSbiLib.h       | 129 ++++++++++++
 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c   | 228 +++++++++++++++++++++
 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf |  28 +++
 3 files changed, 385 insertions(+)
 create mode 100644 MdePkg/Include/Library/RiscVSbiLib.h
 create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c
 create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf

diff --git a/MdePkg/Include/Library/RiscVSbiLib.h b/MdePkg/Include/Library/RiscVSbiLib.h
new file mode 100644
index 0000000000..e94adb08fd
--- /dev/null
+++ b/MdePkg/Include/Library/RiscVSbiLib.h
@@ -0,0 +1,129 @@
+/** @file
+  Library to call the RISC-V SBI ecalls
+
+  Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Glossary:
+    - Hart - Hardware Thread, similar to a CPU core
+
+  Currently, EDK2 needs to call SBI only to set the time and to do system reset.
+
+**/
+
+#ifndef RISCV_SBI_LIB_H_
+#define RISCV_SBI_LIB_H_
+
+#include <Uefi.h>
+
+/* SBI Extension IDs */
+#define SBI_EXT_TIME   0x54494D45
+#define SBI_EXT_SRST   0x53525354
+
+/* SBI function IDs for TIME extension*/
+#define SBI_EXT_TIME_SET_TIMER                  0x0
+
+/* SBI function IDs for SRST extension */
+#define SBI_EXT_SRST_RESET                      0x0
+
+#define SBI_SRST_RESET_TYPE_SHUTDOWN            0x0
+#define SBI_SRST_RESET_TYPE_COLD_REBOOT         0x1
+#define SBI_SRST_RESET_TYPE_WARM_REBOOT         0x2
+#define SBI_SRST_RESET_TYPE_LAST     SBI_SRST_RESET_TYPE_WARM_REBOOT
+
+#define SBI_SRST_RESET_REASON_NONE              0x0
+#define SBI_SRST_RESET_REASON_SYSFAIL           0x1
+
+/* SBI return error codes */
+#define SBI_SUCCESS                              0
+#define SBI_ERR_FAILED                          -1
+#define SBI_ERR_NOT_SUPPORTED                   -2
+#define SBI_ERR_INVALID_PARAM                   -3
+#define SBI_ERR_DENIED                          -4
+#define SBI_ERR_INVALID_ADDRESS                 -5
+#define SBI_ERR_ALREADY_AVAILABLE               -6
+#define SBI_ERR_ALREADY_STARTED                 -7
+#define SBI_ERR_ALREADY_STOPPED                 -8
+
+#define SBI_LAST_ERR                 SBI_ERR_ALREADY_STOPPED
+
+typedef struct {
+  UINT64 BootHartId;
+  VOID   *PeiServiceTable;    // PEI Service table
+  UINT64 FlattenedDeviceTree; // Pointer to Flattened Device tree
+} EFI_RISCV_FIRMWARE_CONTEXT;
+
+
+//
+// EDK2 OpenSBI firmware extension return status.
+//
+typedef struct {
+  UINTN    Error; ///< SBI status code
+  UINTN    Value; ///< Value returned
+} SBI_RET;
+
+VOID
+EFIAPI
+SbiSetTimer (
+  IN  UINT64  Time
+  );
+
+EFI_STATUS
+EFIAPI
+SbiSystemReset (
+  IN  UINTN  ResetType,
+  IN  UINTN  ResetReason
+  );
+
+/**
+  Get firmware context of the calling hart.
+
+  @param[out] FirmwareContext      The firmware context pointer.
+**/
+VOID
+EFIAPI
+GetFirmwareContext (
+  OUT EFI_RISCV_FIRMWARE_CONTEXT  **FirmwareContext
+  );
+
+/**
+  Set firmware context of the calling hart.
+
+  @param[in] FirmwareContext       The firmware context pointer.
+**/
+VOID
+EFIAPI
+SetFirmwareContext (
+  IN EFI_RISCV_FIRMWARE_CONTEXT  *FirmwareContext
+  );
+
+/**
+  Get pointer to OpenSBI Firmware Context
+
+  Get the pointer of firmware context.
+
+  @param    FirmwareContextPtr   Pointer to retrieve pointer to the
+                                 Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+  IN OUT EFI_RISCV_FIRMWARE_CONTEXT  **FirmwareContextPtr
+  );
+
+/**
+  Set pointer to OpenSBI Firmware Context
+
+  Set the pointer of firmware context.
+
+  @param    FirmwareContextPtr   Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+  IN EFI_RISCV_FIRMWARE_CONTEXT  *FirmwareContextPtr
+  );
+
+#endif
diff --git a/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c
new file mode 100644
index 0000000000..39cc6628be
--- /dev/null
+++ b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c
@@ -0,0 +1,228 @@
+/** @file
+  Instance of the SBI ecall library.
+
+  It allows calling an SBI function via an ecall from S-Mode.
+
+  Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/RiscVSbiLib.h>
+#include <Register/RiscV64/RiscVAsm.h>
+
+//
+// Maximum arguments for SBI ecall
+// It's possible to pass more but no SBI call uses more as of SBI 0.2.
+// The additional arguments would have to be passed on the stack instead of as
+// registers, like it's done now.
+//
+#define SBI_CALL_MAX_ARGS  6
+
+/**
+  Call SBI call using ecall instruction.
+
+  Asserts when NumArgs exceeds SBI_CALL_MAX_ARGS.
+
+  @param[in] ExtId    SBI extension ID.
+  @param[in] FuncId   SBI function ID.
+  @param[in] NumArgs  Number of arguments to pass to the ecall.
+  @param[in] ...      Argument list for the ecall.
+
+  @retval  Returns SBI_RET structure with value and error code.
+
+**/
+STATIC
+SBI_RET
+EFIAPI
+SbiCall (
+  IN  UINTN  ExtId,
+  IN  UINTN  FuncId,
+  IN  UINTN  NumArgs,
+  ...
+  )
+{
+  UINTN    I;
+  SBI_RET  Ret;
+  UINTN    Args[SBI_CALL_MAX_ARGS];
+  VA_LIST  ArgList;
+
+  VA_START (ArgList, NumArgs);
+
+  ASSERT (NumArgs <= SBI_CALL_MAX_ARGS);
+
+  for (I = 0; I < SBI_CALL_MAX_ARGS; I++) {
+    if (I < NumArgs) {
+      Args[I] = VA_ARG (ArgList, UINTN);
+    } else {
+      // Default to 0 for all arguments that are not given
+      Args[I] = 0;
+    }
+  }
+
+  VA_END (ArgList);
+
+  register UINTN  a0 asm ("a0") = Args[0];
+  register UINTN  a1 asm ("a1") = Args[1];
+  register UINTN  a2 asm ("a2") = Args[2];
+  register UINTN  a3 asm ("a3") = Args[3];
+  register UINTN  a4 asm ("a4") = Args[4];
+  register UINTN  a5 asm ("a5") = Args[5];
+  register UINTN  a6 asm ("a6") = (UINTN)(FuncId);
+  register UINTN  a7 asm ("a7") = (UINTN)(ExtId);
+
+  asm volatile ("ecall" \
+       : "+r" (a0), "+r" (a1) \
+       : "r" (a2), "r" (a3), "r" (a4), "r" (a5), "r" (a6), "r" (a7) \
+       : "memory"); \
+  Ret.Error = a0;
+  Ret.Value = a1;
+  return Ret;
+}
+
+/**
+  Translate SBI error code to EFI status.
+
+  @param[in] SbiError   SBI error code
+  @retval EFI_STATUS
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+TranslateError (
+  IN  UINTN  SbiError
+  )
+{
+  switch (SbiError) {
+    case SBI_SUCCESS:
+      return EFI_SUCCESS;
+    case SBI_ERR_FAILED:
+      return EFI_DEVICE_ERROR;
+      break;
+    case SBI_ERR_NOT_SUPPORTED:
+      return EFI_UNSUPPORTED;
+      break;
+    case SBI_ERR_INVALID_PARAM:
+      return EFI_INVALID_PARAMETER;
+      break;
+    case SBI_ERR_DENIED:
+      return EFI_ACCESS_DENIED;
+      break;
+    case SBI_ERR_INVALID_ADDRESS:
+      return EFI_LOAD_ERROR;
+      break;
+    case SBI_ERR_ALREADY_AVAILABLE:
+      return EFI_ALREADY_STARTED;
+      break;
+    default:
+      //
+      // Reaches here only if SBI has defined a new error type
+      //
+      ASSERT (FALSE);
+      return EFI_UNSUPPORTED;
+      break;
+  }
+}
+
+/**
+  Clear pending timer interrupt bit and set timer for next event after Time.
+
+  To clear the timer without scheduling a timer event, set Time to a
+  practically infinite value or mask the timer interrupt by clearing sie.STIE.
+
+  @param[in]  Time                 The time offset to the next scheduled timer interrupt.
+**/
+VOID
+EFIAPI
+SbiSetTimer (
+  IN  UINT64  Time
+  )
+{
+  SbiCall (SBI_EXT_TIME, SBI_EXT_TIME_SET_TIMER, 1, Time);
+}
+
+EFI_STATUS
+EFIAPI
+SbiSystemReset (
+  IN  UINTN  ResetType,
+  IN  UINTN  ResetReason
+  )
+{
+  SBI_RET  Ret;
+
+  Ret = SbiCall (
+          SBI_EXT_SRST,
+          SBI_EXT_SRST_RESET,
+          2,
+          ResetType,
+          ResetReason
+          );
+
+  return TranslateError (Ret.Error);
+}
+
+/**
+  Get firmware context of the calling hart.
+
+  @param[out] FirmwareContext      The firmware context pointer.
+  @retval EFI_SUCCESS              The operation succeeds.
+**/
+VOID
+EFIAPI
+GetFirmwareContext (
+  OUT EFI_RISCV_FIRMWARE_CONTEXT  **FirmwareContext
+  )
+{
+  *FirmwareContext = (EFI_RISCV_FIRMWARE_CONTEXT *)csr_read(CSR_SSCRATCH);
+}
+
+/**
+  Set firmware context of the calling hart.
+
+  @param[in] FirmwareContext       The firmware context pointer.
+**/
+VOID
+EFIAPI
+SetFirmwareContext (
+  IN EFI_RISCV_FIRMWARE_CONTEXT  *FirmwareContext
+  )
+{
+  csr_write(CSR_SSCRATCH, FirmwareContext);
+}
+
+/**
+  Get pointer to OpenSBI Firmware Context
+
+  Get the pointer of firmware context through OpenSBI FW Extension SBI.
+
+  @param    FirmwareContextPtr   Pointer to retrieve pointer to the
+                                 Firmware Context.
+**/
+VOID
+EFIAPI
+GetFirmwareContextPointer (
+  IN OUT EFI_RISCV_FIRMWARE_CONTEXT **FirmwareContextPtr
+  )
+{
+  GetFirmwareContext (FirmwareContextPtr);
+}
+
+/**
+  Set the pointer to OpenSBI Firmware Context
+
+  Set the pointer of firmware context through OpenSBI FW Extension SBI.
+
+  @param    FirmwareContextPtr   Pointer to Firmware Context.
+**/
+VOID
+EFIAPI
+SetFirmwareContextPointer (
+  IN EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContextPtr
+  )
+{
+  SetFirmwareContext (FirmwareContextPtr);
+}
diff --git a/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf
new file mode 100644
index 0000000000..b01f909300
--- /dev/null
+++ b/MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf
@@ -0,0 +1,28 @@
+## @file
+# RISC-V Library to call SBI ecalls
+#
+#  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION    = 0x0001001b
+  BASE_NAME      = RiscVSbiLib
+  FILE_GUID      = D742CF3D-E600-4009-8FB5-318073008508
+  MODULE_TYPE    = BASE
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = RiscVSbiLib
+
+[Sources]
+  RiscVSbiLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+  BaseLib
+
-- 
2.25.1


  parent reply	other threads:[~2022-09-06 17:09 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-06 17:08 [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Sunil V L
2022-09-06 17:08 ` [RFC PATCH 01/17] MdePkg/Register: Add register definition header files for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 02/17] MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID Sunil V L
2022-09-06 17:08 ` [RFC PATCH 03/17] MdePkg/Protocol: Add RiscVBootProtocol.h Sunil V L
2022-09-06 17:08 ` [RFC PATCH 04/17] MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 05/17] UefiCpuPkg.dec: Add PCD variable " Sunil V L
2022-09-06 17:08 ` [RFC PATCH 06/17] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Sunil V L
2022-09-06 17:08 ` [RFC PATCH 07/17] MdePkg: Add ArchTimerLib library Sunil V L
2022-09-06 17:08 ` Sunil V L [this message]
2022-09-06 17:08 ` [RFC PATCH 09/17] UefiCpuPkg/DxeCpuExceptionHandlerLib: Refactor to add other architectures Sunil V L
2022-09-06 17:08 ` [RFC PATCH 10/17] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib Sunil V L
2022-09-06 17:08 ` [RFC PATCH 11/17] MdePkg/Library: Add ResetSystemLib library Sunil V L
2022-09-06 17:08 ` [RFC PATCH 12/17] UefiCpuPkg/SecCore: Add SEC startup code for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 13/17] MdePkg: Add PlatformPeiLib library Sunil V L
2022-09-06 17:08 ` [RFC PATCH 14/17] MdeModulePkg/Universal: Add PlatformPei module for RISC-V Sunil V L
2022-09-06 17:08 ` [RFC PATCH 15/17] UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures Sunil V L
2022-09-06 17:08 ` [RFC PATCH 16/17] UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module Sunil V L
2022-09-07  9:32   ` Chang, Abner
2022-09-07 11:22     ` Sunil V L
2022-09-07 12:46       ` Chang, Abner
2022-09-08 10:53         ` Sunil V L
2022-09-08 12:02           ` Chang, Abner
2022-09-06 17:08 ` [RFC PATCH 17/17] MdeModulePkg/Universal: Add TimerDxe module Sunil V L
2022-09-07  5:54 ` [edk2-devel] [RFC PATCH 00/17] Refactor and add RISC-V support in edk2 repo Gerd Hoffmann

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