From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) by mx.groups.io with SMTP id smtpd.web11.6314.1662549134125279691 for ; Wed, 07 Sep 2022 04:12:40 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=SiDQfT25; spf=pass (domain: ventanamicro.com, ip: 209.85.216.54, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f54.google.com with SMTP id pj10so3756395pjb.2 for ; Wed, 07 Sep 2022 04:12:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9ScHOdadCsqYIZ/Gv0CbY0qjdJKvq8sQpNWACgK57SQ=; b=SiDQfT25fRZn19MkIWnOaGtGedXMP3IAbo9eMR0bd3pA2xf88k1VOgO6wlk8CLMnsP CFePcjGfDwuE3gVapgMlxuqGGv8War1rcu7kIHJVlrrYC1frF6rWSuOv4PCV1sX69C25 A5NBVtPZx241miU2ilVKuYdaygjRnanjDYFcfyt1VmE4t2zBjIRt/naENFSTwDiSwj5c zvGliCloQD7o5njmAMg3OFId5ABHmmkgi+Zl0hFC5016GIr3DUsTsAJHD7v39et4np2t 6Rr5aTSdfQRkSj/aazPj/bKNGxQoeEYBQcdVozh9KsGgzTWwArejdPhjPUI0nEreIwkP SPNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9ScHOdadCsqYIZ/Gv0CbY0qjdJKvq8sQpNWACgK57SQ=; b=ELxIWmqo35vKAs24LLO0uTCxi3P2O8S1+pKQBuJcDb/8HZMRbilyBepuplWkPxH3Ms WzinSyIVYhlKV4NPBlgPpYjcooN6+KoWzoHqtAogBcJXL2RlPJM2+hPeSvAVUuHny+4+ ycAFrFvb6uvEV7hGO4Bh/j7ubdDHM5nsNj7LpD+ZaXYQXelNfRYOvOX1GiOghMq3cV/Z gNzNunE3qSAUSqO3DeOx0zF5T/WcWmKhPUGMcXFxPe5MoOCSYWxhtqA8LspV2OZQM07e Z095syu0gwAId5V/iEnnh8/SVxjSHgRC+sZsv5ESuELje2lgR69w8htOcUwPH5/A+od+ ByyQ== X-Gm-Message-State: ACgBeo2jKljXKdjhrC69MSsADMjX0jK2O1JyPl2k5j5uBsfp1XUH3CMv 4aiTav4zRjIB06dJ/UJ/IUWnx2YPOaasKaPf X-Google-Smtp-Source: AA6agR6OlZnteW3qTedKaumc0sVxtgZ+MwD82RKFAHo/yZ6r0XC68dNDgdfbYIa+yiA2/UYCTzV4fQ== X-Received: by 2002:a17:902:ba8e:b0:172:ddb9:fe45 with SMTP id k14-20020a170902ba8e00b00172ddb9fe45mr3407462pls.86.1662549160014; Wed, 07 Sep 2022 04:12:40 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:12:39 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [RFC PATCH V2 10/19] UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib Date: Wed, 7 Sep 2022 16:41:16 +0530 Message-Id: <20220907111125.539698-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Add low level interfaces to register exception and interrupt handlers for RISC-V. Signed-off-by: Sunil V L --- UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf = | 7 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h= | 112 ++++++++++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c= | 136 ++++++++++++++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S = | 105 +++++++++++++++ 4 files changed, 359 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index bf33d54bae13..8570b83e8afb 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -18,7 +18,7 @@ [Defines] #=0D # The following information is for reference only and not required by the = build tools.=0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64=0D +# VALID_ARCHITECTURES =3D IA32 X64 RISCV64=0D #=0D =0D [Sources.Ia32]=0D @@ -38,6 +38,11 @@ [Sources.IA32, Sources.X64] PeiDxeSmmCpuException.c=0D DxeException.c=0D =0D +[Sources.RISCV64]=0D + RiscV64/SupervisorTrapHandler.S=0D + RiscV64/CpuExceptionHandlerLib.c=0D + RiscV64/CpuExceptionHandlerLib.h=0D +=0D [Pcd]=0D gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard=0D gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList=0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.h new file mode 100644 index 000000000000..1cc6dbe73420 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.h @@ -0,0 +1,112 @@ +/** @file=0D +=0D + RISC-V Exception Handler library definition file.=0D +=0D + Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All = rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef RISCV_CPU_EXECPTION_HANDLER_LIB_H_=0D +#define RISCV_CPU_EXECPTION_HANDLER_LIB_H_=0D +=0D +#include =0D +#include =0D +extern void=0D +SupervisorModeTrap (=0D + void=0D + );=0D +=0D +//=0D +// Index of SMode trap register=0D +//=0D +#define SMODE_TRAP_REGS_zero 0=0D +#define SMODE_TRAP_REGS_ra 1=0D +#define SMODE_TRAP_REGS_sp 2=0D +#define SMODE_TRAP_REGS_gp 3=0D +#define SMODE_TRAP_REGS_tp 4=0D +#define SMODE_TRAP_REGS_t0 5=0D +#define SMODE_TRAP_REGS_t1 6=0D +#define SMODE_TRAP_REGS_t2 7=0D +#define SMODE_TRAP_REGS_s0 8=0D +#define SMODE_TRAP_REGS_s1 9=0D +#define SMODE_TRAP_REGS_a0 10=0D +#define SMODE_TRAP_REGS_a1 11=0D +#define SMODE_TRAP_REGS_a2 12=0D +#define SMODE_TRAP_REGS_a3 13=0D +#define SMODE_TRAP_REGS_a4 14=0D +#define SMODE_TRAP_REGS_a5 15=0D +#define SMODE_TRAP_REGS_a6 16=0D +#define SMODE_TRAP_REGS_a7 17=0D +#define SMODE_TRAP_REGS_s2 18=0D +#define SMODE_TRAP_REGS_s3 19=0D +#define SMODE_TRAP_REGS_s4 20=0D +#define SMODE_TRAP_REGS_s5 21=0D +#define SMODE_TRAP_REGS_s6 22=0D +#define SMODE_TRAP_REGS_s7 23=0D +#define SMODE_TRAP_REGS_s8 24=0D +#define SMODE_TRAP_REGS_s9 25=0D +#define SMODE_TRAP_REGS_s10 26=0D +#define SMODE_TRAP_REGS_s11 27=0D +#define SMODE_TRAP_REGS_t3 28=0D +#define SMODE_TRAP_REGS_t4 29=0D +#define SMODE_TRAP_REGS_t5 30=0D +#define SMODE_TRAP_REGS_t6 31=0D +#define SMODE_TRAP_REGS_sepc 32=0D +#define SMODE_TRAP_REGS_sstatus 33=0D +#define SMODE_TRAP_REGS_sie 34=0D +#define SMODE_TRAP_REGS_last 35=0D +=0D +#define SMODE_TRAP_REGS_OFFSET(x) ((SMODE_TRAP_REGS_##x) * __SIZEOF_POINT= ER__)=0D +#define SMODE_TRAP_REGS_SIZE SMODE_TRAP_REGS_OFFSET(last)=0D +=0D +#pragma pack(1)=0D +typedef struct {=0D + //=0D + // Below are follow the format of EFI_SYSTEM_CONTEXT=0D + //=0D + UINT64 zero;=0D + UINT64 ra;=0D + UINT64 sp;=0D + UINT64 gp;=0D + UINT64 tp;=0D + UINT64 t0;=0D + UINT64 t1;=0D + UINT64 t2;=0D + UINT64 s0;=0D + UINT64 s1;=0D + UINT64 a0;=0D + UINT64 a1;=0D + UINT64 a2;=0D + UINT64 a3;=0D + UINT64 a4;=0D + UINT64 a5;=0D + UINT64 a6;=0D + UINT64 a7;=0D + UINT64 s2;=0D + UINT64 s3;=0D + UINT64 s4;=0D + UINT64 s5;=0D + UINT64 s6;=0D + UINT64 s7;=0D + UINT64 s8;=0D + UINT64 s9;=0D + UINT64 s10;=0D + UINT64 s11;=0D + UINT64 t3;=0D + UINT64 t4;=0D + UINT64 t5;=0D + UINT64 t6;=0D + //=0D + // Below are the additional information to=0D + // EFI_SYSTEM_CONTEXT, private to supervisor mode trap=0D + // and not public to EFI environment.=0D + //=0D + UINT64 sepc;=0D + UINT64 sstatus;=0D + UINT64 sie;=0D +} SMODE_TRAP_REGISTERS;=0D +#pragma pack()=0D +=0D +#endif=0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuException= HandlerLib.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExcepti= onHandlerLib.c new file mode 100644 index 000000000000..f4427599a6b7 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandler= Lib.c @@ -0,0 +1,136 @@ +/** @file=0D + RISC-V Exception Handler library implementation.=0D +=0D + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "CpuExceptionHandlerLib.h"=0D +=0D +STATIC EFI_CPU_INTERRUPT_HANDLER mInterruptHandlers[2];=0D +=0D +/**=0D + Initializes all CPU exceptions entries and provides the default exceptio= n handlers.=0D +=0D + Caller should try to get an array of interrupt and/or exception vectors = that are in use and need to=0D + persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification.=0D + If caller cannot get reserved vector list or it does not exists, set Vec= torInfo to NULL.=0D + If VectorInfo is not NULL, the exception vectors will be initialized per= vector attribute accordingly.=0D +=0D + @param[in] VectorInfo Pointer to reserved vector list.=0D +=0D + @retval EFI_SUCCESS CPU Exception Entries have been successful= ly initialized=0D + with default exception handlers.=0D + @retval EFI_INVALID_PARAMETER VectorInfo includes the invalid content if= VectorInfo is not NULL.=0D + @retval EFI_UNSUPPORTED This function is not supported.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializeCpuExceptionHandlers (=0D + IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL=0D + )=0D +{=0D + csr_write (CSR_STVEC, SupervisorModeTrap);=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Registers a function to be called from the processor interrupt handler.= =0D +=0D + This function registers and enables the handler specified by InterruptHa= ndler for a processor=0D + interrupt or exception type specified by InterruptType. If InterruptHand= ler is NULL, then the=0D + handler for the processor interrupt or exception type specified by Inter= ruptType is uninstalled.=0D + The installed handler is called once for each processor interrupt or exc= eption.=0D + NOTE: This function should be invoked after InitializeCpuExceptionHandle= rs() or=0D + InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED retu= rned.=0D +=0D + @param[in] InterruptType Defines which interrupt or exception to ho= ok.=0D + @param[in] InterruptHandler A pointer to a function of type EFI_CPU_IN= TERRUPT_HANDLER that is called=0D + when a processor interrupt occurs. If this= parameter is NULL, then the handler=0D + will be uninstalled.=0D +=0D + @retval EFI_SUCCESS The handler for the processor interrupt wa= s successfully installed or uninstalled.=0D + @retval EFI_ALREADY_STARTED InterruptHandler is not NULL, and a handle= r for InterruptType was=0D + previously installed.=0D + @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler fo= r InterruptType was not=0D + previously installed.=0D + @retval EFI_UNSUPPORTED The interrupt specified by InterruptType i= s not supported,=0D + or this function is not supported.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +RegisterCpuInterruptHandler (=0D + IN EFI_EXCEPTION_TYPE InterruptType,=0D + IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "%a: Type:%x Handler: %x\n", __FUNCTION__, Interrupt= Type, InterruptHandler));=0D + mInterruptHandlers[InterruptType] =3D InterruptHandler;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Setup separate stacks for certain exception handlers.=0D + If the input Buffer and BufferSize are both NULL, use global variable if= possible.=0D +=0D + @param[in] Buffer Point to buffer used to separate exceptio= n stack.=0D + @param[in, out] BufferSize On input, it indicates the byte size of B= uffer.=0D + If the size is not enough, the return sta= tus will=0D + be EFI_BUFFER_TOO_SMALL, and output Buffe= rSize=0D + will be the size it needs.=0D +=0D + @retval EFI_SUCCESS The stacks are assigned successfully.=0D + @retval EFI_UNSUPPORTED This function is not supported.=0D + @retval EFI_BUFFER_TOO_SMALL This BufferSize is too small.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializeSeparateExceptionStacks (=0D + IN VOID *Buffer,=0D + IN OUT UINTN *BufferSize=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Supervisor mode trap handler.=0D +=0D + @param[in] SmodeTrapReg Registers before trap occurred.=0D +=0D +**/=0D +VOID=0D +RiscVSupervisorModeTrapHandler (=0D + SMODE_TRAP_REGISTERS *SmodeTrapReg=0D + )=0D +{=0D + UINTN SCause;=0D + EFI_SYSTEM_CONTEXT RiscVSystemContext;=0D +=0D + RiscVSystemContext.SystemContextRiscV64 =3D (EFI_SYSTEM_CONTEXT_RISCV64 = *)SmodeTrapReg;=0D + //=0D + // Check scasue register.=0D + //=0D + SCause =3D (UINTN)csr_read (CSR_SCAUSE);=0D + if ((SCause & (1UL << (sizeof (UINTN) * 8- 1))) !=3D 0) {=0D + //=0D + // This is interrupt event.=0D + //=0D + SCause &=3D ~(1UL << (sizeof (UINTN) * 8- 1));=0D + if ((SCause =3D=3D IRQ_S_TIMER) && (mInterruptHandlers[EXCEPT_RISCV_TI= MER_INT] !=3D NULL)) {=0D + mInterruptHandlers[EXCEPT_RISCV_TIMER_INT](EXCEPT_RISCV_TIMER_INT, R= iscVSystemContext);=0D + }=0D + }=0D +}=0D diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTr= apHandler.S b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorT= rapHandler.S new file mode 100644 index 000000000000..649c4c5becf4 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandl= er.S @@ -0,0 +1,105 @@ +/** @file=0D + RISC-V Processor supervisor mode trap handler=0D +=0D + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +#include "CpuExceptionHandlerLib.h"=0D +=0D + .align 3=0D + .section .entry, "ax", %progbits=0D + .globl SupervisorModeTrap=0D +SupervisorModeTrap:=0D + addi sp, sp, -SMODE_TRAP_REGS_SIZE=0D +=0D + /* Save all general regisers except SP */=0D + sd t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)=0D +=0D + csrr t0, CSR_SSTATUS=0D + and t0, t0, (SSTATUS_SIE | SSTATUS_SPIE)=0D + sd t0, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)=0D + csrr t0, CSR_SEPC=0D + sd t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)=0D + csrr t0, CSR_SIE=0D + sd t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)=0D + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)=0D +=0D + sd ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)=0D + sd gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)=0D + sd tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)=0D + sd t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)=0D + sd t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)=0D + sd s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)=0D + sd s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)=0D + sd a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)=0D + sd a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)=0D + sd a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)=0D + sd a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)=0D + sd a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)=0D + sd a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)=0D + sd a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)=0D + sd a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)=0D + sd s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)=0D + sd s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)=0D + sd s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)=0D + sd s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)=0D + sd s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)=0D + sd s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)=0D + sd s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)=0D + sd s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)=0D + sd s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)=0D + sd s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)=0D + sd t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)=0D + sd t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)=0D + sd t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)=0D + sd t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)=0D +=0D + /* Call to Supervisor mode trap handler in CpuExceptionHandlerLib.c */=0D + call RiscVSupervisorModeTrapHandler=0D +=0D + /* Restore all general regisers except SP */=0D + ld ra, SMODE_TRAP_REGS_OFFSET(ra)(sp)=0D + ld gp, SMODE_TRAP_REGS_OFFSET(gp)(sp)=0D + ld tp, SMODE_TRAP_REGS_OFFSET(tp)(sp)=0D + ld t2, SMODE_TRAP_REGS_OFFSET(t2)(sp)=0D + ld s0, SMODE_TRAP_REGS_OFFSET(s0)(sp)=0D + ld s1, SMODE_TRAP_REGS_OFFSET(s1)(sp)=0D + ld a0, SMODE_TRAP_REGS_OFFSET(a0)(sp)=0D + ld a1, SMODE_TRAP_REGS_OFFSET(a1)(sp)=0D + ld a2, SMODE_TRAP_REGS_OFFSET(a2)(sp)=0D + ld a3, SMODE_TRAP_REGS_OFFSET(a3)(sp)=0D + ld a4, SMODE_TRAP_REGS_OFFSET(a4)(sp)=0D + ld a5, SMODE_TRAP_REGS_OFFSET(a5)(sp)=0D + ld a6, SMODE_TRAP_REGS_OFFSET(a6)(sp)=0D + ld a7, SMODE_TRAP_REGS_OFFSET(a7)(sp)=0D + ld s2, SMODE_TRAP_REGS_OFFSET(s2)(sp)=0D + ld s3, SMODE_TRAP_REGS_OFFSET(s3)(sp)=0D + ld s4, SMODE_TRAP_REGS_OFFSET(s4)(sp)=0D + ld s5, SMODE_TRAP_REGS_OFFSET(s5)(sp)=0D + ld s6, SMODE_TRAP_REGS_OFFSET(s6)(sp)=0D + ld s7, SMODE_TRAP_REGS_OFFSET(s7)(sp)=0D + ld s8, SMODE_TRAP_REGS_OFFSET(s8)(sp)=0D + ld s9, SMODE_TRAP_REGS_OFFSET(s9)(sp)=0D + ld s10, SMODE_TRAP_REGS_OFFSET(s10)(sp)=0D + ld s11, SMODE_TRAP_REGS_OFFSET(s11)(sp)=0D + ld t3, SMODE_TRAP_REGS_OFFSET(t3)(sp)=0D + ld t4, SMODE_TRAP_REGS_OFFSET(t4)(sp)=0D + ld t5, SMODE_TRAP_REGS_OFFSET(t5)(sp)=0D + ld t6, SMODE_TRAP_REGS_OFFSET(t6)(sp)=0D +=0D + ld t0, SMODE_TRAP_REGS_OFFSET(sepc)(sp)=0D + csrw CSR_SEPC, t0=0D + ld t0, SMODE_TRAP_REGS_OFFSET(sie)(sp)=0D + csrw CSR_SIE, t0=0D + csrr t0, CSR_SSTATUS=0D + ld t1, SMODE_TRAP_REGS_OFFSET(sstatus)(sp)=0D + or t0, t0, t1=0D + csrw CSR_SSTATUS, t0=0D + ld t1, SMODE_TRAP_REGS_OFFSET(t1)(sp)=0D + ld t0, SMODE_TRAP_REGS_OFFSET(t0)(sp)=0D + addi sp, sp, SMODE_TRAP_REGS_SIZE=0D + sret=0D --=20 2.25.1