From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f43.google.com (mail-pj1-f43.google.com [209.85.216.43]) by mx.groups.io with SMTP id smtpd.web10.6313.1662549122987684154 for ; Wed, 07 Sep 2022 04:12:03 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=mXyilspK; spf=pass (domain: ventanamicro.com, ip: 209.85.216.43, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f43.google.com with SMTP id p1-20020a17090a2d8100b0020040a3f75eso9476857pjd.4 for ; Wed, 07 Sep 2022 04:12:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=luBNOC9OW/5RTCSjJA5G0KuwdZm2Xtcpl+4m1ny0Qic=; b=mXyilspKXdSRWPCzL/Wq2oxUXr1pgNEbt5jDsJo8m/jM0G4UJiKvZMKQfgNOiwOLzd pmxQ1Tz3wbk9q3/AxwnwmSOddgW8wVSs7n4hq3XHc1TmEJB7K1Fqt82aXRU/kZG5mERW 1qwZQw8MDyt85dh5rHGrxTz5mAkivDXk33aUkSpV65A3f5VCOcZYyu+Q7s885AFg/WSJ KwmFAAo39PTq1dPrANnuL3ZJwnxvfokI0JWNHoo0MCffmxGIzjiFKcs0+o/saI8PAO0z Wa27fUEGqdc/URy8I2myFEaweGuNhCOWg55qC1x3mS4lLAqGmpIvCr3v0MUXqhVuHfiv J0yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=luBNOC9OW/5RTCSjJA5G0KuwdZm2Xtcpl+4m1ny0Qic=; b=nvdvjBjrC3+HenTuQ6sFV+GzYb6USlfGtPnuhrosqqKyd37FXMQnFEdE6ULdX9ODe9 bRoCOc8qY04vZO3codz0GNdCezUtS8UghuV7Q4+vaeSGduKcs8hk7zN+Pv9mfcj8J9EA Xx6U/cz6DrmI+3b0VmQIo9an/dkqlTFVGjYZ1hmgX3F5qraq97KEs8vOllMeoHsU6fKb 6BUe4J0RtR4+E9oxXFbNRC5GiB+XapuayfgdAfc4H9vnZQy5Iee552cpmkS/Y/HGG/O+ x+sf3+XPoUYvozQG6W8/CiRMdDgAoCXDwgW2EgX1018FusuIlP602P5fynMfXvKtqizy R8kw== X-Gm-Message-State: ACgBeo3ImkBvaw7GKbjLegIDGu8mezuWXAqxGYUwTGw54mJyk3UeGRmy jy80I0GxH2c2rF2tYx0qqqMp51MV6g6XYKGe X-Google-Smtp-Source: AA6agR486ubiFL95sOqEGL26Ah0vYsSiPObJhMY32zLZ0LJ3WVbejVMbkkfNFpWVvsm5Lo+PwDTmaw== X-Received: by 2002:a17:90b:2708:b0:200:22d2:6768 with SMTP id px8-20020a17090b270800b0020022d26768mr3460228pjb.73.1662549122289; Wed, 07 Sep 2022 04:12:02 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id y5-20020aa79ae5000000b0052b84ca900csm12208518pfp.62.2022.09.07.04.11.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:12:01 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [RFC PATCH V2 06/19] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Date: Wed, 7 Sep 2022 16:41:12 +0530 Message-Id: <20220907111125.539698-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220907111125.539698-1-sunilvl@ventanamicro.com> References: <20220907111125.539698-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable EDK2 in S-mode needs to use SSCRATCH register. Implement functions to set/get the SSCRATCH register. Signed-off-by: Sunil V L --- MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Include/Library/BaseLib.h | 10 ++++++ MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 ++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 6be5be9428f2..5429329e39b0 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,7 @@ [Sources.RISCV64] RiscV64/RiscVCpuPause.S | GCC=0D RiscV64/RiscVInterrupt.S | GCC=0D RiscV64/FlushCache.S | GCC=0D + RiscV64/CpuGen.S | GCC=0D =0D [Packages]=0D MdePkg/MdePkg.dec=0D diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index a6f9a194ef1c..a742de61a442 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -150,6 +150,16 @@ typedef struct { =0D #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8=0D =0D +VOID=0D +RiscVSetSupervisorScratch (=0D + UINT64=0D + );=0D +=0D +UINT64=0D +RiscVGetSupervisorScratch (=0D + VOID=0D + );=0D +=0D #endif // defined (MDE_CPU_RISCV64)=0D =0D //=0D diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuGen.S b/MdePkg/Library/BaseL= ib/RiscV64/CpuGen.S new file mode 100644 index 000000000000..d11929cf3233 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------= ------=0D +//=0D +// Generic CPU related functions for RISC-V=0D +//=0D +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
= =0D +//=0D +// SPDX-License-Identifier: BSD-2-Clause-Patent=0D +//=0D +//------------------------------------------------------------------------= ------=0D +=0D +#include =0D +#include =0D +=0D +.data=0D +.align 3=0D +.section .text=0D +=0D +//=0D +// Set Supervisor mode scratch.=0D +// @param a0 : Value set to Supervisor mode scratch=0D +//=0D +ASM_FUNC (RiscVSetSupervisorScratch)=0D + csrrw a1, CSR_SSCRATCH, a0=0D + ret=0D +=0D +//=0D +// Get Supervisor mode scratch.=0D +// @retval a0 : Value in Supervisor mode scratch=0D +//=0D +ASM_FUNC (RiscVGetSupervisorScratch)=0D + csrr a0, CSR_SSCRATCH=0D + ret=0D --=20 2.25.1