From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f180.google.com (mail-pf1-f180.google.com [209.85.210.180]) by mx.groups.io with SMTP id smtpd.web11.6484.1662550599305732161 for ; Wed, 07 Sep 2022 04:36:39 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=d04RdQ/K; spf=pass (domain: ventanamicro.com, ip: 209.85.210.180, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f180.google.com with SMTP id b144so9543944pfb.7 for ; Wed, 07 Sep 2022 04:36:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=TfWnwA0PNApuz8cZrLf1v5XuPT5yX/dQbzIYGGUxqoU=; b=d04RdQ/KpQgwMnrsLqj4pkeLIS1y1BIY0PNLym0XrCnjfhKDmqJSujXyaY+cMDMpic TF+E9GaHtiveBazkcraoMDoCNkTT7TM6ks7478lcNLhgoRhuaGSBa7ASLRvgnea56xX7 Xv3G3vsPXUtvqI2y9ZwDYntztKXs5pJpIQqi0jd43w01PB9IwlYlZO9Sn1Uru94c12HZ u2O+nGVVq2pnox/ZFSRZpJo+Fn7aUlVrQP7nKqqxhKjZaY6UxSuMNryJjHnHhW04THsL SJpWRJOtROvRip8p5ib8BF8e41y+CHrxkPw+MHxzqJnOlzDkcPhHxm6iSSfBL/qba2nB +O0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=TfWnwA0PNApuz8cZrLf1v5XuPT5yX/dQbzIYGGUxqoU=; b=0GiHjrmYg2WV0p5if+C5ZZL2L1tukKPJ0NTcvg0wEofyMwQHZDr0SP8ABmzOifN3AY 3AqohErsJ3uVlpA6zS0bq9/DJW1Lm8XSPMKFszKd6PO6p6N5I05S9gQaI95clZ43PDGd piZh1dZ92Wps9ACFN3jkEhYNb7qb+WVeTVtRfEveVTEDZx3wQyT6Ox/leqySeeeGPLbo 6k1SB/oFtjgoMd76E4I9dqWnfRD4j9UYsIu9h4qJxzKjC36NZqP4ZEZkT8DuTFHJNSXD 71oJyLyyY73UXIOcwHKTeJ244rb8u/8gqTLpvcclBz6JQn1DQJayGQ+DzNOoerKpjByV Zikw== X-Gm-Message-State: ACgBeo2kMdSIaT4y1ZClvSjhECQyCK4jChbu8lJrPz5l3QiH0t+OIIfh LcJTKzGpYgOR5LZnisKC7oSZSWtofAbcFQff X-Google-Smtp-Source: AA6agR5XggM8ubgA33wZHanXNBeMu54RjXJm93glTwoImkotC9DmyleGdLtv5iRw8sdRrs/t858Hqg== X-Received: by 2002:a63:902:0:b0:434:760f:9c83 with SMTP id 2-20020a630902000000b00434760f9c83mr2949413pgj.608.1662550598418; Wed, 07 Sep 2022 04:36:38 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id 8-20020a17090a000800b001fd77933fb3sm10797230pja.17.2022.09.07.04.36.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:36:37 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [RFC PATCH V2 00/19] Refactor and add RISC-V support in edk2 repo Date: Wed, 7 Sep 2022 17:06:07 +0530 Message-Id: <20220907113626.540065-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit RISC-V ProcessorPkg and PlatformPkg were added in edk2-platforms repo. But the recommendation was they should be added in edk2 repo itself leveraging common packages as much as possible. This series tries to create RISC-V specific modules and libraries under standard packages. The approach taken here is to do this in multiple phases. In the first phase, the proposal adds support in edk2 repo without disturbing the edk2-platforms repo. So, existing platforms will continue to build in same way. Only qemu virt machine which is being supported as part of this series will make use of the refactored modules from edk2 repo. In the second phase, plan is to use newly added edk2 packages as much as possible in edk2-platforms and remove the redundant code from edk2-platforms repo. Generic platforms will NOT have integrated OpenSBI library in EDK2. EDK2 should be booted only in S-mode by a separate M-mode firmware on generic platforms. This doesn't exclude the vendors to have the option of having M-mode functionality in EDK2 itself, but they need to be special platforms and should be using edk2-platforms. The reasons to take this design choice are, 1) The expectation that EDK2 always starts in M-mode would not work in case of virtualization like KVM guests. 2) opensbi as M-mode firmware is one of the implementation of SBI specification. It may be the only one open source implementation as of today. But EDk2 should be able to boot with any M-mode firmware. 3) Integrating opensbi in edk2 is not trivial. opensbi repo is frequently changing and it is not possible to upgrade this in edk2 so frequently. Failing to upgrade, edk2 will be left behind other firmware solutions in terms of functionality. Also, there will be duplicate of efforts both in opensbi and edk2. 4) By making EDK2 as a payload of a previous stage M-mode firmware, the design gets simplified in a great way. There is no need to handle multiple CPUs entering EDK2, no wrapper libraries required etc. 5) This allows to follow the RISC-V S-mode calling convention which passes BootHartId and the DTB to S-Mode. EDk2 can parse the DTB instead of hardcoding many platform specific details in PCD variables. In few places, a separate INF file is created (ex: UefiCpuPkg/SecCore/SecCoreRiscV.inf) since there is not much to leverage the code and may not suit to other architectures. But happy to do which is the correct thing to do. At high level the changes are spread in 3 main modules. 1) UefiCpuPkg - Added new SEC(SecCore) for RISC-V - Refactored and added RISC-V support in DxeCpuExceptionHandlerLib - Refactored and added RISC-V support in CpuDxe - Added PCD variable for RISC-V similar to existing PcdCpuCoreCrystalClockFrequency 2) MdePkg - Added RISC-V register definition headers - Added definition of RISCV_EFI_BOOT_PROTOCOL GUID and header file - BaseLib - enhanced to add interfaces to access the SSCRATCH register - Added ArchTimerLib which can be leveraged by other architectures if needed. - Added RiscVSbiLib specific to RISC-V to make SBI calls to M-mode firmware. - Added ResetSystemLib which can be leveraged by other architectures. - Added PlatformPeiLib which can be leveraged by other architectures. 3)MdeModulePkg - Added PCD variables for RISC-V - Added PlatformPei PEIM which can be leveraged by other architectures. - Added TimerDxe module which can be leveraged by other architectures. RISC-V virt needs following packages from ARM. Current RISC-V virt model DSC file include them directly. But in next phase, we need to below move ArmVirtPkg modules to OvmPkg. Need feedback on ArmPlatformPkg modle below. - ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf - ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf - ArmVirtPkg/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf - ArmVirtPkg/Library/NorFlashQemuLib/NorFlashQemuLib.inf I have not run CI. Only CheckPatch is run and RISC-V build is tested. Once we get consensus on the proposal, we can run additional tests required. These changes are available at https://github.com/vlsunil/edk2/tree/virt_refactor_smode_v2 The chnges are tested on qemu but it needs an additional patch series. https://lists.gnu.org/archive/html/qemu-devel/2022-09/msg00838.html 2) Build EDK2 for RISC-V export WORKSPACE=`pwd` export GCC5_RISCV64_PREFIX=riscv64-linux-gnu- export PACKAGES_PATH=$WORKSPACE/edk2 export EDK_TOOLS_PATH=$WORKSPACE/edk2/BaseTools source edk2/edksetup.sh make -C edk2/BaseTools clean make -C edk2/BaseTools make -C edk2/BaseTools/Source/C source edk2/edksetup.sh BaseTools build -a RISCV64 -p OvmfPkg/RiscVVirt/RiscVVirt.dsc -t GCC5 3)Make the EDK2 image size to match with what qemu flash expects truncate -s 32M Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd 4) Run a) Boot to EFI shell (no -kernel / -initrd option) qemu-system-riscv64 -nographic -drive file=Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 -machine virt -M 2G b) With -kernel, -initrd and -pflash qemu-system-riscv64 -nographic -drive file=Build/RiscVVirt/DEBUG_GCC5/FV/RISCV_VIRT.fd,if=pflash,format=raw,unit=1 -machine virt -M 2G -kernel arch/riscv/boot/Image.gz -initrd rootfs.cpio Changes since V1: - Moved the DSC/FDF files to OvmfPkg - Updated the patches after running SetupGit.py Sunil V L (19): MdePkg/Register: Add register definition header files for RISC-V MdePkg/MdePkg.dec: Add RISCV_EFI_BOOT_PROTOCOL GUID MdePkg/Protocol: Add RiscVBootProtocol.h MdeModulePkg/MdeModulePkg.dec: Add PCD variables for RISC-V UefiCpuPkg.dec: Add PCD variable for RISC-V MdePkg/BaseLib: RISC-V: Add generic CPU related functions MdePkg: Add ArchTimerLib library MdePkg: Add RiscVSbiLib Library for RISC-V UefiCpuPkg: Update Sources in DxeCpuExceptionHandlerLib.inf UefiCpuPkg: Add RISC-V support in DxeCpuExceptionHandlerLib MdePkg/Library: Add ResetSystemLib library UefiCpuPkg/SecCore: Add SEC startup code for RISC-V MdePkg: Add PlatformPeiLib library MdeModulePkg/Universal: Add PlatformPei module for RISC-V UefiCpuPkg/CpuDxe: Refactor to allow other CPU architectures UefiCpuPkg/CpuDxe: Add RISC-V support in CpuDxe module MdeModulePkg/Universal: Add TimerDxe module RISC-V: Add Qemu Virt platform support Maintainers.txt: Add entry for new OvmfPkg/RiscVVirt MdeModulePkg/MdeModulePkg.dec | 13 + MdePkg/MdePkg.dec | 6 + UefiCpuPkg/UefiCpuPkg.dec | 3 + OvmfPkg/RiscVVirt/RiscVVirt.dsc | 713 ++++++++++++++++++ OvmfPkg/RiscVVirt/RiscVVirt.fdf | 379 ++++++++++ MdeModulePkg/Universal/PlatformPei/PlatformPei.inf | 65 ++ MdeModulePkg/Universal/TimerDxe/TimerDxe.inf | 52 ++ MdePkg/Library/ArchTimerLib/ArchTimerLib.inf | 40 + MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf | 40 + MdePkg/Library/ResetSystemLib/ResetSystemLib.inf | 35 + MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf | 27 + UefiCpuPkg/CpuDxe/CpuDxe.inf | 28 +- UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf | 13 +- UefiCpuPkg/SecCore/SecCoreRiscV.inf | 59 ++ MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h | 97 +++ MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h | 174 +++++ MdePkg/Include/Library/BaseLib.h | 10 + MdePkg/Include/Library/PlatformPeiLib.h | 15 + MdePkg/Include/Library/RiscVSbiLib.h | 129 ++++ MdePkg/Include/Protocol/RiscVBootProtocol.h | 35 + MdePkg/Include/Register/RiscV64/RiscVAsm.h | 104 +++ MdePkg/Include/Register/RiscV64/RiscVConst.h | 46 ++ MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 129 ++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 24 + UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 200 +++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h | 112 +++ UefiCpuPkg/SecCore/RiscV64/SecMain.h | 63 ++ MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c | 83 ++ MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c | 179 +++++ MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c | 372 +++++++++ MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c | 293 +++++++ MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c | 299 ++++++++ MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c | 68 ++ MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c | 128 ++++ MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c | 228 ++++++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 337 +++++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c | 136 ++++ UefiCpuPkg/SecCore/RiscV64/SecMain.c | 796 ++++++++++++++++++++ Maintainers.txt | 4 + MdeModulePkg/Universal/TimerDxe/Timer.uni | 15 + MdeModulePkg/Universal/TimerDxe/TimerExtra.uni | 13 + MdePkg/Library/ArchTimerLib/ArchTimerLib.uni | 14 + MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 + OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 49 ++ OvmfPkg/RiscVVirt/VarStore.fdf.inc | 79 ++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S | 105 +++ UefiCpuPkg/SecCore/RiscV64/SecEntry.S | 23 + 48 files changed, 5857 insertions(+), 9 deletions(-) create mode 100644 OvmfPkg/RiscVVirt/RiscVVirt.dsc create mode 100644 OvmfPkg/RiscVVirt/RiscVVirt.fdf create mode 100644 MdeModulePkg/Universal/PlatformPei/PlatformPei.inf create mode 100644 MdeModulePkg/Universal/TimerDxe/TimerDxe.inf create mode 100644 MdePkg/Library/ArchTimerLib/ArchTimerLib.inf create mode 100644 MdePkg/Library/PlatformPeiLib/PlatformPeiLib.inf create mode 100644 MdePkg/Library/ResetSystemLib/ResetSystemLib.inf create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.inf create mode 100644 UefiCpuPkg/SecCore/SecCoreRiscV.inf create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.h create mode 100644 MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.h create mode 100644 MdePkg/Include/Library/PlatformPeiLib.h create mode 100644 MdePkg/Include/Library/RiscVSbiLib.h create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVAsm.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVConst.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecMain.h create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Fv.c create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/MemDetect.c create mode 100644 MdeModulePkg/Universal/PlatformPei/RiscV64/Platform.c create mode 100644 MdeModulePkg/Universal/TimerDxe/RiscV64/Timer.c create mode 100644 MdePkg/Library/ArchTimerLib/RiscV64/CpuTimerLib.c create mode 100644 MdePkg/Library/PlatformPeiLib/RiscV64/PlatformPeiLib.c create mode 100644 MdePkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c create mode 100644 MdePkg/Library/RiscVSbiLib/RiscVSbiLib.c create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecMain.c create mode 100644 MdeModulePkg/Universal/TimerDxe/Timer.uni create mode 100644 MdeModulePkg/Universal/TimerDxe/TimerExtra.uni create mode 100644 MdePkg/Library/ArchTimerLib/ArchTimerLib.uni create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuGen.S create mode 100644 OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc create mode 100644 OvmfPkg/RiscVVirt/VarStore.fdf.inc create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S create mode 100644 UefiCpuPkg/SecCore/RiscV64/SecEntry.S -- 2.25.1