From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f47.google.com (mail-pj1-f47.google.com [209.85.216.47]) by mx.groups.io with SMTP id smtpd.web10.6500.1662550603769316202 for ; Wed, 07 Sep 2022 04:36:43 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Z+FwNoLs; spf=pass (domain: ventanamicro.com, ip: 209.85.216.47, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f47.google.com with SMTP id m10-20020a17090a730a00b001fa986fd8eeso18030044pjk.0 for ; Wed, 07 Sep 2022 04:36:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=GYJ/bc1qz/Y3CXDhVXW2rIeZlK+vIsnhSuTZ7XiGOQc=; b=Z+FwNoLs0PhabOMlWRdIwMdGDd63ACV3fGt8L8faZOeLCnO9D2OJiTvEKLLnkruZyI PdmHOzxD/VpoxCVIefZx5d0w5eq0kYtgTys78wUVP3t2VkpdMmXfJ0Wa9KjNcuZ1O+yz QH+USXS8Zwkwoe2SqJ87HGVPHMsGszy87Ciyhov+QTcg/rC4sR9wwVmJTN+GyAH7lpP0 oiyDZItXREfN6IZ7lxNurMY/EKIY/WHFP9Dv7OBERK/MDlwN8rB9TieSMXiYSUiA5p6L 99RVp8PZ9jgnn80yG9G0Lz6020vKHgCji7YZZJZpS5gTICHTgzjgJmZpqd9qM59ZiDJL oDEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=GYJ/bc1qz/Y3CXDhVXW2rIeZlK+vIsnhSuTZ7XiGOQc=; b=tCzJqoWRaVKrOyf1VR06J1Xqhgct4RP/HLyFVIMRKQjDyci9wbZj2eMvpJ4NsvKgYK u9A/eQ0beHlkyobd03OY33YEm2W8L+WL2IsRgBzoJy7UYz1eS9/Dz5pYalpDJimUzNSf lXkBsBDu4VG951wO8ne3aiAJICbCCl0bG0CvX1y3Uk/rtUhmvo2KSIIaq1N12X6aO8vD MmaG4n7p6QOj/krwQMyEhAvO95e7IK68lWJVSFG1DreaQhw6OKPVB1dv/+CrmaX7z5aD LhJKhxkxMcaRPmsVsiSDUSE58pGiBld0sBGOsjZDHBusknGp+u8wPsBjpVwOd2jtjWQW Rviw== X-Gm-Message-State: ACgBeo3vwHJ6sPH/0YqZUnbqB96IVhaB+whZijObkPoXyFya+3067hzn C4fBOW2RxJAaauWHsgcIsQV99jKMobnCiV/Y X-Google-Smtp-Source: AA6agR5cTQ5sq8LRQN9lhIk8PsWY2gJ7FIaQSJBqBbWlaG+/dVX2Bxcpe++9e5cRgR8CzH6V/5uc3g== X-Received: by 2002:a17:90a:2b0a:b0:1ff:f1cc:b430 with SMTP id x10-20020a17090a2b0a00b001fff1ccb430mr30329236pjc.243.1662550602828; Wed, 07 Sep 2022 04:36:42 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id 8-20020a17090a000800b001fd77933fb3sm10797230pja.17.2022.09.07.04.36.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:36:42 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [RFC PATCH V2 01/19] MdePkg/Register: Add register definition header files for RISC-V Date: Wed, 7 Sep 2022 17:06:08 +0530 Message-Id: <20220907113626.540065-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220907113626.540065-1-sunilvl@ventanamicro.com> References: <20220907113626.540065-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Signed-off-by: Sunil V L --- MdePkg/Include/Register/RiscV64/RiscVAsm.h | 104 ++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVConst.h | 46 +++++++ MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 129 ++++++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 24 ++++ 4 files changed, 303 insertions(+) diff --git a/MdePkg/Include/Register/RiscV64/RiscVAsm.h b/MdePkg/Include/Register/RiscV64/RiscVAsm.h new file mode 100644 index 000000000000..e566061b73e2 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVAsm.h @@ -0,0 +1,104 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_ASM_H__ +#define __RISCV_ASM_H__ + +#include + +#ifdef __ASSEMBLER__ +#define __ASM_STR(x) x +#else +#define __ASM_STR(x) #x +#endif + +#ifndef __ASSEMBLER__ + +#define csr_swap(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrrw %0, " __ASM_STR(csr) ", %1" \ + : "=r"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define csr_read(csr) \ + ({ \ + register unsigned long __v; \ + __asm__ __volatile__("csrr %0, " __ASM_STR(csr) \ + : "=r"(__v) \ + : \ + : "memory"); \ + __v; \ + }) + +#define csr_write(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrw " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define csr_read_set(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrrs %0, " __ASM_STR(csr) ", %1" \ + : "=r"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define csr_set(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrs " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define csr_read_clear(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrrc %0, " __ASM_STR(csr) ", %1" \ + : "=r"(__v) \ + : "rK"(__v) \ + : "memory"); \ + __v; \ + }) + +#define csr_clear(csr, val) \ + ({ \ + unsigned long __v = (unsigned long)(val); \ + __asm__ __volatile__("csrc " __ASM_STR(csr) ", %0" \ + : \ + : "rK"(__v) \ + : "memory"); \ + }) + +#define wfi() \ + do { \ + __asm__ __volatile__("wfi" ::: "memory"); \ + } while (0) + +#define ebreak() \ + do { \ + __asm__ __volatile__("ebreak" ::: "memory"); \ + } while (0) + + +#endif /* !__ASSEMBLER__ */ + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVConst.h b/MdePkg/Include/Register/RiscV64/RiscVConst.h new file mode 100644 index 000000000000..ea7e15119150 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVConst.h @@ -0,0 +1,46 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. All rights reserved.
+ * + * Authors: + * Anup Patel + * This is leveraged from sbi_const.h in opensbi. + */ + +#ifndef __RISCV_CONST_H__ +#define __RISCV_CONST_H__ + +/* + * Some constant macros are used in both assembler and + * C code. Therefore we cannot annotate them always with + * 'UL' and other type specifiers unilaterally. We + * use the following macros to deal with this. + * + * Similarly, _AT() will cast an expression with a type in C, but + * leave it unchanged in asm. + */ + +#ifdef __ASSEMBLER__ +#define _AC(X,Y) X +#define _AT(T,X) X +#else +#define __AC(X,Y) (X##Y) +#define _AC(X,Y) __AC(X,Y) +#define _AT(T,X) ((T)(X)) +#endif + +#define _UL(x) (_AC(x, UL)) +#define _ULL(x) (_AC(x, ULL)) + +#define _BITUL(x) (_UL(1) << (x)) +#define _BITULL(x) (_ULL(1) << (x)) + +#define UL(x) (_UL(x)) +#define ULL(x) (_ULL(x)) + +#define __STR(s) #s +#define STRINGIFY(s) __STR(s) + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h new file mode 100644 index 000000000000..5ad66ee7e7de --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -0,0 +1,129 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * Copyright (c) 2022 Ventana Micro Systems Inc. + * + * Authors: + * Anup Patel + */ + +#ifndef __RISCV_ENCODING_H__ +#define __RISCV_ENCODING_H__ + +#include + +/* clang-format off */ +#define MSTATUS_SIE _UL(0x00000002) +#define MSTATUS_MIE _UL(0x00000008) +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (_UL(1) << MSTATUS_SPIE_SHIFT) +#define MSTATUS_UBE _UL(0x00000040) +#define MSTATUS_MPIE _UL(0x00000080) +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (_UL(1) << MSTATUS_SPP_SHIFT) +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (_UL(3) << MSTATUS_MPP_SHIFT) + +#define SSTATUS_SIE MSTATUS_SIE +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT +#define SSTATUS_SPIE MSTATUS_SPIE +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT +#define SSTATUS_SPP MSTATUS_SPP + +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define MIP_SSIP (_UL(1) << IRQ_S_SOFT) +#define MIP_VSSIP (_UL(1) << IRQ_VS_SOFT) +#define MIP_MSIP (_UL(1) << IRQ_M_SOFT) +#define MIP_STIP (_UL(1) << IRQ_S_TIMER) +#define MIP_VSTIP (_UL(1) << IRQ_VS_TIMER) +#define MIP_MTIP (_UL(1) << IRQ_M_TIMER) +#define MIP_SEIP (_UL(1) << IRQ_S_EXT) +#define MIP_VSEIP (_UL(1) << IRQ_VS_EXT) +#define MIP_MEIP (_UL(1) << IRQ_M_EXT) +#define MIP_SGEIP (_UL(1) << IRQ_S_GEXT) +#define MIP_LCOFIP (_UL(1) << IRQ_PMU_OVF) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U _UL(0) +#define PRV_S _UL(1) +#define PRV_M _UL(3) + +#define SATP64_MODE _ULL(0xF000000000000000) +#define SATP64_ASID _ULL(0x0FFFF00000000000) +#define SATP64_PPN _ULL(0x00000FFFFFFFFFFF) + +#define SATP_MODE_OFF _UL(0) +#define SATP_MODE_SV32 _UL(1) +#define SATP_MODE_SV39 _UL(8) +#define SATP_MODE_SV48 _UL(9) +#define SATP_MODE_SV57 _UL(10) +#define SATP_MODE_SV64 _UL(11) + + +#define SATP_MODE SATP64_MODE + +/* ===== User-level CSRs ===== */ + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 + +/* ===== Supervisor-level CSRs ===== */ + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* ===== Trap/Exception Causes ===== */ + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INST_FAULT 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h new file mode 100644 index 000000000000..e9ccd34039ed --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -0,0 +1,24 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __RISCV_IMPL_H_ +#define __RISCV_IMPL_H_ + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) +#define RISCV_TIMER_COMPARE_BITS 32 + +#endif -- 2.25.1