From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f54.google.com (mail-pj1-f54.google.com [209.85.216.54]) by mx.groups.io with SMTP id smtpd.web09.6627.1662550626589889765 for ; Wed, 07 Sep 2022 04:37:06 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=OQ0n5YS6; spf=pass (domain: ventanamicro.com, ip: 209.85.216.54, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f54.google.com with SMTP id pj10so3812635pjb.2 for ; Wed, 07 Sep 2022 04:37:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=bnB1gU0oGC+nlYK33RMn35urfd6l4WjwzNWsg5leWTA=; b=OQ0n5YS6yTSxY3ewxPRDm5tFg6r8Pbd265GaJl33OBs9Ow9yATF1O6l8jCT1AvHYUE UX7TuR59M4f+Gr5NRBZaz2qutjhKfwklUdcKrktGsQKxrTMnAa14nJvMVhgIKscP6fAN FLI1QMdpNhA+C0dwaB7sl9147Z5Rl3WFcpLR1+zj2eMwNWeoKZNHcHYsHMUJcnLeKaps 1EzJvmwHLtvhe7dpqUa+TaIN2dMCn0luTzVh7oPmvAjyXyRKyEu6PYHbclHfAGzmBrtj zVV1i5tlJEnZWlKcQQVZs8ra4l4tbkPc+zO5icQCAqHKqlf4c4JPJB0rZmkGulHhUpG5 0P2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=bnB1gU0oGC+nlYK33RMn35urfd6l4WjwzNWsg5leWTA=; b=bF+FmmFHXx73SYOBCCLkrde4b8PlkObLucECVldVW6NyE7X8MDy5EZNnvh2OdWCSks DHKQPxX1Nr9IW3UAOnB/O50L5oId2/dY8aAe+60+QJtuH6E2jdkeHNkNAOqaqCdqtCZY 0TqPg949hgGHy1IVFOAP+5xw2fj2ROIdqBiE+SwvwBCVUVgO7qXvgTWWimxgrOjhJrTu zAI5DH6ldIy2xT9aE+8kVRdVNWKKrt4KZAawekbOOAKsoABsngT19vypCFaPlcQu59Xj ZA6UbkZSZ9SsvZQcydo/vAEGBgxa7O4kwu+JMLF5Kl8WNHbRRqmOrEUYP13oclLhRs+x nbmg== X-Gm-Message-State: ACgBeo2Ptw5NwTeEswaHHsHqAJKksywkmAsezdB9pIGSEVZXhrTMPuzq X5/2KN0HwvrnBJPSQuEisYchivQYlGb8TvuG X-Google-Smtp-Source: AA6agR5cUwEL+zVeJqI/XaILtjdpWKKpbAN4bxgowwr8XTxOPl9U9QvvsFbGioLfzFReABCl4Qi2Lg== X-Received: by 2002:a17:90b:17ce:b0:1f4:d068:5722 with SMTP id me14-20020a17090b17ce00b001f4d0685722mr29411072pjb.28.1662550625968; Wed, 07 Sep 2022 04:37:05 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.11.92]) by smtp.gmail.com with ESMTPSA id 8-20020a17090a000800b001fd77933fb3sm10797230pja.17.2022.09.07.04.37.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Sep 2022 04:37:05 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Jian J Wang , Liming Gao , Eric Dong , Ray Ni , Rahul Kumar , Debkumar De , Catharine West , Daniel Schaefer , Abner Chang , Leif Lindholm , Andrew Fish , Ard Biesheuvel , Heinrich Schuchardt , Anup Patel , Sunil V L Subject: [RFC PATCH V2 06/19] MdePkg/BaseLib: RISC-V: Add generic CPU related functions Date: Wed, 7 Sep 2022 17:06:13 +0530 Message-Id: <20220907113626.540065-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220907113626.540065-1-sunilvl@ventanamicro.com> References: <20220907113626.540065-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit EDK2 in S-mode needs to use SSCRATCH register. Implement functions to set/get the SSCRATCH register. Signed-off-by: Sunil V L --- MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Include/Library/BaseLib.h | 10 ++++++ MdePkg/Library/BaseLib/RiscV64/CpuGen.S | 33 ++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 6be5be9428f2..5429329e39b0 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -401,6 +401,7 @@ [Sources.RISCV64] RiscV64/RiscVCpuPause.S | GCC RiscV64/RiscVInterrupt.S | GCC RiscV64/FlushCache.S | GCC + RiscV64/CpuGen.S | GCC [Packages] MdePkg/MdePkg.dec diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h index a6f9a194ef1c..a742de61a442 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -150,6 +150,16 @@ typedef struct { #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 +VOID +RiscVSetSupervisorScratch ( + UINT64 + ); + +UINT64 +RiscVGetSupervisorScratch ( + VOID + ); + #endif // defined (MDE_CPU_RISCV64) // diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuGen.S b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S new file mode 100644 index 000000000000..d11929cf3233 --- /dev/null +++ b/MdePkg/Library/BaseLib/RiscV64/CpuGen.S @@ -0,0 +1,33 @@ +//------------------------------------------------------------------------------ +// +// Generic CPU related functions for RISC-V +// +// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.
+// Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------------ + +#include +#include + +.data +.align 3 +.section .text + +// +// Set Supervisor mode scratch. +// @param a0 : Value set to Supervisor mode scratch +// +ASM_FUNC (RiscVSetSupervisorScratch) + csrrw a1, CSR_SSCRATCH, a0 + ret + +// +// Get Supervisor mode scratch. +// @retval a0 : Value in Supervisor mode scratch +// +ASM_FUNC (RiscVGetSupervisorScratch) + csrr a0, CSR_SSCRATCH + ret -- 2.25.1