From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web10.5518.1662644092567616266 for ; Thu, 08 Sep 2022 06:34:52 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: pierre.gondois@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 813BF23A; Thu, 8 Sep 2022 06:34:58 -0700 (PDT) Received: from pierre123.arm.com (pierre123.nice.arm.com [10.34.100.114]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6EEAB3F7B4; Thu, 8 Sep 2022 06:34:51 -0700 (PDT) From: "PierreGondois" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Sami Mujawar , Thomas Abraham Subject: [PATCH 1/1] Platform/ARM: Bump Dsdt/Ssdt ACPI table revision Date: Thu, 8 Sep 2022 15:34:16 +0200 Message-Id: <20220908133416.734613-1-Pierre.Gondois@arm.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Pierre Gondois >>From ACPI 5.1, s19.5.28 DefinitionBlock (Declare Definition Block): Note: For compatibility with ACPI versions before ACPI 2.0, the bit width of Integer objects is dependent on the ComplianceRevision of the DSDT. If the ComplianceRevision is less than 2, all integers are restricted to 32 bits. Otherwise, full 64-bit integers are used. The version of the DSDT sets the global integer width for all integers, including integers in SSDTs. To be up-to-date with the latest table revision, bump the version of all dsdt/ssdt tables that are relying on an ACPI specification version above 2.0. Signed-off-by: Pierre Gondois --- Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl | 2 +- Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl | 2 +- .../ConfigurationManagerDxe/AslTables/Dsdt.asl | 2 +- .../ConfigurationManagerDxe/AslTables/SsdtJunoUsb.asl | 2 +- .../ConfigurationManagerDxe/AslTables/DsdtFvp.asl | 2 +- .../ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl | 2 +- .../ConfigurationManagerDxe/AslTables/Dsdt.asl | 2 +- .../ConfigurationManagerDxe/AslTables/SsdtPci.asl | 2 +- .../ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl | 2 +- .../ConfigurationManagerDxe/AslTables/Dsdt.asl | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl b/Platfo= rm/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl index e60fc42a3340..9ffc045bfc8a 100644 --- a/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl +++ b/Platform/ARM/JunoPkg/AcpiTables/AcpiSsdtRootPci.asl @@ -57,7 +57,7 @@ // Device 0 for Brid= ge. =20 =20 -DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_ACPI= _ARM_OEM_REVISION) { +DefinitionBlock("SsdtPci.aml", "SSDT", 2, "ARMLTD", "ARM-JUNO", EFI_ACPI= _ARM_OEM_REVISION) { Scope(_SB) { // // PCI Root Complex diff --git a/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl b/Platform/ARM/Juno= Pkg/AcpiTables/Dsdt.asl index 61353213fe6f..0e6b2db4ff5a 100644 --- a/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl +++ b/Platform/ARM/JunoPkg/AcpiTables/Dsdt.asl @@ -8,7 +8,7 @@ =20 #include "ArmPlatform.h" =20 -DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_AC= PI_ARM_OEM_REVISION) { +DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARM-JUNO", EFI_AC= PI_ARM_OEM_REVISION) { Scope(_SB) { // // A57x2-A53x4 Processor declaration diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManag= erDxe/AslTables/Dsdt.asl b/Platform/ARM/JunoPkg/ConfigurationManager/Conf= igurationManagerDxe/AslTables/Dsdt.asl index 2270b517cd12..f16e80b9bc0b 100644 --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/A= slTables/Dsdt.asl +++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/A= slTables/Dsdt.asl @@ -8,7 +8,7 @@ =20 #include "ArmPlatform.h" =20 -DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-JUNO", EFI_AC= PI_ARM_OEM_REVISION) { +DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARM-JUNO", EFI_AC= PI_ARM_OEM_REVISION) { Scope(_SB) { // // A57x2-A53x4 Processor declaration diff --git a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManag= erDxe/AslTables/SsdtJunoUsb.asl b/Platform/ARM/JunoPkg/ConfigurationManag= er/ConfigurationManagerDxe/AslTables/SsdtJunoUsb.asl index 8ff9d150b92a..4aaaedde830b 100644 --- a/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/A= slTables/SsdtJunoUsb.asl +++ b/Platform/ARM/JunoPkg/ConfigurationManager/ConfigurationManagerDxe/A= slTables/SsdtJunoUsb.asl @@ -8,7 +8,7 @@ =20 #include "ArmPlatform.h" =20 -DefinitionBlock("SsdtJunoUSB.aml", "SSDT", 1, "ARMLTD", "ARM-JUNO", EFI_= ACPI_ARM_OEM_REVISION) { +DefinitionBlock("SsdtJunoUSB.aml", "SSDT", 2, "ARMLTD", "ARM-JUNO", EFI_= ACPI_ARM_OEM_REVISION) { Scope(_SB) { // // USB EHCI Host Controller diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManag= erDxe/AslTables/DsdtFvp.asl b/Platform/ARM/Morello/ConfigurationManager/C= onfigurationManagerDxe/AslTables/DsdtFvp.asl index 6ff3d030ba9f..e63c2d197301 100644 --- a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/A= slTables/DsdtFvp.asl +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/A= slTables/DsdtFvp.asl @@ -8,7 +8,7 @@ =20 #include "ConfigurationManager.h" =20 -DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "MORELLO", CFG_MGR_OEM_= REVISION) { +DefinitionBlock("Dsdt.aml", "DSDT", 2, "ARMLTD", "MORELLO", CFG_MGR_OEM_= REVISION) { Scope(_SB) { Device(CP00) { // Cluster 0, Cpu 0 Name(_HID, "ACPI0007") diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManag= erDxe/AslTables/SsdtPciFvp.asl b/Platform/ARM/Morello/ConfigurationManage= r/ConfigurationManagerDxe/AslTables/SsdtPciFvp.asl index bdf2f06aed69..2a73c2c9385f 100644 --- a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/A= slTables/SsdtPciFvp.asl +++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/A= slTables/SsdtPciFvp.asl @@ -30,7 +30,7 @@ =20 #define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) //= Device 0 for Bridge. =20 -DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "MORELLO", +DefinitionBlock("SsdtPci.aml", "SSDT", 2, "ARMLTD", "MORELLO", CFG_MGR_OEM_REVISION) { Scope (_SB) { diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager= Dxe/AslTables/Dsdt.asl b/Platform/ARM/N1Sdp/ConfigurationManager/Configur= ationManagerDxe/AslTables/Dsdt.asl index 818862cd7589..6263ff082a05 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Asl= Tables/Dsdt.asl +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Asl= Tables/Dsdt.asl @@ -59,7 +59,7 @@ #define CS_OUTPUT_PORT(_port, _rport, _rphandle) \ CS_PORT(_port, _rport, _rphandle, CS_LINK_MASTER) =20 -DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "N1Sdp", EFI_ACPI_ARM_O= EM_REVISION) { +DefinitionBlock("Dsdt.aml", "DSDT", 2, "ARMLTD", "N1Sdp", EFI_ACPI_ARM_O= EM_REVISION) { Scope(_SB) { Device(CP00) { // Ares-0: Cluster 0, Cpu 0 Name(_HID, "ACPI0007") diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager= Dxe/AslTables/SsdtPci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/Confi= gurationManagerDxe/AslTables/SsdtPci.asl index 9922673d0d8d..194992b8bb55 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Asl= Tables/SsdtPci.asl +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Asl= Tables/SsdtPci.asl @@ -61,7 +61,7 @@ */ #define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) //= Device 0 for Bridge. =20 -DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp", +DefinitionBlock("SsdtPci.aml", "SSDT", 2, "ARMLTD", "N1Sdp", EFI_ACPI_ARM_OEM_REVISION) { Scope (_SB) { diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManager= Dxe/AslTables/SsdtRemotePci.asl b/Platform/ARM/N1Sdp/ConfigurationManager= /ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl index 4c6e0c762fe0..25489b7ed93d 100644 --- a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Asl= Tables/SsdtRemotePci.asl +++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/Asl= Tables/SsdtRemotePci.asl @@ -61,7 +61,7 @@ */ #define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) //= Device 0 for Bridge. =20 -DefinitionBlock("SsdtRemotePci.aml", "SSDT", 1, "ARMLTD", "N1Sdp", +DefinitionBlock("SsdtRemotePci.aml", "SSDT", 2, "ARMLTD", "N1Sdp", EFI_ACPI_ARM_OEM_REVISION) { Scope (_SB) { diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationM= anagerDxe/AslTables/Dsdt.asl b/Platform/ARM/VExpressPkg/ConfigurationMana= ger/ConfigurationManagerDxe/AslTables/Dsdt.asl index e04003d562dd..3acc0c6bc1b4 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerD= xe/AslTables/Dsdt.asl +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerD= xe/AslTables/Dsdt.asl @@ -9,7 +9,7 @@ =20 **/ =20 -DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-VEXP", 1) { +DefinitionBlock("DsdtTable.aml", "DSDT", 2, "ARMLTD", "ARM-VEXP", 1) { Scope(_SB) { // // Processor --=20 2.25.1