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[46.193.66.249]) by smtp.gmail.com with ESMTPSA id i11-20020adfb64b000000b00228df23bd51sm240537wre.82.2022.09.09.04.15.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 09 Sep 2022 04:15:08 -0700 (PDT) From: =?UTF-8?B?VGjDqW8gSmVobA==?= To: devel@edk2.groups.io Cc: Leif Lindholm , Michael D Kinney , Isaac Oram , Pedro Falcato , Gerd Hoffmann , Stefan Hajnoczi Subject: [[edk2-platforms] Patch V2 1/4] QemuOpenBoardPkg: Add QemuOpenBoardPkg Date: Fri, 9 Sep 2022 13:15:01 +0200 Message-Id: <20220909111504.1661-2-theojehl76@gmail.com> X-Mailer: git-send-email 2.32.1 (Apple Git-133) In-Reply-To: <20220909111504.1661-1-theojehl76@gmail.com> References: <20220909111504.1661-1-theojehl76@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable QemuOpenBoardPkg adds a MinPlatform port to QEMU x86_64. This port brings a starting place for understanding the MinPlatform, and board porting. This patch adds the base for QemuOpenBoardPkg. It also enables MinPlatform stage 1 (debug) functionality which includes serial debug messages. Cc: Leif Lindholm =0D Cc: Michael D Kinney =0D Cc: Isaac Oram =0D Cc: Pedro Falcato =0D Cc: Gerd Hoffmann =0D Cc: Stefan Hajnoczi =0D Signed-off-by: Th=C3=A9o Jehl --- Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec = | 33 ++ Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc = | 55 ++ Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc = | 153 +++++ Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf = | 203 +++++++ Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.inf = | 29 + Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.inf = | 63 ++ Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.inf = | 49 ++ Platform/Qemu/QemuOpenBoardPkg/Library/QemuOpenFwCfgLib/QemuOpenFwCfgLib.i= nf | 23 + Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf = | 59 ++ Platform/Qemu/QemuOpenBoardPkg/Include/Library/QemuOpenFwCfgLib.h = | 105 ++++ Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h = | 59 ++ Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c = | 229 ++++++++ Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c = | 285 ++++++++++ Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.c = | 140 +++++ Platform/Qemu/QemuOpenBoardPkg/Library/QemuOpenFwCfgLib/QemuOpenFwCfgLib.c= | 136 +++++ Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c = | 64 +++ Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c = | 251 ++++++++ Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c = | 70 +++ Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c = | 106 ++++ Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c = | 75 +++ Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc = | 94 +++ Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/SecEntry.nasm = | 117 ++++ Platform/Qemu/QemuOpenBoardPkg/README.md = | 53 ++ 23 files changed, 2451 insertions(+) diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec b/Platform= /Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec new file mode 100644 index 000000000000..109e99439f04 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dec @@ -0,0 +1,33 @@ +## @file QemuOpenBoardPkg.dec=0D +# Declaration file for QemuOpenBoardPkg.=0D +#=0D +# This package supports a simple QEMU port implemented per the MinPlatfor= m=0D +# Arch specification.=0D +#=0D +# Copyright (c) 2022 Th=C3=A9o Jehl=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +# @par Specification Reference:=0D +# -https://tianocore-docs.github.io/edk2-MinimumPlatformSpecification/dr= aft/ 0.7=0D +##=0D +=0D +[Defines]=0D + DEC_SPECIFICATION =3D 0x00010005=0D + PACKAGE_NAME =3D QemuOpenBoardPkg=0D + PACKAGE_GUID =3D 3487DE0A-6770-48A2-9833-FB426A42D7B2= =0D + PACKAGE_VERSION =3D 0.1=0D +=0D +[LibraryClasses]=0D + QemuOpenFwCfgLib|Include/Library/QemuOpenFwCfgLib.h=0D +=0D +[Includes]=0D + Include=0D +=0D +[Guids]=0D + gQemuOpenBoardPkgTokenSpaceGuid =3D { 0x221b20c4, 0x= a3dc, 0x4b8f, { 0xb6, 0x94, 0x03, 0xc7, 0xf4, 0x76, 0x51, 0x2b } }=0D +=0D +[PcdsFixedAtBuild]=0D + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x00000001= =0D + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00000002= =0D + gQemuOpenBoardPkgTokenSpaceGuid.PcdDebugIoPort|0|UINT16|0x00000003=0D + gQemuOpenBoardPkgTokenSpaceGuid.PcdFdVarBlockSize|0|UINT16|0x00000004=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc b/Pl= atform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc new file mode 100644 index 000000000000..114c4e8193b2 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc @@ -0,0 +1,55 @@ +## @file=0D +# Common DSC content to begin Stage 1 enabling=0D +#=0D +# @copyright=0D +# Copyright (C) 2022 Intel Corporation=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Library Class section - list of all Library Classes needed by this Platf= orm.=0D +#=0D +##########################################################################= ######=0D +=0D +[LibraryClasses]=0D + PciSegmentInfoLib | MinPlatformPkg/Pci/Library/PciSegmentInfoLibSi= mple/PciSegmentInfoLibSimple.inf=0D + BoardInitLib | QemuOpenBoardPkg/Library/BoardInitLib/BoardIni= tLib.inf=0D + SetCacheMtrrLib | MinPlatformPkg/Library/SetCacheMtrrLib/SetCach= eMtrrLib.inf=0D + ReportCpuHobLib | MinPlatformPkg/PlatformInit/Library/ReportCpuH= obLib/ReportCpuHobLib.inf=0D + SiliconPolicyInitLib | MinPlatformPkg/PlatformInit/Library/SiliconPol= icyInitLibNull/SiliconPolicyInitLibNull.inf=0D + SiliconPolicyUpdateLib | MinPlatformPkg/PlatformInit/Library/SiliconPol= icyUpdateLibNull/SiliconPolicyUpdateLibNull.inf=0D + ReportFvLib | QemuOpenBoardPkg/Library/PeiReportFvLib/PeiRep= ortFvLib.inf=0D + PciLib | MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf= =0D +=0D +[LibraryClasses.Common.SEC]=0D + TestPointCheckLib | MinPlatformPkg/Test/Library/TestPointCheckLib/= SecTestPointCheckLib.inf=0D + TimerLib | MdePkg/Library/BaseTimerLibNullTemplate/BaseTi= merLibNullTemplate.inf=0D +=0D +[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]=0D + TestPointCheckLib | MinPlatformPkg/Test/Library/TestPointCheckLib/= PeiTestPointCheckLib.inf=0D + TestPointLib | MinPlatformPkg/Test/Library/TestPointLib/PeiTe= stPointLib.inf=0D + TimerLib | MdePkg/Library/BaseTimerLibNullTemplate/BaseTi= merLibNullTemplate.inf=0D +=0D +[Components.$(PEI_ARCH)]=0D + UefiCpuPkg/SecCore/SecCore.inf=0D + MdeModulePkg/Core/Pei/PeiMain.inf=0D + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf=0D + UefiCpuPkg/CpuIoPei/CpuIoPei.inf=0D + MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciC= fg2Pei.inf=0D + MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf=0D + MdeModulePkg/Universal/PCD/Pei/Pcd.inf {=0D + =0D + PcdLib | MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D + }=0D + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouter= Pei.inf=0D + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf=0D + MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf=0D + MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf=0D + MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf= =0D + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf=0D + QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf=0D + !if $(SMM_REQUIRED) =3D=3D TRUE=0D + OvmfPkg/SmmAccess/SmmAccessPei.inf=0D + !endif=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc b/Platform= /Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc new file mode 100644 index 000000000000..e170f5235340 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.dsc @@ -0,0 +1,153 @@ +## @file=0D +# QemuOpenBoardPkg.dsc=0D +#=0D +# Description file for QemuOpenBoardPkg=0D +#=0D +# Copyright (c) 2022 Th=C3=A9o Jehl=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +##=0D +=0D +[Defines]=0D + DSC_SPECIFICATION =3D 0x0001001C=0D + PLATFORM_GUID =3D 94797875-D562-40CF-8D55-ADD623C8D46C=0D + PLATFORM_NAME =3D QemuOpenBoardPkg=0D + PLATFORM_VERSION =3D 0.1=0D + SUPPORTED_ARCHITECTURES =3D IA32 | X64=0D + FLASH_DEFINITION =3D $(PLATFORM_NAME)/$(PLATFORM_NAME).fdf=0D + OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)=0D + BUILD_TARGETS =3D DEBUG | RELEASE | NOOPT=0D + SKUID_IDENTIFIER =3D ALL=0D + SMM_REQUIRED =3D TRUE=0D +=0D +!ifndef $(PEI_ARCH)=0D + !error "PEI_ARCH must be specified to build this feature!"=0D +!endif=0D +!ifndef $(DXE_ARCH)=0D + !error "DXE_ARCH must be specified to build this feature!"=0D +!endif=0D +=0D +[SkuIds]=0D + 0 | DEFAULT=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + QemuOpenBoardPkg/QemuOpenBoardPkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D + OvmfPkg/OvmfPkg.dec=0D +=0D +[PcdsFixedAtBuild]=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootStage | = 1=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel | = 0x802A00C7=0D + gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel | = 0x802A00C7=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask | = 0x17=0D +=0D + # QEMU "memory" is functional even in SEC. For simplicity, we just use = that=0D + # "memory" for the temporary RAM=0D + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamBase | = 0x1000000=0D + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamSize | = 0x010000=0D +=0D + gQemuOpenBoardPkgTokenSpaceGuid.PcdDebugIoPort | = 0x402=0D + gEfiMdePkgTokenSpaceGuid.PcdFSBClock | = 100000000=0D +=0D + # PCIe base address for Q35 machines=0D + # QEMU usable memory below 4G cannot exceed 2.8Gb=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress | = 0xB0000000=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable | = TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange | = FALSE=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase | = 0x00000000 # Will be updated by build=0D +=0D +[PcdsFeatureFlag]=0D + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable | = TRUE=0D + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable | = FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable | = FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress | = TRUE=0D +=0D + !if $(DXE_ARCH) =3D=3D X64=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode | = TRUE=0D + !else=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode | = FALSE=0D + !endif=0D +=0D +=0D + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit | = TRUE=0D + !endif=0D +=0D + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 2=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit | = TRUE=0D + !endif=0D +=0D + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 3=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly | = TRUE=0D + !endif=0D +=0D + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5=0D + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable | = TRUE=0D + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable | = TRUE=0D + !endif=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable | = TRUE=0D + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable | = FALSE=0D +=0D + !if $(SMM_REQUIRED) =3D=3D TRUE=0D + gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire | = FALSE=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport | = FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache | = FALSE=0D + !endif=0D +=0D +[PcdsDynamicDefault]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId | = 0=0D +=0D + # Video setup=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution | = 640=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution | = 480=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion | = 0x0208=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev | = 0x0=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut | = 3=0D +=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber | = 0=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber | = 0=0D +=0D + !if $(SMM_REQUIRED) =3D=3D TRUE=0D + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes | = 8=0D + gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase | = FALSE=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmSyncMode | = 0x01=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout | = 100000=0D + !endif=0D +=0D +# Include Common libraries and then stage specific libraries and component= s=0D +!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc=0D +!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc=0D +!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc=0D +!include QemuOpenBoardPkg/Include/Dsc/Stage1.dsc.inc=0D +=0D +[LibraryClasses.Common]=0D + QemuOpenFwCfgLib | QemuOpenBoardPkg/Library/QemuOpenFwCfgLib/Qemu= OpenFwCfgLib.inf=0D + PlatformHookLib | MdeModulePkg/Library/BasePlatformHookLibNull/B= asePlatformHookLibNull.inf=0D + PlatformSecLib | QemuOpenBoardPkg/Library/PlatformSecLib/Platfo= rmSecLib.inf=0D + DebugLib | MdePkg/Library/BaseDebugLibSerialPort/BaseDebu= gLibSerialPort.inf=0D + PciCf8Lib | MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf= =0D + TimerLib | OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.= inf=0D +=0D +[LibraryClasses.Common.DXE_CORE]=0D + TimerLib | OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.= inf=0D +=0D +[LibraryClasses.Common.DXE_DRIVER, LibraryClasses.Common.DXE_RUNTIME_DRIVE= R, LibraryClasses.Common.DXE_SMM_DRIVER, LibraryClasses.Common.UEFI_DRIVER,= LibraryClasses.Common.UEFI_APPLICATION, LibraryClasses.Common.SMM_CORE]=0D + TimerLib | OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.i= nf=0D + QemuFwCfgLib | OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgDxeLib.i= nf=0D + MemEncryptSevLib | OvmfPkg/Library/BaseMemEncryptSevLib/DxeMemEnc= ryptSevLib.inf=0D + MemEncryptTdxLib | OvmfPkg/Library/BaseMemEncryptTdxLib/BaseMemEn= cryptTdxLibNull.inf=0D + Tcg2PhysicalPresenceLib | OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/Dx= eTcg2PhysicalPresenceLib.inf=0D + ResetSystemLib | OvmfPkg/Library/ResetSystemLib/DxeResetSystemL= ib.inf=0D +=0D +[LibraryClasses.Common.SEC]=0D + DebugLib | OvmfPkg/Library/PlatformDebugLibIoPort/Platfor= mRomDebugLibIoPort.inf=0D +=0D +[Components.$(DXE_ARCH)]=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf b/Platform= /Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf new file mode 100644 index 000000000000..ccd18d559fa9 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/QemuOpenBoardPkg.fdf @@ -0,0 +1,203 @@ +## @file=0D +# QemuOpenBoardPkg.fdf=0D +#=0D +# Copyright (c) 2022 Th=C3=A9o Jehl=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D 0xFF800= 000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D 0x80000= 0=0D +=0D +!include QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc=0D +=0D +[FD.QemuOpenBoardPkgVars]=0D + BaseAddress =3D 0xFF800000=0D + Size =3D 0x80000=0D + ErasePolarity =3D 1=0D + BlockSize =3D 0x800|gQemuOpenBoardPkgTokenSpaceGuid.PcdFdVarBlockSiz= e=0D + NumBlocks =3D 0x100=0D +=0D + #=0D + # Do not modify this block=0D + # These three areas are tightly coupled and should be modified with utmo= st care.=0D + # The total size must match the size in the EFI_FIRMWARE_VOLUME_HEADER i= n NvStorage512K.fdf.=0D + # The NvStorageVariableSize must also match the VARIABLE_STORE_HEADER si= ze in NvStorage512K.fdf.=0D + # The EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER in CommonNvStorageFtwWorki= ng.fdf doesn't have size info.=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset | gEfiMdeM= odulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D + !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset | gEfiMd= eModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D + !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset | gEfiMdeM= odulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as B= ase/Size to be written=0D +=0D +[FD.QemuOpenBoardPkg]=0D + BaseAddress =3D 0xFF880000=0D + Size =3D 0x780000=0D + ErasePolarity =3D 1=0D + BlockSize =3D 0x1000=0D + NumBlocks =3D 0x780=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset | gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvAdvancedSize=0D + FV =3D FvAdvanced=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset | gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvSecuritySize=0D + FV =3D FvSecurity=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset | gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvOsBootSize=0D + FV =3D FvOsBoot=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset | gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvUefiBootSize=0D + FV =3D FvUefiBoot=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset | gMinPlatformPkgToken= SpaceGuid.PcdFlashFvBspSize=0D + FV =3D FvBsp=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset | gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPostMemorySize=0D + FV =3D FvPostMemory=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset | gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspSSize=0D + FV =3D FvFspS=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset | gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspMSize=0D + FV =3D FvFspM=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset | gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvFspTSize=0D + FV =3D FvFspT=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset | gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize=0D + FV =3D FvBspPreMemory=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset | gMinPlatformPk= gTokenSpaceGuid.PcdFlashFvPreMemorySize=0D + FV =3D FvPreMemory=0D +=0D +###########################=0D +#=0D +# Stage 1 Firmware Volumes=0D +#=0D +###########################=0D +=0D +[FV.FvPreMemory]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D BD479C6B-2EFF-401F-A7F1-566347B41D07=0D +=0D + FILE FV_IMAGE =3D 618FBA00-2231-41F6-9931-25A89DF501D3 {=0D + SECTION FV_IMAGE =3D FvSecurityPreMemory=0D + }=0D +=0D + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf=0D +=0D + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRo= uterPei.inf=0D + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf=0D +=0D + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.i= nf=0D + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf=0D +=0D + INF UefiCpuPkg/SecCore/SecCore.inf=0D +=0D +[FV.FvSecurityPreMemory]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D F626B0FB-D759-44A8-B131-42408BB3533D=0D +=0D +[FV.FvBspPreMemory]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D 5CF9C072-385F-44FC-B21B-002074251C08=0D +=0D + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.in= f=0D + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf=0D + INF QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf=0D +=0D + FILE FV_IMAGE =3D 90B948EA-FF73-4689-B90A-A54F86C1FC01 {=0D + SECTION FV_IMAGE =3D FvAdvancedPreMemory=0D + }=0D +=0D +[FV.FvAdvancedPreMemory]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D 43528CE0-812B-4074-B77E-C49E7A2F4FE1=0D +=0D +[FV.FvFspT]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D 958CAF39-0B6C-40F1-B190-EC91C536CFF9=0D +=0D +[FV.FvFspM]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D 03982cf7-246a-4356-b6ba-436a2251595c=0D +=0D + INF MdeModulePkg/Core/Pei/PeiMain.inf=0D +=0D + FILE FV_IMAGE =3D 83B39C64-BFB9-42EC-A7A3-527854A5C4C3 {=0D + SECTION FV_IMAGE =3D FvPreMemorySilicon=0D + }=0D +=0D +[FV.FvPreMemorySilicon]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D F0205C0E-0AD1-499C-A5F9-96BAF98248A0=0D +=0D + INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.= inf=0D +=0D + !if $(SMM_REQUIRED) =3D=3D TRUE=0D + INF OvmfPkg/SmmAccess/SmmAccessPei.inf=0D + !endif=0D +=0D +[FV.FvFspS]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D C6786443-AFCA-471B-A8FC-E8C330708F99=0D +=0D +[FV.FvPostMemorySilicon]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D EF76DFDC-2B7D-423D-BFE4-8FD4BB22E770=0D +=0D +###########################=0D +#=0D +# Stage 2 Firmware Volumes=0D +#=0D +###########################=0D +[FV.FvPostMemory]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D 5A1D6978-BABE-42F9-A629-F7B3B6A1E1BD=0D +=0D +[FV.FvBsp]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D FCA0BC4A-994D-4EF9-BD56-A8C45872C2A8=0D +=0D +###########################=0D +#=0D +# Stage 3 Firmware Volumes=0D +#=0D +###########################=0D +[FV.FvUefiBoot]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D D0C15ADB-FE38-4331-841C-0E96C1B0FBFA=0D +=0D +###########################=0D +#=0D +# Stage 4 Firmware Volumes=0D +#=0D +###########################=0D +[FV.FvOsBoot]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D AE8F0EA0-1614-422D-ABC1-C518596F1678=0D +=0D +###########################=0D +#=0D +# Stage 5 Firmware Volumes=0D +#=0D +###########################=0D +[FV.FvSecurity]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D 1AE6AB90-9431-425B-9A92-ED2708A4E982=0D +=0D +###########################=0D +#=0D +# Stage 6 Firmware Volumes=0D +#=0D +###########################=0D +[FV.FvAdvanced]=0D + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf=0D + FvNameGuid =3D 936D6D65-CB6C-4B87-A51C-70D56511CB55=0D +=0D +###########################=0D +#=0D +# File Construction Rules=0D +#=0D +###########################=0D +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitL= ib.inf b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.i= nf new file mode 100644 index 000000000000..8f75d1277070 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.inf @@ -0,0 +1,29 @@ +## @file=0D +# QemuOpenBoardPkg BoardInitLib instance=0D +#=0D +# Copyright (c) 2019, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D BoardInitLib=0D + FILE_GUID =3D 70EE7BD9-08FF-4D0E-AA7B-4320844F939A= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D BoardInitLib=0D +=0D +[Sources]=0D + BoardInitLib.c=0D +=0D +[Packages]=0D + QemuOpenBoardPkg/QemuOpenBoardPkg.dec=0D + MdePkg/MdePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + OvmfPkg/OvmfPkg.dec=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + PcdLib=0D + IoLib=0D + PciCf8Lib=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiRepor= tFvLib.inf b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiRepor= tFvLib.inf new file mode 100644 index 000000000000..d416f1c64061 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.= inf @@ -0,0 +1,63 @@ +### @file=0D +# Component information file for the Report Firmware Volume (FV) library.= =0D +#=0D +# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +###=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PeiReportFvLib=0D + FILE_GUID =3D 44328FA5-E4DD-4A15-ABDF-C6584AC363D9= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D PEIM=0D + LIBRARY_CLASS =3D ReportFvLib=0D +=0D +[LibraryClasses]=0D + BaseMemoryLib=0D + DebugLib=0D + HobLib=0D + PeiServicesLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + QemuOpenBoardPkg/QemuOpenBoardPkg.dec=0D +=0D +[Sources]=0D + PeiReportFvLib.c=0D +=0D +[Pcd]=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootStage ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase ## CONSU= MES=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset ## CONSU= MES=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Platform= SecLib.inf b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Platform= SecLib.inf new file mode 100644 index 000000000000..a4c793af05cd --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.= inf @@ -0,0 +1,49 @@ +## @file=0D +# PlatformSecLib for QEMU OpenBoardPkg=0D +#=0D +# Copyright (c) 2022 Th=C3=A9o Jehl=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PlatformSecLib=0D + FILE_GUID =3D 37b1bddc-5a53-4f2a-af7d-b78d5e80dcbd= =0D + MODULE_TYPE =3D SEC=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PlatformSecLib=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32=0D +#=0D +=0D +[Sources.IA32]=0D + Ia32/SecEntry.nasm=0D +=0D +[Sources]=0D + PlatformSecLib.c=0D +=0D +[LibraryClasses]=0D + DebugLib=0D + BaseLib=0D + BaseMemoryLib=0D + PciLib=0D + PcdLib=0D + HobLib=0D + MtrrLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D + QemuOpenBoardPkg/QemuOpenBoardPkg.dec=0D + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D +=0D +[Ppis]=0D + gTopOfTemporaryRamPpiGuid=0D +=0D +[Pcd]=0D + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamBase=0D + gQemuOpenBoardPkgTokenSpaceGuid.PcdTemporaryRamSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/QemuOpenFwCfgLib/QemuOp= enFwCfgLib.inf b/Platform/Qemu/QemuOpenBoardPkg/Library/QemuOpenFwCfgLib/Qe= muOpenFwCfgLib.inf new file mode 100644 index 000000000000..3709d538321a --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/QemuOpenFwCfgLib/QemuOpenFwCfg= Lib.inf @@ -0,0 +1,23 @@ +## @file=0D +# QemuOpenFwCfgLib.inf=0D +#=0D +# Simple implementation of the QemuFwCfgLib that reads data from the QEMU= =0D +# FW_CFG device=0D +#=0D +# Copyright (c) 2022 Th=C3=A9o Jehl=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D QemuFwCfgLib=0D + FILE_GUID =3D 70EE7BD9-08FF-4D0E-AA7B-4320844F939A= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D QemuOpenFwCfgLib=0D +=0D +[Sources]=0D + QemuOpenFwCfgLib.c=0D +=0D +[LibraryClasses]=0D + IoLib=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei= .inf b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf new file mode 100644 index 000000000000..76e354e6e6b1 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInitPei.inf @@ -0,0 +1,59 @@ +## @file=0D +# PlatformInitPei=0D +#=0D +# Simple PEIM for QEMU PIIX4/Q35 Memory, SMP and PCI/PCI Express initiali= zation=0D +#=0D +# Copyright (c) 2022 Th=C3=A9o Jehl=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PlatformInitPei=0D + FILE_GUID =3D 82d851fe-3106-4175-8b6c-87fda1f2d0ac= =0D + MODULE_TYPE =3D PEIM=0D + VERSION_STRING =3D 1.0=0D + ENTRY_POINT =3D PlatformInit=0D +=0D +[Packages]=0D + OvmfPkg/OvmfPkg.dec=0D + MdePkg/MdePkg.dec=0D + QemuOpenBoardPkg/QemuOpenBoardPkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D +=0D +[Sources]=0D + PlatformInit.h=0D + PlatformInit.c=0D + Memory.c=0D + Pcie.c=0D + Pci.c=0D + Cpu.c=0D +=0D +[LibraryClasses]=0D + PeimEntryPoint=0D + QemuOpenFwCfgLib=0D + HobLib=0D + PcdLib=0D + PciLib=0D +=0D +[Guids]=0D + gUefiOvmfPkgPlatformInfoGuid=0D +=0D +[Pcd]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base=0D + gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes=0D +=0D +[FeaturePcd]=0D + gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire=0D +=0D +[Depex]=0D + TRUE=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Library/QemuOpenFwCfgLi= b.h b/Platform/Qemu/QemuOpenBoardPkg/Include/Library/QemuOpenFwCfgLib.h new file mode 100644 index 000000000000..2d4690b660f5 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Library/QemuOpenFwCfgLib.h @@ -0,0 +1,105 @@ +/** @file QemuOpenFwCfgLib.h=0D + QemuOpenFwCfgLib Headers=0D +=0D + Implements a minimal library to interact with Qemu FW CFG device=0D +=0D + QEMU FW CFG device allow the OS to retrieve files passed by QEMU or the = user.=0D + Files can vary from E820 entries to ACPI tables.=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +=0D +#ifndef QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_=0D +#define QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_=0D +=0D +#include =0D +#include =0D +=0D +// QEMU fw_cfg registers=0D +#define FW_CFG_PORT_SEL 0x510=0D +#define FW_CFG_PORT_DATA 0x511=0D +#define FW_CFG_PORT_DMA 0x514=0D +=0D +// QEMU Selectors=0D +#define FW_CFG_SIGNATURE 0x0000=0D +#define FW_CFG_ID 0x0001=0D +#define FW_CFG_FILE_DIR 0x0019=0D +=0D +#define FW_CFG_QEMU_SIGNATURE SIGNATURE_32('Q', 'E', 'M', 'U')=0D +=0D +typedef struct {=0D + UINT32 Size;=0D + UINT16 Select;=0D + UINT16 Reserved;=0D + CHAR8 Name[56];=0D +} QEMU_FW_CFG_FILE;=0D +=0D +/**=0D + Checks for Qemu fw_cfg device by reading "QEMU" using the signature sele= ctor=0D +=0D + @return EFI_SUCCESS - The fw_cfg device is present=0D + @return EFI_UNSUPPORTED - The device is absent=0D + */=0D +EFI_STATUS=0D +EFIAPI=0D +QemuFwCfgIsPresent (=0D + VOID=0D + );=0D +=0D +/**=0D + Sets the selector register to the specified value=0D +=0D + @param[in] Selector=0D +=0D + @return EFI_SUCCESS=0D + @return EFI_UNSUPPORTED=0D + */=0D +EFI_STATUS=0D +EFIAPI=0D +QemuFwCfgSelectItem (=0D + IN UINT16 Selector=0D + );=0D +=0D +/**=0D + Reads 8 bits from the data register=0D +=0D + @return UINT8=0D + */=0D +UINT8=0D +EFIAPI=0D +QemuFwCfgRead8 (=0D + VOID=0D + );=0D +=0D +/**=0D + Reads N bytes from the data register=0D +=0D + @param Size=0D + @param Buffer=0D + */=0D +VOID=0D +EFIAPI=0D +QemuFwCfgReadBytes (=0D + IN UINTN Size,=0D + OUT VOID *Buffer=0D + );=0D +=0D +/**=0D + Finds a file in fw_cfg by its name=0D +=0D + @param[in] String Pointer to an ASCII string to match in the database=0D + @param[out] FWConfigFile Buffer for the config file=0D +=0D + @return EFI_STATUS - Entry was found, FWConfigFile is populated=0D + @return EFI_ERROR - Entry was not found=0D + */=0D +EFI_STATUS=0D +EFIAPI=0D +QemuFwCfgFindFile (=0D + IN CHAR8 *String,=0D + OUT QEMU_FW_CFG_FILE *FWConfigFile=0D + );=0D +=0D +#endif // QEMU_OPEN_BOARD_PKG_QEMU_FW_CFG_LIB_H_=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h = b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h new file mode 100644 index 000000000000..7f84e5d9724b --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.h @@ -0,0 +1,59 @@ +/** @file PlatformInit.h=0D + Headers for PlatformInitPei PEIM=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_=0D +#define QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_=0D +=0D +#include =0D +#include =0D +=0D +#define PIIX4_PCI_IO_BASE 0xC000=0D +#define PIIX4_PCI_IO_SIZE 0x4000=0D +=0D +#define Q35_PCI_IO_BASE 0x6000=0D +#define Q35_PCI_IO_SIZE 0xA000=0D +=0D +#define PCI_MMIO_TOP_ADDRESS 0xFC000000=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PlatformInit (=0D + IN EFI_PEI_FILE_HANDLE FileHandle,=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + );=0D +=0D +UINT32=0D +EFIAPI=0D +GetMemoryBelow4Gb (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +InstallMemory (=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +InitializePcie (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +InitializePciPIIX4 (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +MaxCpuInit (=0D + VOID=0D + );=0D +=0D +#endif //QEMU_OPEN_BOARD_PKG_PLATFORM_INIT_H_=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitL= ib.c b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c new file mode 100644 index 000000000000..17b0b703fe59 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/BoardInitLib/BoardInitLib.c @@ -0,0 +1,229 @@ +/** @file=0D + Board initialization library=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define QEMU_IO_DEBUG_MAGIC 0xE9=0D +=0D +/**=0D + This board service detects the board type.=0D +=0D + @retval EFI_SUCCESS The board was detected successfully.=0D + @retval EFI_NOT_FOUND The board could not be detected.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardDetect (=0D + VOID=0D + )=0D +{=0D + UINT16 DeviceID, VendorID;=0D +=0D + DEBUG ((DEBUG_INFO, "BoardDetect()\n"));=0D +=0D + //Retrieve chipset device ID and vendor ID=0D + DeviceID =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_O= FFSET));=0D + VendorID =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, PCI_VENDOR_ID_O= FFSET));=0D +=0D + //=0D + // Qemu can emulate 2 chipsets:=0D + // Intel 440FX with PIIX4 southbridge=0D + // Intel Q35 memory host controller with ICH9 southbridge=0D + //=0D +=0D + switch (DeviceID) {=0D + case INTEL_82441_DEVICE_ID:=0D + DEBUG ((DEBUG_INFO, "Intel 440FX/PIIX4 platform detected!\n"));=0D + return EFI_SUCCESS;=0D +=0D + case INTEL_Q35_MCH_DEVICE_ID:=0D + DEBUG ((DEBUG_INFO, "Intel Q35 MCH/ICH9 platform detected!\n"));=0D + return EFI_SUCCESS;=0D +=0D + default:=0D + DEBUG ((DEBUG_ERROR, "Unable to detect board (Device id %u Vendor ID= %u)\n", DeviceID, VendorID));=0D + return EFI_NOT_FOUND;=0D + }=0D +}=0D +=0D +/**=0D + This board service initializes board-specific debug devices.=0D +=0D + @retval EFI_SUCCESS Board-specific debug initialization was successful= .=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardDebugInit (=0D + VOID=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_BOOT_MODE=0D +EFIAPI=0D +BoardBootModeDetect (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardBootModeDetect()\n"));=0D + return BOOT_WITH_FULL_CONFIGURATION;=0D +}=0D +=0D +/**=0D + A hook for board-specific initialization prior to memory initialization.= =0D +=0D + @retval EFI_SUCCESS The board initialization was successful.=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitBeforeMemoryInit (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardInitBeforeMemoryInit()\n"));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + A hook for board-specific initialization after memory initialization.=0D +=0D + @retval EFI_SUCCESS The board initialization was successful.=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitAfterMemoryInit (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardInitAfterMemoryInit()\n"));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + A hook for board-specific initialization prior to disabling temporary RA= M.=0D +=0D + @retval EFI_SUCCESS The board initialization was successful.=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitBeforeTempRamExit (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardInitBeforeTempRamExit()\n"));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + A hook for board-specific initialization after disabling temporary RAM.= =0D +=0D + @retval EFI_SUCCESS The board initialization was successful.=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitAfterTempRamExit (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardInitAfterTempRamExit()\n"));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + A hook for board-specific initialization prior to silicon initialization= .=0D +=0D + @retval EFI_SUCCESS The board initialization was successful.=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitBeforeSiliconInit (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardInitBeforeSiliconInit()\n"));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + A hook for board-specific initialization after silicon initialization.=0D +=0D + @retval EFI_SUCCESS The board initialization was successful.=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitAfterSiliconInit (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardInitAfterSiliconInit()\n"));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + A hook for board-specific initialization after PCI enumeration.=0D +=0D + @retval EFI_SUCCESS The board initialization was successful.=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitAfterPciEnumeration (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardInitAfterPciEnumeration()\n"));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + A hook for board-specific functionality for the ReadyToBoot event.=0D +=0D + @retval EFI_SUCCESS The board initialization was successful.=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitReadyToBoot (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardInitReadyToBoot()\n"));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + A hook for board-specific functionality for the ExitBootServices event.= =0D +=0D + @retval EFI_SUCCESS The board initialization was successful.=0D + @retval EFI_NOT_READY The board has not been detected yet.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BoardInitEndOfFirmware (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "BoardInitEndOfFirmware()\n"));=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiRepor= tFvLib.c b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportF= vLib.c new file mode 100644 index 000000000000..809e69ce4381 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.c @@ -0,0 +1,285 @@ +/** @file PeiReportFvLib.c=0D + Source code file for Report Firmware Volume (FV) library=0D +=0D + Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +// Use a FV pointer PCD to get a pointer to the FileSystemGuid in the FV h= eader=0D +#define PCD_TO_FV_HEADER_FILE_SYSTEM_GUID(Pcd) (&((EFI_FIRMWARE_VOLUME_H= EADER *)(UINTN) PcdGet32 (Pcd))->FileSystemGuid)=0D +=0D +/**=0D + Reports FVs necessary for MinPlarform pre-memory initialization=0D + */=0D +VOID=0D +ReportPreMemFv (=0D + VOID=0D + )=0D +{=0D + UINTN Index =3D 0;=0D + EFI_PEI_PPI_DESCRIPTOR *Descriptor =3D NULL;=0D + EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *Ppi =3D NULL;=0D + EFI_STATUS Status =3D EFI_SUCCESS;=0D + EFI_FIRMWARE_VOLUME_HEADER *FvHeader =3D NULL;=0D + EFI_BOOT_MODE BootMode =3D BOOT_WITH_FULL_CONFIG= URATION;=0D +=0D + Status =3D PeiServicesGetBootMode (&BootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + DEBUG_CODE (=0D + for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) {=0D + Status =3D PeiServicesLocatePpi (&gEfiPeiFirmwareVolumeInfo2PpiGuid,= Index, &Descriptor, (VOID**) &Ppi);=0D + if (!EFI_ERROR (Status)) {=0D + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi->FvInfo;=0D + DEBUG ((DEBUG_INFO, "Found FV at 0x%x, size 0x%x\n", FvHeader, FvH= eader->FvLength));=0D + }=0D + }=0D + );=0D +=0D + //=0D + // FvBspPreMemory and FvPreMemory are required for all stages.=0D + //=0D +=0D + DEBUG ((DEBUG_INFO, "Install FlashFvBspPreMemory - 0x%x, 0x%x\n", PcdGet= 32 (PcdFlashFvBspPreMemoryBase), PcdGet32 (PcdFlashFvBspPreMemorySize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFlas= hFvBspPreMemoryBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvBspPreM= emoryBase),=0D + PcdGet32 (PcdFlashFvBspPreMemorySize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D +=0D + DEBUG ((DEBUG_INFO, "Install FlashFvPreMemory - 0x%x, 0x%x\n", PcdGet32 = (PcdFlashFvPreMemoryBase), PcdGet32 (PcdFlashFvPreMemorySize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFlas= hFvPreMemoryBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvPreMemo= ryBase),=0D + PcdGet32 (PcdFlashFvPreMemorySize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D +=0D + //=0D + // In API mode, do not publish FSP FV.=0D + //=0D + if (!PcdGetBool (PcdFspWrapperBootMode)) {=0D + //=0D + // FvFspT may be required for all stages=0D + //=0D + DEBUG ((DEBUG_INFO, "Install FlashFvFspT - 0x%x, 0x%x\n", PcdGet32 (Pc= dFlashFvFspTBase), PcdGet32 (PcdFlashFvFspTSize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFl= ashFvFspTBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvFspTB= ase),=0D + PcdGet32 (PcdFlashFvFspTSize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D +=0D + //=0D + // FvFspM required for stage 2 and above=0D + //=0D + if (PcdGet8 (PcdBootStage) >=3D 2) {=0D + DEBUG ((DEBUG_INFO, "Install FlashFvFspM - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvFspMBase), PcdGet32 (PcdFlashFvFspMSize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (Pcd= FlashFvFspMBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvFsp= MBase),=0D + PcdGet32 (PcdFlashFvFspMSize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D + }=0D + }=0D +=0D + //=0D + // FvAdvanced not needed until stage 6=0D + //=0D + if (PcdGet8 (PcdBootStage) >=3D 6) {=0D + DEBUG ((DEBUG_INFO, "Install FlashFvAdvancedPreMemory - 0x%x, 0x%x\n",= PcdGet32 (PcdFlashFvAdvancedPreMemoryBase), PcdGet32 (PcdFlashFvAdvancedPr= eMemorySize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFl= ashFvAdvancedPreMemoryBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvAdvan= cedPreMemoryBase),=0D + PcdGet32 (PcdFlashFvAdvancedPreMemorySiz= e),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D + }=0D +}=0D +/**=0D + Reports FVs for MinPlarform post-memory initialization=0D + This function also publish FV HOBs to ensure DXE phase is aware of those= FVs=0D + */=0D +VOID=0D +ReportPostMemFv (=0D + VOID=0D + )=0D +{=0D + UINTN Index =3D 0;=0D + EFI_PEI_PPI_DESCRIPTOR *Descriptor =3D NULL;=0D + EFI_PEI_FIRMWARE_VOLUME_INFO2_PPI *Ppi =3D NULL;=0D + EFI_STATUS Status =3D EFI_SUCCESS;=0D + EFI_FIRMWARE_VOLUME_HEADER *FvHeader =3D NULL;=0D +=0D + DEBUG_CODE (=0D + for (Index =3D 0; Status =3D=3D EFI_SUCCESS; Index++) {=0D + Status =3D PeiServicesLocatePpi (&gEfiPeiFirmwareVolumeInfo2PpiGuid,= Index, &Descriptor, (VOID**) &Ppi);=0D + if (!EFI_ERROR (Status)) {=0D + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER*) Ppi->FvInfo;=0D + DEBUG ((DEBUG_INFO, "Found FV at 0x%x, size 0x%x\n", FvHeader, FvH= eader->FvLength));=0D + }=0D + }=0D + );=0D +=0D + //=0D + // FvFspS, FvPostMemory, and FvBsp may be required for completing stage = 2=0D + //=0D + if (PcdGet8 (PcdBootStage) >=3D 2) {=0D + //=0D + // In API mode, do not publish FSP FV.=0D + //=0D + if (!PcdGetBool (PcdFspWrapperBootMode)) {=0D + DEBUG ((DEBUG_INFO, "Install FlashFvFspS - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvFspSBase), PcdGet32 (PcdFlashFvFspSSize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (Pcd= FlashFvFspSBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvFsp= SBase),=0D + PcdGet32 (PcdFlashFvFspSSize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "Install FlashFvPostMemory - 0x%x, 0x%x\n", PcdGet= 32 (PcdFlashFvPostMemoryBase), PcdGet32 (PcdFlashFvPostMemorySize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFl= ashFvPostMemoryBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvPostM= emoryBase),=0D + PcdGet32 (PcdFlashFvPostMemorySize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D +=0D + DEBUG ((DEBUG_INFO, "%Build FlashFvPostMemory FV Hob at %Lx \n", (EFI_= PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvPostMemoryBase)));=0D +=0D + BuildFvHob (=0D + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvPostMemoryBase),= =0D + PcdGet32 (PcdFlashFvPostMemorySize)=0D + );=0D +=0D + DEBUG ((DEBUG_INFO, "Install FlashFvBsp - 0x%x, 0x%x\n", PcdGet32 (Pcd= FlashFvBspBase), PcdGet32 (PcdFlashFvBspSize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFl= ashFvBspBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvBspBa= se),=0D + PcdGet32 (PcdFlashFvBspSize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D + }=0D +=0D + //=0D + // FvUefiBoot required for completing stage 3=0D + //=0D + if (PcdGet8 (PcdBootStage) >=3D 3) {=0D + DEBUG ((DEBUG_INFO, "Install FlashFvUefiBoot - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvUefiBootBase), PcdGet32 (PcdFlashFvUefiBootSize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFl= ashFvUefiBootBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvUefiB= ootBase),=0D + PcdGet32 (PcdFlashFvUefiBootSize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D +=0D + DEBUG ((DEBUG_INFO, "%Build FlashFvUefiBoot FV Hob at %Lx \n", (EFI_PH= YSICAL_ADDRESS)PcdGet32 (PcdFlashFvUefiBootBase)));=0D +=0D + BuildFvHob (=0D + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvUefiBootBase),=0D + PcdGet32 (PcdFlashFvUefiBootSize)=0D + );=0D + }=0D +=0D + //=0D + // FvOsBoot required for completing stage 4=0D + //=0D + if (PcdGet8 (PcdBootStage) >=3D 4) {=0D + DEBUG ((DEBUG_INFO, "Install FlashFvOsBoot - 0x%x, 0x%x\n", PcdGet32 (= PcdFlashFvOsBootBase), PcdGet32 (PcdFlashFvOsBootSize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFl= ashFvOsBootBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvOsBoo= tBase),=0D + PcdGet32 (PcdFlashFvOsBootSize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D +=0D + DEBUG ((DEBUG_INFO, "%Build FlashFvOsBoot FV Hob at %Lx \n", (EFI_PHYS= ICAL_ADDRESS)PcdGet32 (PcdFlashFvUefiBootBase)));=0D +=0D + BuildFvHob (=0D + (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdFlashFvOsBootBase),=0D + PcdGet32 (PcdFlashFvOsBootSize)=0D + );=0D + }=0D +=0D + //=0D + // FvSecurity required for completing stage 5=0D + //=0D + if (PcdGet8 (PcdBootStage) >=3D 5) {=0D + DEBUG ((DEBUG_INFO, "Install FlashFvSecurity - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvSecurityBase), PcdGet32 (PcdFlashFvSecuritySize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFl= ashFvSecurityBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvSecur= ityBase),=0D + PcdGet32 (PcdFlashFvSecuritySize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D + }=0D +=0D + //=0D + // FvAdvanced required for completing stage 6=0D + //=0D + if (PcdGet8 (PcdBootStage) >=3D 6) {=0D + DEBUG ((DEBUG_INFO, "Install FlashFvAdvanced - 0x%x, 0x%x\n", PcdGet32= (PcdFlashFvAdvancedBase), PcdGet32 (PcdFlashFvAdvancedSize)));=0D + PeiServicesInstallFvInfo2Ppi (=0D + PCD_TO_FV_HEADER_FILE_SYSTEM_GUID (PcdFl= ashFvAdvancedBase),=0D + (VOID *)(UINTN)PcdGet32 (PcdFlashFvAdvan= cedBase),=0D + PcdGet32 (PcdFlashFvAdvancedSize),=0D + NULL,=0D + NULL,=0D + 0=0D + );=0D + }=0D +=0D + //=0D + // Report resource related HOB for flash FV to reserve space in GCD and = memory map=0D + //=0D +=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_MAPPED_IO,=0D + (EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),=0D + (UINTN)PcdGet32 (PcdFlashAreaBaseAddress),=0D + (UINTN)PcdGet32 (PcdFlashAreaSize)=0D + );=0D +=0D + BuildMemoryAllocationHob (=0D + (UINTN)PcdGet32 (PcdFlashAreaBaseAddress),=0D + (UINTN)PcdGet32 (PcdFlashAreaSize),=0D + EfiMemoryMappedIO=0D + );=0D +}=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Platform= SecLib.c b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSe= cLib.c new file mode 100644 index 000000000000..ff632494c4a3 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/PlatformSecLib.c @@ -0,0 +1,140 @@ +/** @file=0D + PlatformSecLib library functions=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +EFI_PEI_CORE_FV_LOCATION_PPI gEfiPeiCoreFvLocationPpi =3D {=0D + (VOID *)FixedPcdGet32 (PcdFlashFvFspMBase)=0D +};=0D +=0D +STATIC EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D {=0D + //=0D + // This must be the second PPI in the list because it will be patched in= SecPlatformMain ();=0D + //=0D + {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,=0D + &gTopOfTemporaryRamPpiGuid,=0D + NULL=0D + }=0D +};=0D +=0D +EFI_PEI_PPI_DESCRIPTOR gEfiPeiCoreFvLocationDescriptor =3D {=0D + EFI_PEI_PPI_DESCRIPTOR_PPI,=0D + &gEfiPeiCoreFvLocationPpiGuid,=0D + &gEfiPeiCoreFvLocationPpi=0D +};=0D +=0D +EFI_PEI_PPI_DESCRIPTOR *=0D +EFIAPI=0D +SecPlatformMain (=0D + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData=0D + )=0D +{=0D + // Use half of available heap size for PpiList=0D + EFI_PEI_PPI_DESCRIPTOR *PpiList;=0D +=0D + PpiList =3D (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + (UINTN)Se= cCoreData->PeiTemporaryRamSize / 2);=0D +=0D + CopyMem (PpiList, &gEfiPeiCoreFvLocationDescriptor, sizeof (EFI_PEI_PPI_= DESCRIPTOR));=0D +=0D + CopyMem (&PpiList[1], &mPeiSecPlatformPpi, sizeof (EFI_PEI_PPI_DESCRIPTO= R));=0D +=0D + // Patch the top of RAM PPI=0D + PpiList[1].Ppi =3D (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCo= reData->TemporaryRamSize);=0D + DEBUG ((DEBUG_INFO, "SecPlatformMain(): Top of memory %p\n", PpiList[1].= Ppi));=0D +=0D + return PpiList;=0D +}=0D +=0D +/**=0D + This interface conveys state information out of the Security (SEC) phase= into PEI.=0D +=0D + @param PeiServices Pointer to the PEI Services Table.=0D + @param StructureSize Pointer to the variable describing siz= e of the input buffer.=0D + @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORM= ATION_RECORD.=0D +=0D + @retval EFI_SUCCESS The data was successfully returned.=0D + @retval EFI_BUFFER_TOO_SMALL The buffer was too small.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SecPlatformInformation (=0D + IN CONST EFI_PEI_SERVICES **PeiServices,=0D + IN OUT UINT64 *StructureSize,=0D + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord=0D + )=0D +{=0D + UINT32 TopOfTemporaryRam;=0D + VOID *TopOfRamPpi;=0D + EFI_STATUS Status;=0D + UINT32 Count;=0D + UINT32 *BistStart;=0D + UINT32 Length;=0D +=0D + Status =3D (*PeiServices)->LocatePpi (PeiServices, &gTopOfTemporaryRamPp= iGuid, 0, NULL, &TopOfRamPpi);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + TopOfTemporaryRam =3D (UINT32)TopOfRamPpi;=0D +=0D + DEBUG ((DEBUG_INFO, "SecPlatformInformation: Top of memory is %p\n", Top= OfRamPpi));=0D +=0D + Count =3D *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32));=0D + Length =3D Count * sizeof (UINT32);=0D +=0D + BistStart =3D (UINT32 *)(TopOfTemporaryRam - sizeof (UINT32) - Length);= =0D +=0D + DEBUG ((DEBUG_INFO, "SecPlatformInformation: Found %u processors with BI= STs starting at %p\n", Count, BistStart));=0D +=0D + if (*StructureSize < Length) {=0D + *StructureSize =3D Length;=0D + return EFI_BUFFER_TOO_SMALL;=0D + }=0D +=0D + CopyMem (PlatformInformationRecord, BistStart, Length);=0D + *StructureSize =3D Length;=0D +=0D + // Mask the PIC to avoid any interruption down the line=0D + IoWrite8 (0x21, 0xff);=0D + IoWrite8 (0xA1, 0xff);=0D +=0D + DEBUG ((DEBUG_INFO, "Initialize APIC Timer \n"));=0D + InitializeApicTimer (0, MAX_UINT32, TRUE, 5);=0D +=0D + DEBUG ((DEBUG_INFO, "Disable APIC Timer interrupt\n"));=0D + DisableApicTimerInterrupt ();=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This interface disables temporary memory in SEC Phase.=0D +**/=0D +VOID=0D +EFIAPI=0D +SecPlatformDisableTemporaryMemory (=0D + VOID=0D + )=0D +{=0D + return;=0D +}=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/QemuOpenFwCfgLib/QemuOp= enFwCfgLib.c b/Platform/Qemu/QemuOpenBoardPkg/Library/QemuOpenFwCfgLib/Qemu= OpenFwCfgLib.c new file mode 100644 index 000000000000..ec3ca9d5b644 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/QemuOpenFwCfgLib/QemuOpenFwCfg= Lib.c @@ -0,0 +1,136 @@ +/** @file QemuOpenFwCfgLib.c=0D + QemuOpenFwCfgLib library=0D +=0D + Implements a minimal library to interact with Qemu FW CFG device=0D +=0D + QEMU FW CFG device allow the OS to retrieve files passed by QEMU or the = user.=0D + Files can vary from E820 entries to ACPI tables.=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Reads 8 bits from the data register=0D +=0D + @retval UINT8=0D +**/=0D +UINT8=0D +EFIAPI=0D +QemuFwCfgRead8 (=0D + VOID=0D + )=0D +{=0D + return IoRead8 (FW_CFG_PORT_DATA);=0D +}=0D +=0D +/**=0D + Sets the selector register to the specified value=0D +=0D + @param Selector=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_UNSUPPORTED=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +QemuFwCfgSelectItem (=0D + IN UINT16 Selector=0D + )=0D +{=0D + UINT16 WritenSelector;=0D +=0D + WritenSelector =3D IoWrite16 (FW_CFG_PORT_SEL, Selector);=0D +=0D + if (WritenSelector !=3D Selector) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Reads N bytes from the data register=0D +=0D + @param Size=0D + @param Buffer=0D +**/=0D +VOID=0D +EFIAPI=0D +QemuFwCfgReadBytes (=0D + IN UINTN Size,=0D + OUT VOID *Buffer=0D + )=0D +{=0D + IoReadFifo8 (FW_CFG_PORT_DATA, Size, Buffer);=0D +}=0D +=0D +/**=0D + Checks for Qemu fw_cfg device by reading "QEMU" using the signature sele= ctor=0D +=0D + @retval EFI_SUCCESS - The fw_cfg device is present=0D + @retval EFI_UNSUPPORTED - The device is absent=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +QemuFwCfgIsPresent (=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT32 Control;=0D +=0D + Status =3D QemuFwCfgSelectItem (FW_CFG_SIGNATURE);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + QemuFwCfgReadBytes (4, &Control);=0D + if (Control !=3D FW_CFG_QEMU_SIGNATURE) {=0D + ASSERT (Control =3D=3D FW_CFG_QEMU_SIGNATURE);=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Finds a file in fw_cfg by its name=0D +=0D + @param String Pointer to an ASCII string to match in the database=0D + @param FWConfigFile Buffer for the config file=0D + @retval EFI_STATUS - Entry was found, FWConfigFile is populated=0D + @retval EFI_ERROR - Entry was not found=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +QemuFwCfgFindFile (=0D + IN CHAR8 *String,=0D + OUT QEMU_FW_CFG_FILE *FWConfigFile=0D + )=0D +{=0D + QEMU_FW_CFG_FILE FirmwareConfigFile;=0D + UINT32 FilesCount;=0D + UINT32 Idx;=0D +=0D + QemuFwCfgSelectItem (FW_CFG_FILE_DIR);=0D + QemuFwCfgReadBytes (sizeof (UINT32), &FilesCount);=0D +=0D + FilesCount =3D SwapBytes32 (FilesCount);=0D +=0D + for (Idx =3D 0; Idx < FilesCount; Idx++) {=0D + QemuFwCfgReadBytes (sizeof (QEMU_FW_CFG_FILE), &FirmwareConfigFile);=0D + if (AsciiStrCmp ((CHAR8 *)&(FirmwareConfigFile.Name), String) =3D=3D 0= ) {=0D + FirmwareConfigFile.Select =3D SwapBytes16 (FirmwareConfigFile.Select= );=0D + FirmwareConfigFile.Size =3D SwapBytes32 (FirmwareConfigFile.Size);= =0D + CopyMem (FWConfigFile, &FirmwareConfigFile, sizeof (QEMU_FW_CFG_FILE= ));=0D + return EFI_SUCCESS;=0D + }=0D + }=0D +=0D + return EFI_UNSUPPORTED;=0D +}=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c b/Platfor= m/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c new file mode 100644 index 000000000000..991f982781a6 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Cpu.c @@ -0,0 +1,64 @@ +/** @file Cpu.c=0D + CPU Count initialization=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "PlatformInit.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Probe Qemu FW CFG device for current CPU count and report to MpInitLib=0D +=0D + @return EFI_SUCCESS Detection was successful=0D + @retval EFI_UNSUPPORTED Qemu FW CFG device is not present=0D + */=0D +EFI_STATUS=0D +EFIAPI=0D +MaxCpuInit (=0D + VOID=0D + )=0D +{=0D + UINT16 BootCpuCount;=0D + EFI_STATUS Status;=0D +=0D + Status =3D QemuFwCfgIsPresent ();=0D +=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "QemuFwCfg not present, unable to detect CPU coun= t \n"));=0D + ASSERT_EFI_ERROR (Status);=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + //=0D + // Probe Qemu FW CFG device for CPU count=0D + //=0D +=0D + Status =3D QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);=0D +=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + QemuFwCfgReadBytes (sizeof (BootCpuCount), &BootCpuCount);=0D +=0D + //=0D + // Report count to MpInitLib=0D + //=0D +=0D + PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount);=0D +=0D + PcdSet32S (PcdCpuMaxLogicalProcessorNumber, 64);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c b/Plat= form/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c new file mode 100644 index 000000000000..ec1d326f7266 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Memory.c @@ -0,0 +1,251 @@ +/** @file Memory.c=0D + Memory probing and installation=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Return the memory size below 4GB.=0D +=0D + @return UINT32=0D +**/=0D +UINT32=0D +EFIAPI=0D +GetMemoryBelow4Gb (=0D + VOID=0D + )=0D +{=0D + EFI_E820_ENTRY64 E820Entry;=0D + QEMU_FW_CFG_FILE FwCfgFile;=0D + UINT32 Processed;=0D + UINT64 Size;=0D + EFI_STATUS Status;=0D +=0D + Status =3D QemuFwCfgIsPresent ();=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgFile);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + Size =3D 0;=0D + QemuFwCfgSelectItem (FwCfgFile.Select);=0D + for (Processed =3D 0; Processed < FwCfgFile.Size / sizeof (EFI_E820_ENTR= Y); Processed++) {=0D + QemuFwCfgReadBytes (sizeof (EFI_E820_ENTRY), &E820Entry);=0D + if (E820Entry.Type !=3D EfiAcpiAddressRangeMemory) {=0D + continue;=0D + }=0D +=0D + if (E820Entry.BaseAddr + E820Entry.Length < SIZE_4GB) {=0D + Size +=3D E820Entry.Length;=0D + } else {=0D + return Size;=0D + }=0D + }=0D +=0D + return Size;=0D +}=0D +=0D +/**=0D + Reserve an MMIO region=0D +=0D + @param Start=0D + @param Length=0D +**/=0D +STATIC=0D +VOID=0D +ReserveMmioRegion (=0D + EFI_PHYSICAL_ADDRESS Start,=0D + UINT64 Length=0D + )=0D +{=0D + EFI_RESOURCE_TYPE ResourceType;=0D + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;=0D +=0D + ResourceAttributes =3D EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATT= RIBUTE_UNCACHEABLE | EFI_RESOURCE_ATTRIBUTE_TESTED;=0D + ResourceType =3D EFI_RESOURCE_MEMORY_MAPPED_IO;=0D +=0D + BuildResourceDescriptorHob (=0D + ResourceType,=0D + ResourceAttributes,=0D + Start,=0D + Length=0D + );=0D +}=0D +=0D +/**=0D + Install EFI memory by probing Qemu FW CFG devices for valid E820 entries= =0D + It also reserve space for MMIO regions such as VGA, BIOS and APIC=0D +=0D + @param PeiServices=0D + @retval EFI_SUCCESS Memory initialization succeded=0D + @retval EFI_UNSUPPORTED Installation failed (etc/e820 file was not found= )=0D + @retval EFI_NOT_FOUND Qemu FW CFG device is not present=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InstallMemory (=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + )=0D +{=0D + EFI_STATUS Status;=0D + CONST EFI_PEI_SERVICES **PeiServicesTable;=0D + EFI_E820_ENTRY64 E820Entry;=0D + EFI_E820_ENTRY64 LargestE820Entry;=0D + QEMU_FW_CFG_FILE FwCfgFile;=0D + UINT32 Processed;=0D + BOOLEAN ValidMemory;=0D + EFI_RESOURCE_TYPE ResourceType;=0D + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;=0D + UINT32 MemoryBelow4G;=0D + UINT32 RequiredBySmm;=0D +=0D + Status =3D QemuFwCfgIsPresent ();=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_INFO, "QEMU fw_cfg device is not present\n"));=0D + return EFI_NOT_FOUND;=0D + } else {=0D + DEBUG ((DEBUG_INFO, "QEMU fw_cfg device is present\n"));=0D + }=0D +=0D + Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgFile);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "etc/e820 was not found \n"));=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + MemoryBelow4G =3D GetMemoryBelow4Gb ();=0D +=0D + LargestE820Entry.Length =3D 0;=0D + QemuFwCfgSelectItem (FwCfgFile.Select);=0D + for (Processed =3D 0; Processed < FwCfgFile.Size / sizeof (EFI_E820_ENTR= Y); Processed++) {=0D + QemuFwCfgReadBytes (sizeof (EFI_E820_ENTRY), &E820Entry);=0D +=0D + ValidMemory =3D E820Entry.Type =3D=3D EfiAcpiAddressRangeMemory= ;=0D + ResourceType =3D EFI_RESOURCE_MEMORY_RESERVED;=0D + ResourceAttributes =3D EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_A= TTRIBUTE_UNCACHEABLE | EFI_RESOURCE_ATTRIBUTE_TESTED;=0D +=0D + if (ValidMemory) {=0D + if (FeaturePcdGet (PcdSmmSmramRequire) && (E820Entry.BaseAddr + E820= Entry.Length =3D=3D MemoryBelow4G)) {=0D + RequiredBySmm =3D PcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB;=0D + if (E820Entry.Length < RequiredBySmm) {=0D + DEBUG ((=0D + DEBUG_ERROR,=0D + "Error: There's not enough memory below TOLUD for SMM (%lx < %= x)\n",=0D + E820Entry.Length,=0D + RequiredBySmm=0D + ));=0D + }=0D +=0D + E820Entry.Length -=3D RequiredBySmm;=0D + DEBUG ((=0D + DEBUG_INFO,=0D + "SMM is enabled! Stealing [%lx, %lx](%u MiB) for SMRAM...\n",=0D + E820Entry.BaseAddr + E820Entry.Length,=0D + E820Entry.BaseAddr + E820Entry.Length + RequiredBySmm - 1,=0D + PcdGet16 (PcdQ35TsegMbytes)=0D + ));=0D + }=0D +=0D + ResourceType =3D EFI_RESOURCE_SYSTEM_MEMORY;=0D + ResourceAttributes =3D EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE = |=0D + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED;=0D +=0D + //=0D + // Lets handle the lower 1MB in a special way=0D + //=0D +=0D + if (E820Entry.BaseAddr =3D=3D 0) {=0D + //=0D + // 0 - 0xa0000 is system memory, everything above that up to 1MB i= s not=0D + // Note that we check if we actually have 1MB=0D + //=0D +=0D + BuildResourceDescriptorHob (=0D + ResourceType,=0D + ResourceAttributes,=0D + 0,=0D + MIN (0xa0000, E820Entry.Length)=0D + );=0D +=0D + E820Entry.BaseAddr +=3D BASE_1MB;=0D + E820Entry.Length -=3D MIN (BASE_1MB, E820Entry.Length);=0D + }=0D +=0D + //=0D + // Note that we can only check if this is the largest entry after re= serving everything we have to reserve=0D + //=0D +=0D + if ((E820Entry.Length > LargestE820Entry.Length) && (E820Entry.BaseA= ddr + E820Entry.Length <=3D SIZE_4GB)) {=0D + CopyMem (&LargestE820Entry, &E820Entry, sizeof (EFI_E820_ENTRY64))= ;=0D + DEBUG ((=0D + DEBUG_INFO,=0D + "New largest entry for PEI: BaseAddress %lx, Size %lx\n",=0D + LargestE820Entry.BaseAddr,=0D + LargestE820Entry.Length=0D + ));=0D + }=0D + }=0D +=0D + BuildResourceDescriptorHob (=0D + ResourceType,=0D + ResourceAttributes,=0D + E820Entry.BaseAddr,=0D + E820Entry.Length=0D + );=0D +=0D + DEBUG ((=0D + DEBUG_INFO,=0D + "Processed E820 entry [%lx, %lx] with type %x\n",=0D + E820Entry.BaseAddr,=0D + E820Entry.BaseAddr + E820Entry.Length - 1,=0D + E820Entry.Type=0D + ));=0D + }=0D +=0D + ASSERT (LargestE820Entry.Length !=3D 0);=0D + DEBUG ((=0D + DEBUG_INFO,=0D + "Largest memory chunk found: [%lx, %lx]\n",=0D + LargestE820Entry.BaseAddr,=0D + LargestE820Entry.BaseAddr + LargestE820Entry.Length - 1=0D + ));=0D +=0D + PeiServicesTable =3D GetPeiServicesTablePointer ();=0D +=0D + Status =3D (*PeiServices)->InstallPeiMemory (PeiServicesTable, LargestE8= 20Entry.BaseAddr, LargestE820Entry.Length);=0D +=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Reserve architectural PC MMIO regions=0D + // VGA space + BIOS shadow mapping=0D + //=0D +=0D + ReserveMmioRegion (0xa0000, 0x100000 - 0xa0000);=0D +=0D + //=0D + // IO APIC and LAPIC space=0D + //=0D +=0D + ReserveMmioRegion (0xfec00000, 0xff000000 - 0xfec00000);=0D + return Status;=0D +}=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c b/Platfor= m/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c new file mode 100644 index 000000000000..684b4426cc55 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pci.c @@ -0,0 +1,70 @@ +/** @file Pci.c=0D + PCI Initialization for PIIX4 QEMU=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "PlatformInit.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Initialize PCI support for QEMU PIIX4 machine=0D +=0D + It also publishes PCI MMIO and IO ranges PCDs for OVMF PciHostBridgeLib= =0D +=0D + @retval EFI_SUCCESS Initialization was a success=0D + @retval EFI_UNSUPPORTED Initialization failed (Memory below 4Gb probing = failed)=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializePciPIIX4 (=0D + VOID=0D + )=0D +{=0D + UINTN PciIoBase;=0D + UINTN PciIoSize;=0D + UINTN PciMmio32Base;=0D + UINTN PciMmio32Size;=0D +=0D + //=0D + // Setup PCI IO ranges for 440FX/PIIX4 platform=0D + //=0D + PciIoBase =3D PIIX4_PCI_IO_BASE;=0D + PciIoSize =3D PIIX4_PCI_IO_SIZE;=0D +=0D + PcdSet64S (PcdPciIoBase, PciIoBase);=0D + PcdSet64S (PcdPciIoSize, PciIoSize);=0D +=0D + //=0D + // QEMU only allow a maximum of 2.8Gb of real memory below 4G=0D + // PCI MMIO range below 4Gb starts at the end of real memory below 4G=0D + //=0D + PciMmio32Base =3D (UINTN) GetMemoryBelow4Gb ();=0D +=0D + if (PciMmio32Base =3D=3D 0) {=0D + DEBUG ((DEBUG_ERROR, "Unable to detect memory below 4Gb\n"));=0D + ASSERT (PciMmio32Base !=3D 0);=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + DEBUG ((DEBUG_ERROR, "Memory below 4Gb: %x \n", PciMmio32Base));=0D +=0D + //=0D + // Maximum size being PCI_MMIO_TOP_ADDRESS - TopOfLowMem to avoid overla= pping with IO-APIC and other hardware mmio ranges=0D + //=0D + PciMmio32Size =3D PCI_MMIO_TOP_ADDRESS - PciMmio32Base;=0D +=0D + PcdSet64S (PcdPciMmio32Base, PciMmio32Base);=0D + PcdSet64S (PcdPciMmio32Size, PciMmio32Size);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c b/Platfo= rm/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c new file mode 100644 index 000000000000..637f25955f24 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/Pcie.c @@ -0,0 +1,106 @@ +/** @file Pcie.c=0D + PCI Express initialization for QEMU Q35=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "PlatformInit.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Initialize PCI Express support for QEMU Q35 system=0D + It also publishes PCI MMIO and IO ranges PCDs for OVMF PciHostBridgeLib= =0D + @retval EFI_SUCCESS Initialization was successful=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +InitializePcie (=0D + VOID=0D + )=0D +{=0D + UINTN PciBase;=0D + UINTN PciSize;=0D + UINTN PciIoBase;=0D + UINTN PciIoSize;=0D +=0D + union {=0D + UINT64 Uint64;=0D + UINT32 Uint32[2];=0D + } PciExBarBase;=0D +=0D + PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress);=0D +=0D + //=0D + // Build a reserved memory space for PCIE MMIO=0D + //=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_RESERVED,=0D + EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |=0D + EFI_RESOURCE_ATTRIBUTE_TESTED,=0D + PciExBarBase.Uint64,=0D + SIZE_256MB=0D + );=0D +=0D + BuildMemoryAllocationHob (=0D + PciExBarBase.Uint64,=0D + SIZE_256MB,=0D + EfiReservedMemoryType=0D + );=0D +=0D + //=0D + // Clear lower 32 bits of register=0D + //=0D + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);=0D +=0D + //=0D + // Program PCIE MMIO Base address in MCH PCIEXBAR register=0D + //=0D + PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[= 1]);=0D +=0D + //=0D + // Enable 256Mb MMIO space=0D + //=0D + PciWrite32 (=0D + DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),=0D + PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN=0D + );=0D +=0D + //=0D + // Disable PCI/PCIe MMIO above 4Gb=0D + //=0D + PcdSet64S (PcdPciMmio64Size, 0);=0D +=0D + //=0D + // Set Pci MMIO space below 4GB=0D + //=0D + PciBase =3D (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + SIZE_256MB);= =0D + PciSize =3D PCI_MMIO_TOP_ADDRESS - PciBase;=0D +=0D + PcdSet64S (PcdPciMmio32Base, PciBase);=0D + PcdSet64S (PcdPciMmio32Size, PciSize);=0D +=0D + //=0D + // Set Pci IO port range=0D + //=0D + PciIoBase =3D Q35_PCI_IO_BASE;=0D + PciIoSize =3D Q35_PCI_IO_SIZE;=0D +=0D + PcdSet64S (PcdPciIoBase, PciIoBase);=0D + PcdSet64S (PcdPciIoSize, PciIoSize);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c = b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c new file mode 100644 index 000000000000..7e67cad83df6 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/PlatformInitPei/PlatformInit.c @@ -0,0 +1,75 @@ +/** @file PlarformInit.c=0D + Platform initialization PEIM for QEMU=0D +=0D + Copyright (c) 2022 Th=C3=A9o Jehl All rights reserved.=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "PlatformInit.h"=0D +#include =0D +#include =0D +#include "Library/DebugLib.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PlatformInit (=0D + IN EFI_PEI_FILE_HANDLE FileHandle,=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT16 DeviceId;=0D + EFI_HOB_PLATFORM_INFO *EfiPlatformInfo;=0D +=0D + //=0D + // Install permanent memory=0D + //=0D + Status =3D InstallMemory (PeiServices);=0D +=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "Memory installation failed\n"));=0D + return Status;=0D + } else {=0D + DEBUG ((DEBUG_INFO, "Memory installation success\n"));=0D + }=0D +=0D + //=0D + // Report CPU core count to MPInitLib=0D + //=0D + MaxCpuInit ();=0D +=0D + EfiPlatformInfo =3D AllocateZeroPool (sizeof (EFI_HOB_PLATFORM_INFO));=0D + if (EfiPlatformInfo =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "Failed to allocate pool for EFI_HOB_PLATFORM_INF= O\n"));=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + //=0D + // Report gUefiOvmfPkgPlatformInfo HOB with only the necessary data for = OVMF=0D + //=0D + DeviceId =3D PciCf8Read16 (PCI_CF8_LIB_ADDRESS (0, 0, 0, PCI_DEVICE_ID_O= FFSET));=0D + DEBUG ((DEBUG_INFO, "Building gUefiOvmfPkgPlatformInfoGuid with Host bri= dge dev ID %x \n", DeviceId));=0D + (*EfiPlatformInfo).HostBridgeDevId =3D DeviceId;=0D +=0D + BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, EfiPlatformInfo, sizeof= (EFI_HOB_PLATFORM_INFO));=0D +=0D + PcdSet16S (PcdOvmfHostBridgePciDevId, DeviceId);=0D +=0D + //=0D + // Initialize PCI or PCIe based on current emulated system=0D + //=0D + if (DeviceId =3D=3D INTEL_Q35_MCH_DEVICE_ID) {=0D + DEBUG ((DEBUG_INFO, "Q35: Initialize PCIe\n"));=0D + return InitializePcie ();=0D + } else {=0D + DEBUG ((DEBUG_INFO, "PIIX4: Initialize PCI\n"));=0D + return InitializePciPIIX4 ();=0D + }=0D +}=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc b/= Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc new file mode 100644 index 000000000000..ad1847f81883 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Include/Fdf/FlashMap.fdf.inc @@ -0,0 +1,94 @@ +## @file=0D +# Flashmap and variable definitions for QemuOpenBoardPkg FVs and FD=0D +#=0D +# @copyright=0D +# Copyright (C) 2022 Th=C3=A9o Jehl=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +##=0D +=0D +#=0D +# These three items are tightly coupled.=0D +# The spare area size must be >=3D the first two areas.=0D +# The total size must match the size in the EFI_FIRMWARE_VOLUME_HEADER.=0D +# The NvStorageVariableSize must also match the VARIABLE_STORE_HEADER size= .=0D +# The EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER doesn't have size info.=0D +#=0D +# There isn't really a benefit to a larger spare area unless the FLASH dev= ice=0D +# block size is larger than the size specified.=0D +#=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0x= 0003C000=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D 0x= 00004000=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D gE= fiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModuleP= kgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D +=0D +#=0D +# Early FV=0D +#=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00081000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize =3D 0x= 00040000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00010000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 00040000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00020000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 00080000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize =3D 0x= 00020000=0D +=0D +#=0D +# Later FV=0D +#=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 00400000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x= 00100000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x= 00080000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashAreaSize - gEfiMdeModulePkgTokenSpaceGu= id.PcdFlashNvStorageVariableSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashN= vStorageFtwWorkingSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFt= wSpareSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize - gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSp= aceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPre= MemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPla= tformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvSecuritySize=0D +=0D +#=0D +# Calculate Offsets Once (Do not modify)=0D +# This layout is specified by the EDK II Minimum Platform Archicture speci= fication.=0D +# Each offset is the prior region's offset plus the prior region's size.=0D +#=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x= 00000000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00000000=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvAdvancedSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvSecuritySize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvOsBootSize=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvUefiBootSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvBspSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvPostMemorySize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspSSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspMSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspTSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize=0D +=0D +#=0D +# Calculate base addresses=0D +# QemuOpenBoardPkgVars FD=0D +#=0D +=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =3D gE= fiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase =3D gE= fiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D +=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase =3D = gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeM= odulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D +=0D +#=0D +# QemuOpenBoardPkg FD=0D +#=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +gEfiMdeModulePkgTokenSpa= ceGuid.PcdFlashNvStorageFtwSpareSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvAdvancedSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvSecuritySize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvOsBootSize=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvUefiBootSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvBspSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvPostMemorySize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspSSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspMSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspTSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase =3D gM= inPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/Sec= Entry.nasm b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/Sec= Entry.nasm new file mode 100644 index 000000000000..599acea5d713 --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/Library/PlatformSecLib/Ia32/SecEntry.n= asm @@ -0,0 +1,117 @@ +;-------------------------------------------------------------------------= -----=0D +; @file SecEntry=0D +; Sec entry implementation=0D +;=0D +; Copyright (c) 2022 Th=C3=A9o Jehl=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;=0D +;-------------------------------------------------------------------------= -----=0D +=0D +CODE_SEG equ CodeSegDescriptor - GDT_START=0D +DATA_SEG equ DataSegDescriptor - GDT_START=0D +=0D +extern ASM_PFX(SecStartup)=0D +=0D +extern ASM_PFX(PcdGet32 (PcdTemporaryRamBase))=0D +extern ASM_PFX(PcdGet32 (PcdTemporaryRamSize))=0D +=0D +SECTION .text=0D +=0D +BITS 16=0D +align 4=0D +global ASM_PFX(_ModuleEntryPoint)=0D +ASM_PFX(_ModuleEntryPoint):=0D + cli=0D + ; Save the BIST in mm0=0D + movd mm0, eax=0D + mov esi, GDT_Descriptor=0D + db 66h=0D + lgdt [cs:si]=0D +=0D + mov eax, cr0=0D + or eax, 1=0D + mov cr0, eax=0D +=0D + mov ax, DATA_SEG=0D + mov ds, ax=0D + mov es, ax=0D + mov fs, ax=0D + mov gs, ax=0D + mov ss, ax=0D +=0D + mov esi, ProtectedModeEntryLinearAddress=0D +=0D + jmp dword far [cs:si]=0D +=0D +BITS 32=0D +align 4=0D +ProtectedModeEntry:=0D + PROTECTED_MODE equ $=0D +=0D + mov ecx, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamBase))]=0D + mov edx, DWORD [ASM_PFX(PcdGet32 (PcdTemporaryRamSize))]=0D +=0D + ; Initialize the stack at the end of base + size=0D + mov esp, ecx=0D + add esp, edx=0D +=0D + ; Push 1 CPU, will be probed later with Qemu FW CFG device=0D + push 1=0D + ; For now, we push the BIST once=0D + movd eax, mm0=0D + push eax=0D + ; Code in PlatformSecLib will look up this information we've just pushed= =0D + ; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D TOP OF MEMORY =3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0D + ; Count of BISTs=0D + ; BISTs[1..n]=0D + ; =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D REST OF MEMORY = =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0D + ; Each BIST is always a DWORD in size=0D +=0D + mov edi, 0xFFFFFFFC ;BFV=0D +=0D + push DWORD [edi] ;Passes BFV=0D +=0D + push ecx ;Passes RAM size=0D +=0D + push edx ;Passes RAM base=0D +=0D + call ASM_PFX(SecStartup)=0D +=0D +align 8=0D +NULL_SEGMENT equ $ - GDT_START=0D +GDT_START:=0D +=0D +NullSegDescriptor:=0D + dd 0x0=0D + dd 0x0=0D +=0D + CODE_SEL equ $ - GDT_START=0D +=0D +CodeSegDescriptor:=0D + dw 0xFFFF=0D + dw 0x0=0D + db 0x0=0D + db 0x9B=0D + db 0xCF=0D + db 0x0=0D +=0D + DATA_SEL equ $ - GDT_START=0D +=0D +DataSegDescriptor:=0D + dw 0xFFFF=0D + dw 0x0=0D + db 0x0=0D + db 0x93=0D + db 0xCF=0D + db 0x0=0D +=0D +GDT_END:=0D +=0D +GDT_Descriptor:=0D + dw GDT_END - GDT_START - 1=0D + dd GDT_START=0D +=0D +ProtectedModeEntryLinearAddress:=0D +ProtectedModeEntryLinear:=0D + DD ProtectedModeEntry ; Offset of our 32 bit code=0D + DW CODE_SEL=0D diff --git a/Platform/Qemu/QemuOpenBoardPkg/README.md b/Platform/Qemu/QemuO= penBoardPkg/README.md new file mode 100644 index 000000000000..e1238c1f4e3e --- /dev/null +++ b/Platform/Qemu/QemuOpenBoardPkg/README.md @@ -0,0 +1,53 @@ +# QemuOpenBoardPkg=0D +=0D +This project brings UEFI support to QEMU x86_64 following the MinPlatform = specification.=0D +=0D +## Capabilities=0D +=0D +- Supports IA-32 and hybrid X64 (IA32 PEI Core and X64 DXE Core)=0D +- Modern QEMU (Tested on 7.0.0)=0D + - PIIX4 and Q35 machines=0D +- Boot UEFI Linux=0D +- Boot UEFI Windows=0D +=0D +## How to build=0D +=0D +### Pre-requesites=0D +=0D +- EDK2=0D + - How to setup a local tree: https://github.com/tianocore/tianocore.gith= ub.io/wiki/Getting-Started-with-EDK-II=0D +=0D +- EDK2 Platforms=0D + - https://github.com/tianocore/edk2-platforms=0D +=0D +- Environnements variables:=0D + - WORKSPACE set to your current workspace=0D + - PACKAGES_PATH should contain path to:=0D + - edk2=0D + - edk2-platforms=0D + - edk2-platforms/Platform/Intel=0D + - edk2-platforms/Platform/Qemu=0D + - edk2-platforms/Silicon/Intel=0D +=0D +Currently QemuOpenBoardPkg's PEI Core is 32 bits only, DXE supports either= 32 bits or 64 bits=0D +=0D +QemuOpenBoardPkg (IA32 PEI - IA32 DXE)=0D +=0D +```build -a IA32 -D PEI_ARCH=3DIA32 -D DXE_ARCH=3DIA32```=0D +=0D +QemuOpenBoardPkg (IA32 PEI - X64 DXE)=0D +=0D +```build -a IA32 -a X64 -D PEI_ARCH=3DIA32 -D DXE_ARCH=3DX64```=0D +=0D +## How to use=0D +=0D +Using qemu-system-x86_64, use=0D +=0D +```-bios ```=0D +=0D +To redirect serial output to the console=0D +=0D +```-serial stdio```=0D +=0D +## Important notes=0D +- Secure boot is not yet available due to QemuOpenBoardPkg NVRAM storage n= ot being persistent yet.=0D --=20 2.32.1 (Apple Git-133)