* [edk2-platforms][PATCH v3 0/4] Implement S3 resume
@ 2022-09-12 17:12 Benjamin Doron
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 1/4] MinPlatformPkg: Add SmmLockBox to build Benjamin Doron
` (5 more replies)
0 siblings, 6 replies; 11+ messages in thread
From: Benjamin Doron @ 2022-09-12 17:12 UTC (permalink / raw)
To: devel
Cc: Sai Chaganty, Isaac Oram, Nate DeSimone, Ankit Sinha, Chasel Chiu,
Liming Gao, Eric Dong, Jeremy Soller
MinPlatform is an open-source EDK2 firmware project that can boot some
mainstream boards. However, it lacked working support for S3 resume, an
important feature for mobile platforms, which means that its
applicability as-is to mainstream use is limited. Therefore, I have now
implemented working S3 resume support on MinPlatform. This patch series
comprises a majority of one of my work products for GSoC 2022.
The BootScript-related modules are EDK2 open-source and fairly
straightforward to include. However, the partial dependency
PiSmmCommunicationPei (for signalling SMM) creates a dependency on both
the SmmAccess and SmmControl PPIs, so these are implemented here as
libraries, ported from the DXE drivers. As the register definitions are
generic, one library shim is implemented for compatibility, so the
library can be generic too. SmmAccess shall be required regardless of
SMM signalling, for the LockBox.
Like all boots, S3 resume will require working DRAM. To my
understanding, we do not need to parse the memory map HOBs again, so
some memory is allocated in DXE phase (to reserve it), the address
stashed in a variable and consumed on S3 resume flows. Some
optimisation can be performed here, regarding how much is necessary.
Stashing in a variable is imperfect, but the details must be available
without DRAM. As the FSP HOBs are published later, SmmAccess cannot be
used to retrieve from the LockBox.
Per my suspicions, notes from my mentors, Nate and Ankit, and the
coreboot code, the PAMs are opened for access to the AP wake vectors.
Presently, all are opened, more research can be performed here.
As noted, either FSP or PiSmmCpuDxeSmm can apply boot CPU structures
(GDT, IDT, MTRRs, etc). Per my research and findings by my mentors, the
closed-source module CpuInitDxe would be required, so this
implementation includes CpuS3DataDxe and open-source code will perform
this task instead.
Unfortunately, board-specific code has some tasks to perform too. I've
implemented these for Kabylake, the platform I can test. This includes
detecting the boot mode, policy (memory overwrite is contraindicated,
do not pass a VBT so FSP does not initialise graphics again) and
ensuring a special provision, if desired, for debugging
BootScriptExecutorDxe.
One major bug that blocked progress was simply specific to debugging.
DebugLibReportStatusCode should not be used for that module, because
RSC has uninstalled the serial port handler at end-of-BS. Furthermore,
it's obvious that the boot services are now unavailable. So,
DebugLibSerialPort should be used. As an aside, due to AutoGen ordering,
gBS cannot be used in SerialPortInitialize(). What really makes this
module a unique case is the fact that it's behaviour is very like
runtime drivers. For the integrity of the platform's security, the
module is copied to the LockBox at DxeSmmReadyToLock. This caused one
major bug that was blocking progress: libraries cannot attempt to
modify globals (the data section) with end-of-BS events; they will
never reach the true copy. So, rather than using flags to control code
flow, it must be coded this way instead. For instance, there is now a
special variant of I2cHdmiDebugSerialPortLib that does not use gBS in
SerialPortWrite().
Previous revisions of this patch-set tested on my Aspire VN7-572G
(Skylake). It's my belief and intention that this implementation be
ready for other platforms too (some Intel-specific assumptions made),
with a minimum of porting effort, though readying for some debugging is
recommended.
Some potential bugs include:
- Power failure is being set (PMC PWR_FLR), so BootMode == 0x0. This bit
is RW/1C, so mitigate it. Until finalised and I close the laptop
chassis, I don't know if this is a bug in Kabylake's PchPmcLib.
- Very early in testing I saw a memory init error, which means that
self-refresh failed. A BaseMemoryTest() predictably failed too,
inserted before the PEI core installs memory. Either this was fixed
in the code as I finished the implementation, or it's a bug. A major
difference in build options is SerialPortSpiFlash ->
I2cHdmiDebugSerialPortLib, but this seemed irrelevant. If it's simply
the finalised implementation, I think this isn't worth a diff against
the reflog.
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Benjamin Doron (4):
MinPlatformPkg: Add SmmLockBox to build
S3FeaturePkg: Implement working S3 resume
MinPlatformPkg: Implement working S3 resume
KabylakeOpenBoardPkg: Example of board S3
.../S3FeaturePkg/Include/PostMemory.fdf | 12 ++
.../S3FeaturePkg/Include/PreMemory.fdf | 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc | 36 +++-
.../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++
.../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++
.../S3FeaturePkg/S3FeaturePkg.dsc | 3 +
.../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++-
.../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../PeiAspireVn7Dash572GInitPreMemLib.c | 38 +++--
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 +
.../AspireVn7Dash572G/OpenBoardPkg.dsc | 21 +++
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 16 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../PeiFspMiscUpdUpdateLib.c | 11 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 ++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../GalagoPro3/OpenBoardPkg.dsc | 15 ++
.../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../PeiKabylakeRvp3InitPreMemLib.c | 27 ++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../KabylakeRvp3/OpenBoardPkg.dsc | 12 ++
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../FspWrapperHobProcessLib.c | 69 +++++++-
.../PeiFspWrapperHobProcessLib.inf | 2 +
.../Include/AcpiS3MemoryNvData.h | 22 +++
.../Include/Dsc/CoreDxeInclude.dsc | 1 +
.../Include/Dsc/CorePeiInclude.dsc | 2 +
.../Include/Fdf/CoreOsBootInclude.fdf | 1 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 4 +
39 files changed, 665 insertions(+), 52 deletions(-)
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
--
2.37.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [edk2-platforms][PATCH v3 1/4] MinPlatformPkg: Add SmmLockBox to build
2022-09-12 17:12 [edk2-platforms][PATCH v3 0/4] Implement S3 resume Benjamin Doron
@ 2022-09-12 17:12 ` Benjamin Doron
2022-09-12 23:31 ` Isaac Oram
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 2/4] S3FeaturePkg: Implement working S3 resume Benjamin Doron
` (4 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Benjamin Doron @ 2022-09-12 17:12 UTC (permalink / raw)
To: devel
Cc: Sai Chaganty, Isaac Oram, Nate DeSimone, Ankit Sinha, Chasel Chiu,
Liming Gao, Eric Dong
The LockBox is used for S3 resume in the follow-up patches, but might be
used to support other features too. So, the module is added to a
MinPlatform FV here.
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc | 1 +
Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf | 1 +
2 files changed, 2 insertions(+)
diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
index edee4b5e9dfd..f7f14501fd7d 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
+++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
@@ -145,6 +145,7 @@
UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.inf
diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf
index 1983c94d6e37..90b7681915c3 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf
@@ -21,6 +21,7 @@ INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
#INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
+INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
!endif
!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
--
2.37.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [edk2-platforms][PATCH v3 2/4] S3FeaturePkg: Implement working S3 resume
2022-09-12 17:12 [edk2-platforms][PATCH v3 0/4] Implement S3 resume Benjamin Doron
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 1/4] MinPlatformPkg: Add SmmLockBox to build Benjamin Doron
@ 2022-09-12 17:12 ` Benjamin Doron
2022-09-12 23:31 ` Isaac Oram
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 3/4] MinPlatformPkg: " Benjamin Doron
` (3 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Benjamin Doron @ 2022-09-12 17:12 UTC (permalink / raw)
To: devel; +Cc: Nate DeSimone, Ankit Sinha, Sai Chaganty, Isaac Oram, Liming Gao
Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for
memory) and FSP-related board libraries (policy overrides)
required for successful S3 resume.
Factored allocation logic into new module to avoid MinPlatform
dependency on S3Feature package.
TODO: Can optimise required size.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../S3FeaturePkg/Include/PostMemory.fdf | 12 ++
.../S3FeaturePkg/Include/PreMemory.fdf | 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc | 36 +++-
.../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++
.../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++
.../S3FeaturePkg/S3FeaturePkg.dsc | 3 +
.../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++-
.../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +-
.../Include/AcpiS3MemoryNvData.h | 22 +++
9 files changed, 365 insertions(+), 11 deletions(-)
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
index 9e17f853c630..4e87b3e68d1a 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
@@ -2,7 +2,19 @@
# FDF file for post-memory S3 advanced feature modules.
#
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
+
+## Dependencies
+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+## Save-state module stack
+ INF S3FeaturePkg/S3Dxe/S3Dxe.inf
+ INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+ INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+## Restore-state module stack
+ INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
index fdd16a4e0356..e130fa5f098d 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
@@ -2,9 +2,15 @@
# FDF file for pre-memory S3 advanced feature modules.
#
# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
-INF S3FeaturePkg/S3Pei/S3Pei.inf
+## Dependencies
+ INF S3FeaturePkg/S3Pei/S3Pei.inf
+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+
+## Restore-state module stack
+ INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
index cc34e785076a..29e8f9e8530d 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
@@ -7,6 +7,7 @@
# for the build infrastructure.
#
# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,6 +26,10 @@
!error "DXE_ARCH must be specified to build this feature!"
!endif
+[PcdsFixedAtBuild]
+ # Attempts to improve performance at the cost of more DRAM usage
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+
################################################################################
#
# Library Class section - list of all Library Classes needed by this feature.
@@ -32,7 +37,13 @@
################################################################################
[LibraryClasses.common.PEIM]
- SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf
+ SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf
+
+[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_SMM_DRIVER]
+ #######################################
+ # Edk2 Packages
+ #######################################
+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
################################################################################
#
@@ -60,8 +71,25 @@
# S3 Feature Package
#####################################
- # Add library instances here that are not included in package components and should be tested
- # in the package build.
-
# Add components here that should be included in the package build.
S3FeaturePkg/S3Pei/S3Pei.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
+
+#
+# Feature DXE Components
+#
+
+# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308
+# is completed.
+[Components.X64]
+ #####################################
+ # S3 Feature Package
+ #####################################
+
+ # Add components here that should be included in the package build.
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+ S3FeaturePkg/S3Dxe/S3Dxe.inf
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
new file mode 100644
index 000000000000..1a7ccb8eedab
--- /dev/null
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
@@ -0,0 +1,155 @@
+/** @file
+ Source code file for S3 DXE module
+
+Copyright (c) 2022, Baruch Binyamin Doron.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <PiDxe.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Guid/AcpiS3Context.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <AcpiS3MemoryNvData.h>
+
+#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE)
+
+/**
+ Get the mem size in memory type information table.
+
+ @return the mem size in memory type information table.
+**/
+UINT64
+EFIAPI
+GetMemorySizeInMemoryTypeInformation (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ EFI_MEMORY_TYPE_INFORMATION *MemoryData;
+ UINT8 Index;
+ UINTN TempPageNum;
+
+ Status = EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGuid, (VOID **) &MemoryData);
+
+ if (EFI_ERROR (Status) || MemoryData == NULL) {
+ return 0;
+ }
+
+ TempPageNum = 0;
+ for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {
+ //
+ // Accumulate default memory size requirements
+ //
+ TempPageNum += MemoryData[Index].NumberOfPages;
+ }
+
+ return TempPageNum * EFI_PAGE_SIZE;
+}
+
+/**
+ Get the mem size need to be consumed and reserved for PEI phase resume.
+
+ @return the mem size to be reserved for PEI phase resume.
+**/
+UINT64
+EFIAPI
+GetPeiMemSize (
+ VOID
+ )
+{
+ UINT64 Size;
+
+ Size = GetMemorySizeInMemoryTypeInformation ();
+
+ return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE;
+}
+
+/**
+ Allocate EfiACPIMemoryNVS below 4G memory address.
+
+ This function allocates EfiACPIMemoryNVS below 4G memory address.
+
+ @param Size Size of memory to allocate.
+
+ @return Allocated address for output.
+
+**/
+VOID *
+EFIAPI
+AllocateAcpiNvsMemoryBelow4G (
+ IN UINTN Size
+ )
+{
+ UINTN Pages;
+ EFI_PHYSICAL_ADDRESS Address;
+ EFI_STATUS Status;
+ VOID *Buffer;
+
+ Pages = EFI_SIZE_TO_PAGES (Size);
+ Address = 0xffffffff;
+
+ Status = gBS->AllocatePages (
+ AllocateMaxAddress,
+ EfiACPIMemoryNVS,
+ Pages,
+ &Address
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Buffer = (VOID *)(UINTN)Address;
+ ZeroMem (Buffer, Size);
+
+ return Buffer;
+}
+
+/**
+ Allocates memory to use on S3 resume.
+
+ @param[in] ImageHandle Not used.
+ @param[in] SystemTable General purpose services available to every DXE driver.
+
+ @retval EFI_SUCCESS The function completes successfully
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database
+**/
+EFI_STATUS
+EFIAPI
+S3DxeEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ UINT64 S3PeiMemSize;
+ UINT64 S3PeiMemBase;
+ ACPI_S3_MEMORY S3MemoryInfo;
+ EFI_STATUS Status;
+
+ DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));
+
+ S3PeiMemSize = GetPeiMemSize ();
+ S3PeiMemBase = (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize);
+ ASSERT (S3PeiMemBase != 0);
+
+ S3MemoryInfo.S3PeiMemBase = S3PeiMemBase;
+ S3MemoryInfo.S3PeiMemSize = S3PeiMemSize;
+
+ DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase));
+ DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize));
+
+ Status = gRT->SetVariable (
+ ACPI_S3_MEMORY_NV_NAME,
+ &gEfiAcpiVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ sizeof (S3MemoryInfo),
+ &S3MemoryInfo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));
+ return EFI_SUCCESS;
+}
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
new file mode 100644
index 000000000000..28589c2c869b
--- /dev/null
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
@@ -0,0 +1,49 @@
+### @file
+# Component information file for the S3 DXE module.
+#
+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = S3Dxe
+ FILE_GUID = 30926F92-CC83-4381-9F70-AC96EDB5BEE0
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ ENTRY_POINT = S3DxeEntryPoint
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+ S3FeaturePkg/S3FeaturePkg.dec
+
+[Sources]
+ S3Dxe.c
+
+[Pcd]
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize
+
+[FeaturePcd]
+ gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable
+
+[Guids]
+ gEfiMemoryTypeInformationGuid ## CONSUMES
+ gEfiAcpiVariableGuid ## CONSUMES
+
+[Depex]
+ gEfiVariableArchProtocolGuid AND
+ gEfiVariableWriteArchProtocolGuid
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc b/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc
index 2d1d197b2a95..cd4b1c4f198f 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc
@@ -41,6 +41,9 @@
!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
+[LibraryClasses.common.PEIM]
+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf
+
#
# This package always builds the feature.
#
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
index b0aaa04962c8..6acb894b6fc9 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
@@ -2,12 +2,87 @@
Source code file for S3 PEI module
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2022, Baruch Binyamin Doron.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PciLib.h>
#include <Library/PeiServicesLib.h>
#include <Library/SmmAccessLib.h>
+#include <Library/SmmControlLib.h>
+
+// TODO: Finalise implementation factoring
+#define R_SA_PAM0 (0x80)
+#define R_SA_PAM5 (0x85)
+#define R_SA_PAM6 (0x86)
+
+/**
+ This function is called after FspSiliconInitDone installed PPI.
+ For FSP API mode, this is when FSP-M HOBs are installed into EDK2.
+
+ @param[in] PeiServices Pointer to PEI Services Table.
+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that
+ caused this function to execute.
+ @param[in] Ppi Pointer to the PPI data associated with this function.
+
+ @retval EFI_STATUS Always return EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+FspSiliconInitDoneNotify (
+ IN EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,
+ IN VOID *Ppi
+ )
+{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
+ UINT64 MchBaseAddress;
+
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
+ // Enable PAM regions for AP wakeup vector (resume)
+ // - CPU is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here?
+ // TODO/TEST: coreboot does this unconditionally, vendor FWs may not (test resume). Should we?
+ // - It is certainly interesting that only PAM0, PAM5 and PAM6 are defined for KabylakeSiliconPkg.
+ // - Also note that 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - this does not mean
+ // that the memory is unusable, perhaps this is precisely because it will contain
+ // the AP wakeup vector.
+ if (BootMode == BOOT_ON_S3_RESUME) {
+ MchBaseAddress = PCI_LIB_ADDRESS (0, 0, 0, 0);
+ PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30);
+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33);
+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2), 0x33);
+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33);
+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33);
+ PciWrite8 (MchBaseAddress + R_SA_PAM5, 0x33);
+ PciWrite8 (MchBaseAddress + R_SA_PAM6, 0x33);
+ }
+
+ //
+ // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case
+ //
+ Status = PeiInstallSmmAccessPpi ();
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case
+ //
+ Status = PeiInstallSmmControlPpi ();
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc = {
+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gFspSiliconInitDonePpiGuid,
+ FspSiliconInitDoneNotify
+};
/**
S3 PEI module entry point
@@ -25,12 +100,10 @@ S3PeiEntryPoint (
IN CONST EFI_PEI_SERVICES **PeiServices
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
- //
- // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case
- //
- Status = PeiInstallSmmAccessPpi ();
+ Status = PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc);
+ ASSERT_EFI_ERROR (Status);
return Status;
}
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
index e485eac9521f..173919bb881e 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
@@ -18,10 +18,13 @@
[LibraryClasses]
PeimEntryPoint
PeiServicesLib
+ DebugLib
SmmAccessLib
+ SmmControlLib
[Packages]
MdePkg/MdePkg.dec
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
IntelSiliconPkg/IntelSiliconPkg.dec
S3FeaturePkg/S3FeaturePkg.dec
@@ -31,5 +34,8 @@
[FeaturePcd]
gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable
+[Ppis]
+ gFspSiliconInitDonePpiGuid
+
[Depex]
- gEfiPeiMemoryDiscoveredPpiGuid
+ TRUE
diff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
new file mode 100644
index 000000000000..0d75af8e9a03
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for NV data structure definition.
+
+Copyright (c) 2021, Baruch Binyamin Doron
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ACPI_S3_MEMORY_NV_DATA_H__
+#define __ACPI_S3_MEMORY_NV_DATA_H__
+
+//
+// NV data structure
+//
+typedef struct {
+ UINT64 S3PeiMemBase;
+ UINT64 S3PeiMemSize;
+} ACPI_S3_MEMORY;
+
+#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo"
+
+#endif
--
2.37.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [edk2-platforms][PATCH v3 3/4] MinPlatformPkg: Implement working S3 resume
2022-09-12 17:12 [edk2-platforms][PATCH v3 0/4] Implement S3 resume Benjamin Doron
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 1/4] MinPlatformPkg: Add SmmLockBox to build Benjamin Doron
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 2/4] S3FeaturePkg: Implement working S3 resume Benjamin Doron
@ 2022-09-12 17:12 ` Benjamin Doron
2022-09-13 1:00 ` Isaac Oram
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 4/4] KabylakeOpenBoardPkg: Example of board S3 Benjamin Doron
` (2 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Benjamin Doron @ 2022-09-12 17:12 UTC (permalink / raw)
To: devel
Cc: Chasel Chiu, Nate DeSimone, Ankit Sinha, Isaac Oram, Liming Gao,
Eric Dong
Consume S3 resume memory allocation on resume flow.
Also, include complementary FirmwarePerformanceDataTablePei module in
MinPlatform FV for S3 resume performance measurement.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../FspWrapperHobProcessLib.c | 69 ++++++++++++++++++-
.../PeiFspWrapperHobProcessLib.inf | 2 +
.../Include/Dsc/CorePeiInclude.dsc | 2 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 4 ++
4 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
index 7ee4d3a31c49..9bd6fe6290c5 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
@@ -16,14 +16,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/FspWrapperPlatformLib.h>
+#include <Guid/AcpiS3Context.h>
#include <Guid/GuidHobFspEas.h>
#include <Guid/MemoryTypeInformation.h>
#include <Guid/GraphicsInfoHob.h>
#include <Guid/PcdDataBaseHobGuid.h>
#include <Guid/ZeroGuid.h>
#include <Ppi/Capsule.h>
+#include <Ppi/ReadOnlyVariable2.h>
#include <FspEas.h>
+#include <AcpiS3MemoryNvData.h>
//
// Additional pages are used by DXE memory manager.
@@ -130,6 +133,55 @@ GetPeiMemSize (
return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE;
}
+/**
+ Get S3 PEI memory information.
+
+ @note At this point, memory is ready, and PeiServices are available to use.
+ Platform can get some data from SMRAM directly.
+
+ @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.
+ @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.
+
+ @return If S3 PEI memory information is got successfully.
+**/
+EFI_STATUS
+EFIAPI
+GetS3MemoryInfo (
+ OUT UINT64 *S3PeiMemSize,
+ OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
+ UINTN DataSize;
+ ACPI_S3_MEMORY S3MemoryInfo;
+
+ *S3PeiMemBase = 0;
+ *S3PeiMemSize = 0;
+
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi);
+ ASSERT_EFI_ERROR (Status);
+
+ DataSize = sizeof (S3MemoryInfo);
+ Status = VariablePpi->GetVariable (
+ VariablePpi,
+ ACPI_S3_MEMORY_NV_NAME,
+ &gEfiAcpiVariableGuid,
+ NULL,
+ &DataSize,
+ &S3MemoryInfo
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ *S3PeiMemBase = S3MemoryInfo.S3PeiMemBase;
+ *S3PeiMemSize = S3MemoryInfo.S3PeiMemSize;
+ return EFI_SUCCESS;
+}
+
/**
Post FSP-M HOB process for Memory Resource Descriptor.
@@ -280,7 +332,7 @@ PostFspmHobProcess (
0x1000
);
-
+ if (BootMode != BOOT_ON_S3_RESUME) {
//
// Capsule mode
//
@@ -337,7 +389,22 @@ PostFspmHobProcess (
if (Capsule != NULL) {
Status = Capsule->CreateState ((EFI_PEI_SERVICES **)PeiServices, CapsuleBuffer, CapsuleBufferLength);
}
+ } else {
+ Status = GetS3MemoryInfo (&PeiMemSize, &PeiMemBase);
+ ASSERT_EFI_ERROR (Status);
+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemBase : 0x%08x\n", PeiMemBase));
+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemSize : 0x%08x\n", PeiMemSize));
+
+ //
+ // Install efi memory
+ //
+ Status = PeiServicesInstallPeiMemory (
+ PeiMemBase,
+ PeiMemSize
+ );
+ ASSERT_EFI_ERROR (Status);
+ }
//
// Create a memory allocation HOB at fixed location for MP Services PPI AP wait loop.
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
index b846e7af1d2d..e2aac36bf018 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
@@ -75,7 +75,9 @@
gZeroGuid
gEfiGraphicsInfoHobGuid
gEfiGraphicsDeviceInfoHobGuid
+ gEfiAcpiVariableGuid
[Ppis]
gEfiPeiCapsulePpiGuid ## CONSUMES
+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES
gEdkiiSiliconInitializedPpiGuid ## PRODUCES
diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
index 08e50cac075f..f271fb26b189 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
@@ -41,3 +41,5 @@
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf
}
!endif
+
+ MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
diff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
index 3c2716d6728a..3edc239e5264 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
@@ -6,3 +6,7 @@
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
+
+!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
+ INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf
+!endif
--
2.37.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [edk2-platforms][PATCH v3 4/4] KabylakeOpenBoardPkg: Example of board S3
2022-09-12 17:12 [edk2-platforms][PATCH v3 0/4] Implement S3 resume Benjamin Doron
` (2 preceding siblings ...)
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 3/4] MinPlatformPkg: " Benjamin Doron
@ 2022-09-12 17:12 ` Benjamin Doron
2022-09-12 23:32 ` Isaac Oram
2022-10-12 1:31 ` [edk2-platforms][PATCH v3 0/4] Implement S3 resume Isaac Oram
[not found] ` <171D2E406AE360FA.17458@groups.io>
5 siblings, 1 reply; 11+ messages in thread
From: Benjamin Doron @ 2022-09-12 17:12 UTC (permalink / raw)
To: devel
Cc: Nate DeSimone, Ankit Sinha, Chasel Chiu, Jeremy Soller,
Sai Chaganty, Isaac Oram
Use silicon code to detect S3 resume state. Apply some relevant policy
modifications.
PcdPeiMemSize must be in common scope, for a DXE module to allocate
required memory. Libraries that produce required PPIs are defined.
BootScriptExecutorDxe should only be linked against a functionally
compatible debug stack.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../PeiFspMiscUpdUpdateLib.c | 12 +++++-
.../PeiSaPolicyUpdate.c | 12 +++++-
.../PeiAspireVn7Dash572GInitPreMemLib.c | 38 +++++++++++--------
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 ++
.../AspireVn7Dash572G/OpenBoardPkg.dsc | 21 ++++++++++
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 16 ++------
.../PeiSiliconPolicyUpdateLib.c | 11 +++++-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../PeiFspMiscUpdUpdateLib.c | 11 +++++-
.../PeiSaPolicyUpdate.c | 12 +++++-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 ++++++++++++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../GalagoPro3/OpenBoardPkg.dsc | 15 ++++++++
.../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +++++-
.../PeiSaPolicyUpdate.c | 12 +++++-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../PeiKabylakeRvp3InitPreMemLib.c | 27 ++++++++++++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../KabylakeRvp3/OpenBoardPkg.dsc | 12 ++++++
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +++++-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
24 files changed, 222 insertions(+), 40 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index a9b7e446c8d6..7e4194bf4fe6 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,6 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/PciLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
+
#include <FspEas.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
@@ -32,11 +34,15 @@ PeiFspMiscUpdUpdatePreMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
UINTN VariableSize;
VOID *FspNvsBufferPtr;
UINT8 MorControl;
VOID *MorControlPtr;
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
//
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
//
@@ -70,7 +76,11 @@ PeiFspMiscUpdUpdatePreMem (
&VariableSize
);
DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
- if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+ //
+ // Do not set CleanMemory on S3 resume
+ // TODO: Handle advanced features later - capsule update is in-memory list
+ //
+ if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) {
FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index 4621cbd3ca3a..98db86570368 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
/**
Performs FSP SA PEI Policy initialization.
@@ -27,12 +28,17 @@ PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
)
{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
Size = 0;
@@ -40,7 +46,11 @@ PeiFspSaPolicyUpdate (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialization is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
index 1c9a65399b54..3029354b96cd 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
@@ -11,7 +11,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/PcdLib.h>
#include <Library/PchCycleDecodingLib.h>
+#include <Library/PchPmcLib.h>
#include <Library/PchResetLib.h>
+#include <Library/PciLib.h>
#include <Library/SiliconInitLib.h>
#include <Library/TimerLib.h>
#include <Library/PeiLib.h>
@@ -267,25 +269,31 @@ AspireVn7Dash572GBoardBootModeDetect (
VOID
)
{
- UINT16 ABase;
+ EFI_BOOT_MODE BootMode;
UINT32 SleepType;
DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
- // TODO: Perform advanced detection (recovery/capsule)
- // FIXME: This violates PI specification? But BOOT_WITH* would always take precedence
- // over BOOT_ON_S{4,5}...
- PchAcpiBaseGet (&ABase);
- SleepType = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT_SLP_TYP;
+ // Known sane defaults; TODO: Consider "default"?
+ BootMode = BOOT_WITH_FULL_CONFIGURATION;
- switch (SleepType) {
- case V_PCH_ACPI_PM1_CNT_S3:
- return BOOT_ON_S3_RESUME;
- case V_PCH_ACPI_PM1_CNT_S4:
- return BOOT_ON_S4_RESUME;
-// case V_PCH_ACPI_PM1_CNT_S5:
-// return BOOT_ON_S5_RESUME;
- default:
- return BOOT_WITH_FULL_CONFIGURATION;
+ // TODO: Perform advanced detection (capsule/recovery)
+ // TODO: Perform "IsFirstBoot" test with VariablePpi for "minimal"/"assume"
+ if (GetSleepTypeAfterWakeup (&SleepType)) {
+ switch (SleepType) {
+ case V_PCH_ACPI_PM1_CNT_S3:
+ BootMode = BOOT_ON_S3_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S4:
+ BootMode = BOOT_ON_S4_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S5:
+ BootMode = BOOT_ON_S5_RESUME;
+ break;
+ }
}
+
+ DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
+
+ return BootMode;
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index cd9f979d313c..c53114e15450 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -25,11 +25,14 @@
TimerLib
PchCycleDecodingLib
PchResetLib
+ PciLib
IoLib
EcLib
BoardEcLib
GpioLib
PeiLib
+ PeiServicesLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
index efe29c617a02..20c42a7c1c20 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
@@ -249,6 +249,7 @@
# Silicon Package
#######################################
ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
#######################################
# Platform Package
@@ -712,6 +713,26 @@
!endif
}
+!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
+ <LibraryClasses>
+ # On S3 resume, RSC is in end-of-BS state
+ # - Moreover: Library cannot effectively use some end-of-BS events
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ # Reverse-ranked priority list
+# TODO: Requires testing
+# - Strongly suspect DebugLibSerialPort constructor presents PeiDxeSerialPortLibMem dependency on services as a bug
+!if FALSE # $(USE_MEMORY_LOGGING) == TRUE
+ SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/DxeSerialPortLibMem.inf
+!endif
+ # Also, can debug CpuExceptionHandlerLib
+!if $(USE_HDMI_DEBUG_PORT) == TRUE
+ SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPortLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf
+!endif
+ }
+!endif
+
!endif
#######################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index 3ed7aa0a2b10..490c3ee6bf76 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
@@ -127,10 +127,7 @@
# PcdIpmiFeatureEnable will not be enabled (no BMC)
# TODO: Can be build-time (user) choice
gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |FALSE
- # TODO: Continue developing support. Broken at present.
- # - PeiSmmAccessLib in IntelSiliconPkg seems like a stub
- # - May require a PeiSmmControlLib to SMM communicate
- gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |FALSE
+ gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |TRUE
# TODO: Definitions (now added SmbiosDxe)
gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable |TRUE
# Requires actual hook-up
@@ -335,6 +332,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|4
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
#
# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
@@ -360,13 +358,8 @@
# 0x7F, 0xFF, 0x04, 0x00}<BR>
gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF, 0x04, 0x00}
-!if $(TARGET) == RELEASE
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x800
-!else
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B # TODO
-!endif
- # TODO: Consider using reserved space instead for debug log
- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x200
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x4800
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100
!if $(TARGET) == RELEASE
gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70
!else
@@ -447,7 +440,6 @@
# Edk2 Configuration
######################################
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
######################################
# Platform Configuration
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
index 3764f7c3ac09..04cd2e741489 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/ConfigBlockLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/CpuPlatformLib.h>
@@ -549,6 +550,7 @@ SiliconPolicyUpdatePostMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
@@ -557,6 +559,9 @@ SiliconPolicyUpdatePostMem (
DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
GtConfig = NULL;
Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
ASSERT_EFI_ERROR (Status);
@@ -571,7 +576,11 @@ SiliconPolicyUpdatePostMem (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialization is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
index 1ce26fc3dcec..31a45292209d 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -23,6 +23,7 @@
BaseMemoryLib
MemoryAllocationLib
PeiLib
+ PeiServicesLib
CpuPlatformLib
PchPcieRpLib
PchInfoLib
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index dbc84631acaa..ce309bd378d2 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/PeiLib.h>
#include <Library/ConfigBlockLib.h>
+#include <Library/PeiServicesLib.h>
#include <FspEas.h>
#include <FspmUpd.h>
@@ -36,11 +37,15 @@ PeiFspMiscUpdUpdatePreMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
UINTN VariableSize;
VOID *FspNvsBufferPtr;
UINT8 MorControl;
VOID *MorControlPtr;
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
//
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
//
@@ -75,7 +80,11 @@ PeiFspMiscUpdUpdatePreMem (
&VariableSize
);
DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
- if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+ //
+ // Do not set CleanMemory on S3 resume
+ // TODO: Handle advanced features later - capsule update is in-memory list
+ //
+ if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) {
FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index 133b8c963f65..6fd45cc79f61 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
/**
Performs FSP SA PEI Policy initialization.
@@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
)
{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
Size = 0;
@@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialization is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index d6c91cd2b94b..5b3a6921d0ee 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -23,6 +23,7 @@
PcdLib
SiliconInitLib
PchResetLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c
index 051dac0b204d..1cd2baf4a4dd 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c
@@ -14,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/PchCycleDecodingLib.h>
+#include <Library/PchPmcLib.h>
#include <Library/PciLib.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
@@ -236,5 +237,29 @@ GalagoPro3BoardBootModeDetect (
VOID
)
{
- return BOOT_WITH_FULL_CONFIGURATION;
+ EFI_BOOT_MODE BootMode;
+ UINT32 SleepType;
+
+ DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
+
+ // Known sane defaults
+ BootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+ if (GetSleepTypeAfterWakeup (&SleepType)) {
+ switch (SleepType) {
+ case V_PCH_ACPI_PM1_CNT_S3:
+ BootMode = BOOT_ON_S3_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S4:
+ BootMode = BOOT_ON_S4_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S5:
+ BootMode = BOOT_ON_S5_RESUME;
+ break;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
+
+ return BootMode;
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index fe31f421356e..20ddac1d994d 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -25,6 +25,7 @@
SiliconInitLib
MultiBoardInitSupportLib
PchResetLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index f0e9a21ccad9..219ef20e55f0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -180,6 +180,7 @@
# Silicon Package
#######################################
ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
#######################################
# Platform Package
@@ -494,6 +495,20 @@
!endif
}
+!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
+ <LibraryClasses>
+ # On S3 resume, RSC is in end-of-BS state
+ # - Moreover: Libraries cannot effectively use some end-of-BS events
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ # Reverse-ranked priority list
+!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdI2cHdmiDebugPortEnable == TRUE
+ SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPortLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf
+!endif
+ }
+!endif
+
!endif
#######################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index 8180312f5ca5..7a73f5a831c6 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -279,6 +279,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
#
# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
@@ -380,7 +381,6 @@
######################################
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
######################################
# Platform Configuration
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index 699f4297fad6..71b03f2da464 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,11 +11,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/PeiLib.h>
#include <Library/ConfigBlockLib.h>
+#include <Library/PeiServicesLib.h>
#include <FspEas.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
-
#include <Library/DebugLib.h>
#include <Library/DebugPrintErrorLevelLib.h>
#include <Library/PciLib.h>
@@ -36,11 +36,15 @@ PeiFspMiscUpdUpdatePreMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
UINTN VariableSize;
VOID *FspNvsBufferPtr;
UINT8 MorControl;
VOID *MorControlPtr;
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
//
// Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths.
//
@@ -73,7 +77,11 @@ PeiFspMiscUpdUpdatePreMem (
&VariableSize
);
DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));
- if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {
+ //
+ // Do not set CleanMemory on S3 resume
+ // TODO: Handle advanced features later - capsule update is in-memory list
+ //
+ if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) {
FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK);
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index d6ec3e38dd7e..e855207af0d1 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/PeiSaPolicyLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
/**
Performs FSP SA PEI Policy initialization.
@@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd
)
{
+ EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1;
Size = 0;
@@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialization is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index 850fc514188b..e0022e8d6118 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
@@ -24,6 +24,7 @@
SiliconInitLib
EcLib
PchResetLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c
index 87ae3b531ed6..02cd37227e50 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c
@@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/HobLib.h>
#include <Library/PcdLib.h>
#include <Library/PchCycleDecodingLib.h>
+#include <Library/PchPmcLib.h>
#include <Library/PciLib.h>
#include <Library/PcdLib.h>
#include <Library/BaseMemoryLib.h>
@@ -330,5 +331,29 @@ KabylakeRvp3BoardBootModeDetect (
VOID
)
{
- return BOOT_WITH_FULL_CONFIGURATION;
+ EFI_BOOT_MODE BootMode;
+ UINT32 SleepType;
+
+ DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
+
+ // Known sane defaults
+ BootMode = BOOT_WITH_FULL_CONFIGURATION;
+
+ if (GetSleepTypeAfterWakeup (&SleepType)) {
+ switch (SleepType) {
+ case V_PCH_ACPI_PM1_CNT_S3:
+ BootMode = BOOT_ON_S3_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S4:
+ BootMode = BOOT_ON_S4_RESUME;
+ break;
+ case V_PCH_ACPI_PM1_CNT_S5:
+ BootMode = BOOT_ON_S5_RESUME;
+ break;
+ }
+ }
+
+ DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));
+
+ return BootMode;
}
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index 23fe6b6f03c5..0112bf84a193 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -26,6 +26,7 @@
MultiBoardInitSupportLib
EcLib
PchResetLib
+ PchPmcLib
[Packages]
MinPlatformPkg/MinPlatformPkg.dec
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 37837eeb04bf..1634d9b31f00 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -202,6 +202,7 @@
# Silicon Package
#######################################
ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf
#######################################
# Platform Package
@@ -506,6 +507,17 @@
!endif
}
+!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
+ <LibraryClasses>
+ # On S3 resume, RSC is in end-of-BS state
+ # - Moreover: Libraries cannot effectively use some end-of-BS events
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf
+ # TODO: Insert a reverse-ranked priority list of compatible libraries here
+ }
+!endif
+
!endif
#######################################
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index cfd032814850..87510748783f 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
@@ -279,6 +279,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
#
# The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
@@ -349,7 +350,6 @@
######################################
gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
######################################
# Platform Configuration
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
index 22aadc0221df..bd3da7f38416 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DebugLib.h>
#include <Library/ConfigBlockLib.h>
#include <Library/PeiLib.h>
+#include <Library/PeiServicesLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/CpuPlatformLib.h>
@@ -513,6 +514,7 @@ SiliconPolicyUpdatePostMem (
)
{
EFI_STATUS Status;
+ EFI_BOOT_MODE BootMode;
VOID *Buffer;
VOID *MemBuffer;
UINT32 Size;
@@ -521,6 +523,9 @@ SiliconPolicyUpdatePostMem (
DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n"));
+ Status = PeiServicesGetBootMode (&BootMode);
+ ASSERT_EFI_ERROR (Status);
+
GtConfig = NULL;
Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig);
ASSERT_EFI_ERROR (Status);
@@ -535,7 +540,11 @@ SiliconPolicyUpdatePostMem (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size);
if (Buffer == NULL) {
DEBUG((DEBUG_WARN, "Could not locate VBT\n"));
- } else {
+ //
+ // Graphics initialization is unnecessary,
+ // OS has present framebuffer.
+ //
+ } else if (BootMode != BOOT_ON_S3_RESUME) {
MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size));
if ((MemBuffer != NULL) && (Buffer != NULL)) {
CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
index 25eae88f5989..e9a23593e133 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -23,6 +23,7 @@
BaseMemoryLib
MemoryAllocationLib
PeiLib
+ PeiServicesLib
CpuPlatformLib
PchPcieRpLib
PchInfoLib
--
2.37.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms][PATCH v3 1/4] MinPlatformPkg: Add SmmLockBox to build
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 1/4] MinPlatformPkg: Add SmmLockBox to build Benjamin Doron
@ 2022-09-12 23:31 ` Isaac Oram
0 siblings, 0 replies; 11+ messages in thread
From: Isaac Oram @ 2022-09-12 23:31 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Sinha, Ankit,
Chiu, Chasel, Gao, Liming, Dong, Eric
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Monday, September 12, 2022 10:13 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>
Subject: [edk2-platforms][PATCH v3 1/4] MinPlatformPkg: Add SmmLockBox to build
The LockBox is used for S3 resume in the follow-up patches, but might be used to support other features too. So, the module is added to a MinPlatform FV here.
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc | 1 +
Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf | 1 +
2 files changed, 2 insertions(+)
diff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
index edee4b5e9dfd..f7f14501fd7d 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
+++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc
@@ -145,6 +145,7 @@
UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTableDxe/FirmwarePerformanceDxe.infdiff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf
index 1983c94d6e37..90b7681915c3 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CoreOsBootInclude.fdf
@@ -21,6 +21,7 @@ INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
#INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf+INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf !endif !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE--
2.37.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms][PATCH v3 2/4] S3FeaturePkg: Implement working S3 resume
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 2/4] S3FeaturePkg: Implement working S3 resume Benjamin Doron
@ 2022-09-12 23:31 ` Isaac Oram
0 siblings, 0 replies; 11+ messages in thread
From: Isaac Oram @ 2022-09-12 23:31 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Sinha, Ankit, Chaganty, Rangasai V,
Gao, Liming
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Monday, September 12, 2022 10:13 AM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>
Subject: [edk2-platforms][PATCH v3 2/4] S3FeaturePkg: Implement working S3 resume
Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for
memory) and FSP-related board libraries (policy overrides) required for successful S3 resume.
Factored allocation logic into new module to avoid MinPlatform dependency on S3Feature package.
TODO: Can optimise required size.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../S3FeaturePkg/Include/PostMemory.fdf | 12 ++
.../S3FeaturePkg/Include/PreMemory.fdf | 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc | 36 +++-
.../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++
.../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++
.../S3FeaturePkg/S3FeaturePkg.dsc | 3 +
.../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++-
.../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +-
.../Include/AcpiS3MemoryNvData.h | 22 +++
9 files changed, 365 insertions(+), 11 deletions(-) create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
index 9e17f853c630..4e87b3e68d1a 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf
@@ -2,7 +2,19 @@
# FDF file for post-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+# Copyright (c) 2022, Baruch Binyamin Doron.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # ##++## Dependencies+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf++## Save-state module stack+ INF S3FeaturePkg/S3Dxe/S3Dxe.inf+ INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf+ INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf++## Restore-state module stack+ INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.infdiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
index fdd16a4e0356..e130fa5f098d 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf
@@ -2,9 +2,15 @@
# FDF file for pre-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+# Copyright (c) 2022, Baruch Binyamin Doron.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # ## -INF S3FeaturePkg/S3Pei/S3Pei.inf+## Dependencies+ INF S3FeaturePkg/S3Pei/S3Pei.inf+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf++## Restore-state module stack+ INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.infdiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
index cc34e785076a..29e8f9e8530d 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc
@@ -7,6 +7,7 @@
# for the build infrastructure. # # Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>+# Copyright (c) 2022, Baruch Binyamin Doron.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent #@@ -25,6 +26,10 @@
!error "DXE_ARCH must be specified to build this feature!" !endif +[PcdsFixedAtBuild]+ # Attempts to improve performance at the cost of more DRAM usage+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE+ ################################################################################ # # Library Class section - list of all Library Classes needed by this feature.@@ -32,7 +37,13 @@
################################################################################ [LibraryClasses.common.PEIM]- SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf+ SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf++[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_SMM_DRIVER]+ #######################################+ # Edk2 Packages+ #######################################+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf ################################################################################ #@@ -60,8 +71,25 @@
# S3 Feature Package ##################################### - # Add library instances here that are not included in package components and should be tested- # in the package build.- # Add components here that should be included in the package build. S3FeaturePkg/S3Pei/S3Pei.inf+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf++#+# Feature DXE Components+#++# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzilla.tianocore.org/show_bug.cgi?id=2308+# is completed.+[Components.X64]+ #####################################+ # S3 Feature Package+ #####################################++ # Add components here that should be included in the package build.+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf+ S3FeaturePkg/S3Dxe/S3Dxe.inf+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.infdiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
new file mode 100644
index 000000000000..1a7ccb8eedab
--- /dev/null
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
@@ -0,0 +1,155 @@
+/** @file+ Source code file for S3 DXE module++Copyright (c) 2022, Baruch Binyamin Doron.<BR>+SPDX-License-Identifier: BSD-2-Clause-Patent++**/++#include <PiDxe.h>+#include <Library/BaseMemoryLib.h>+#include <Library/DebugLib.h>+#include <Library/PcdLib.h>+#include <Library/UefiLib.h>+#include <Library/UefiBootServicesTableLib.h>+#include <Library/UefiRuntimeServicesTableLib.h>+#include <Guid/AcpiS3Context.h>+#include <Guid/MemoryTypeInformation.h>+#include <AcpiS3MemoryNvData.h>++#define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE)++/**+ Get the mem size in memory type information table.++ @return the mem size in memory type information table.+**/+UINT64+EFIAPI+GetMemorySizeInMemoryTypeInformation (+ VOID+ )+{+ EFI_STATUS Status;+ EFI_MEMORY_TYPE_INFORMATION *MemoryData;+ UINT8 Index;+ UINTN TempPageNum;++ Status = EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGuid, (VOID **) &MemoryData);++ if (EFI_ERROR (Status) || MemoryData == NULL) {+ return 0;+ }++ TempPageNum = 0;+ for (Index = 0; MemoryData[Index].Type != EfiMaxMemoryType; Index++) {+ //+ // Accumulate default memory size requirements+ //+ TempPageNum += MemoryData[Index].NumberOfPages;+ }++ return TempPageNum * EFI_PAGE_SIZE;+}++/**+ Get the mem size need to be consumed and reserved for PEI phase resume.++ @return the mem size to be reserved for PEI phase resume.+**/+UINT64+EFIAPI+GetPeiMemSize (+ VOID+ )+{+ UINT64 Size;++ Size = GetMemorySizeInMemoryTypeInformation ();++ return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE;+}++/**+ Allocate EfiACPIMemoryNVS below 4G memory address.++ This function allocates EfiACPIMemoryNVS below 4G memory address.++ @param Size Size of memory to allocate.++ @return Allocated address for output.++**/+VOID *+EFIAPI+AllocateAcpiNvsMemoryBelow4G (+ IN UINTN Size+ )+{+ UINTN Pages;+ EFI_PHYSICAL_ADDRESS Address;+ EFI_STATUS Status;+ VOID *Buffer;++ Pages = EFI_SIZE_TO_PAGES (Size);+ Address = 0xffffffff;++ Status = gBS->AllocatePages (+ AllocateMaxAddress,+ EfiACPIMemoryNVS,+ Pages,+ &Address+ );+ ASSERT_EFI_ERROR (Status);++ Buffer = (VOID *)(UINTN)Address;+ ZeroMem (Buffer, Size);++ return Buffer;+}++/**+ Allocates memory to use on S3 resume.++ @param[in] ImageHandle Not used.+ @param[in] SystemTable General purpose services available to every DXE driver.++ @retval EFI_SUCCESS The function completes successfully+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create database+**/+EFI_STATUS+EFIAPI+S3DxeEntryPoint (+ IN EFI_HANDLE ImageHandle,+ IN EFI_SYSTEM_TABLE *SystemTable+ )+{+ UINT64 S3PeiMemSize;+ UINT64 S3PeiMemBase;+ ACPI_S3_MEMORY S3MemoryInfo;+ EFI_STATUS Status;++ DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__));++ S3PeiMemSize = GetPeiMemSize ();+ S3PeiMemBase = (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize);+ ASSERT (S3PeiMemBase != 0);++ S3MemoryInfo.S3PeiMemBase = S3PeiMemBase;+ S3MemoryInfo.S3PeiMemSize = S3PeiMemSize;++ DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase));+ DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize));++ Status = gRT->SetVariable (+ ACPI_S3_MEMORY_NV_NAME,+ &gEfiAcpiVariableGuid,+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,+ sizeof (S3MemoryInfo),+ &S3MemoryInfo+ );+ ASSERT_EFI_ERROR (Status);++ DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__));+ return EFI_SUCCESS;+}diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
new file mode 100644
index 000000000000..28589c2c869b
--- /dev/null
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
@@ -0,0 +1,49 @@
+### @file+# Component information file for the S3 DXE module.+#+# Copyright (c) 2022, Baruch Binyamin Doron.<BR>+#+# SPDX-License-Identifier: BSD-2-Clause-Patent+#+###++[Defines]+ INF_VERSION = 0x00010017+ BASE_NAME = S3Dxe+ FILE_GUID = 30926F92-CC83-4381-9F70-AC96EDB5BEE0+ VERSION_STRING = 1.0+ MODULE_TYPE = DXE_DRIVER+ ENTRY_POINT = S3DxeEntryPoint++[LibraryClasses]+ UefiDriverEntryPoint+ UefiBootServicesTableLib+ UefiRuntimeServicesTableLib+ BaseMemoryLib+ DebugLib+ PcdLib+ UefiLib++[Packages]+ MdePkg/MdePkg.dec+ MdeModulePkg/MdeModulePkg.dec+ MinPlatformPkg/MinPlatformPkg.dec+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec+ S3FeaturePkg/S3FeaturePkg.dec++[Sources]+ S3Dxe.c++[Pcd]+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize++[FeaturePcd]+ gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable++[Guids]+ gEfiMemoryTypeInformationGuid ## CONSUMES+ gEfiAcpiVariableGuid ## CONSUMES++[Depex]+ gEfiVariableArchProtocolGuid AND+ gEfiVariableWriteArchProtocolGuiddiff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc b/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc
index 2d1d197b2a95..cd4b1c4f198f 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3FeaturePkg.dsc
@@ -41,6 +41,9 @@
!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc +[LibraryClasses.common.PEIM]+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf+ # # This package always builds the feature. #diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
index b0aaa04962c8..6acb894b6fc9 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c
@@ -2,12 +2,87 @@
Source code file for S3 PEI module Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2022, Baruch Binyamin Doron.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent **/ +#include <PiPei.h>+#include <Library/DebugLib.h>+#include <Library/PciLib.h> #include <Library/PeiServicesLib.h> #include <Library/SmmAccessLib.h>+#include <Library/SmmControlLib.h>++// TODO: Finalise implementation factoring+#define R_SA_PAM0 (0x80)+#define R_SA_PAM5 (0x85)+#define R_SA_PAM6 (0x86)++/**+ This function is called after FspSiliconInitDone installed PPI.+ For FSP API mode, this is when FSP-M HOBs are installed into EDK2.++ @param[in] PeiServices Pointer to PEI Services Table.+ @param[in] NotifyDesc Pointer to the descriptor for the Notification event that+ caused this function to execute.+ @param[in] Ppi Pointer to the PPI data associated with this function.++ @retval EFI_STATUS Always return EFI_SUCCESS+**/+EFI_STATUS+EFIAPI+FspSiliconInitDoneNotify (+ IN EFI_PEI_SERVICES **PeiServices,+ IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc,+ IN VOID *Ppi+ )+{+ EFI_STATUS Status;+ EFI_BOOT_MODE BootMode;+ UINT64 MchBaseAddress;++ Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);++ // Enable PAM regions for AP wakeup vector (resume)+ // - CPU is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here?+ // TODO/TEST: coreboot does this unconditionally, vendor FWs may not (test resume). Should we?+ // - It is certainly interesting that only PAM0, PAM5 and PAM6 are defined for KabylakeSiliconPkg.+ // - Also note that 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - this does not mean+ // that the memory is unusable, perhaps this is precisely because it will contain+ // the AP wakeup vector.+ if (BootMode == BOOT_ON_S3_RESUME) {+ MchBaseAddress = PCI_LIB_ADDRESS (0, 0, 0, 0);+ PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2), 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33);+ PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33);+ PciWrite8 (MchBaseAddress + R_SA_PAM5, 0x33);+ PciWrite8 (MchBaseAddress + R_SA_PAM6, 0x33);+ }++ //+ // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case+ //+ Status = PeiInstallSmmAccessPpi ();+ ASSERT_EFI_ERROR (Status);++ //+ // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case+ //+ Status = PeiInstallSmmControlPpi ();+ ASSERT_EFI_ERROR (Status);++ return Status;+}++EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc = {+ (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),+ &gFspSiliconInitDonePpiGuid,+ FspSiliconInitDoneNotify+}; /** S3 PEI module entry point@@ -25,12 +100,10 @@ S3PeiEntryPoint (
IN CONST EFI_PEI_SERVICES **PeiServices ) {- EFI_STATUS Status;+ EFI_STATUS Status; - //- // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case- //- Status = PeiInstallSmmAccessPpi ();+ Status = PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc);+ ASSERT_EFI_ERROR (Status); return Status; }diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
index e485eac9521f..173919bb881e 100644
--- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
+++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf
@@ -18,10 +18,13 @@
[LibraryClasses] PeimEntryPoint PeiServicesLib+ DebugLib SmmAccessLib+ SmmControlLib [Packages] MdePkg/MdePkg.dec+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec S3FeaturePkg/S3FeaturePkg.dec @@ -31,5 +34,8 @@
[FeaturePcd] gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable +[Ppis]+ gFspSiliconInitDonePpiGuid+ [Depex]- gEfiPeiMemoryDiscoveredPpiGuid+ TRUEdiff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
new file mode 100644
index 000000000000..0d75af8e9a03
--- /dev/null
+++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
@@ -0,0 +1,22 @@
+/** @file
+ Header file for NV data structure definition.
+
+Copyright (c) 2021, Baruch Binyamin Doron
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __ACPI_S3_MEMORY_NV_DATA_H__
+#define __ACPI_S3_MEMORY_NV_DATA_H__
+
+//
+// NV data structure
+//
+typedef struct {
+ UINT64 S3PeiMemBase;
+ UINT64 S3PeiMemSize;
+} ACPI_S3_MEMORY;
+
+#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo"
+
+#endif
--
2.37.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms][PATCH v3 4/4] KabylakeOpenBoardPkg: Example of board S3
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 4/4] KabylakeOpenBoardPkg: Example of board S3 Benjamin Doron
@ 2022-09-12 23:32 ` Isaac Oram
0 siblings, 0 replies; 11+ messages in thread
From: Isaac Oram @ 2022-09-12 23:32 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Desimone, Nathaniel L, Sinha, Ankit, Chiu, Chasel, Soller, Jeremy,
Chaganty, Rangasai V
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Monday, September 12, 2022 10:13 AM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Soller, Jeremy <jeremy@system76.com>; Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>
Subject: [edk2-platforms][PATCH v3 4/4] KabylakeOpenBoardPkg: Example of board S3
Use silicon code to detect S3 resume state. Apply some relevant policy modifications.
PcdPeiMemSize must be in common scope, for a DXE module to allocate required memory. Libraries that produce required PPIs are defined.
BootScriptExecutorDxe should only be linked against a functionally compatible debug stack.
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../PeiFspMiscUpdUpdateLib.c | 12 +++++-
.../PeiSaPolicyUpdate.c | 12 +++++-
.../PeiAspireVn7Dash572GInitPreMemLib.c | 38 +++++++++++--------
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 ++
.../AspireVn7Dash572G/OpenBoardPkg.dsc | 21 ++++++++++
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 16 ++------
.../PeiSiliconPolicyUpdateLib.c | 11 +++++-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../PeiFspMiscUpdUpdateLib.c | 11 +++++-
.../PeiSaPolicyUpdate.c | 12 +++++-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 ++++++++++++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../GalagoPro3/OpenBoardPkg.dsc | 15 ++++++++
.../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +++++-
.../PeiSaPolicyUpdate.c | 12 +++++-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../PeiKabylakeRvp3InitPreMemLib.c | 27 ++++++++++++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../KabylakeRvp3/OpenBoardPkg.dsc | 12 ++++++
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +++++-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
24 files changed, 222 insertions(+), 40 deletions(-)
diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index a9b7e446c8d6..7e4194bf4fe6 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/L
+++ ibrary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,6 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/DebugLib.h> #include <Library/PciLib.h> #include <Library/PeiLib.h>+#include <Library/PeiServicesLib.h>+ #include <FspEas.h> #include <FspmUpd.h> #include <FspsUpd.h>@@ -32,11 +34,15 @@ PeiFspMiscUpdUpdatePreMem (
) { EFI_STATUS Status;+ EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; + Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);+ // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. //@@ -70,7 +76,11 @@ PeiFspMiscUpdUpdatePreMem (
&VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));- if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {+ //+ // Do not set CleanMemory on S3 resume+ // TODO: Handle advanced features later - capsule update is in-memory list+ //+ if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) { FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK); } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index 4621cbd3ca3a..98db86570368 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/L
+++ ibrary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h> #include <Library/PeiSaPolicyLib.h> #include <Library/PeiLib.h>+#include <Library/PeiServicesLib.h> /** Performs FSP SA PEI Policy initialization.@@ -27,12 +28,17 @@ PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd ) {+ EFI_STATUS Status;+ EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);+ FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1; Size = 0;@@ -40,7 +46,11 @@ PeiFspSaPolicyUpdate (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); if (Buffer == NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n"));- } else {+ //+ // Graphics initialization is unnecessary,+ // OS has present framebuffer.+ //+ } else if (BootMode != BOOT_ON_S3_RESUME) { MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); if ((MemBuffer != NULL) && (Buffer != NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
index 1c9a65399b54..3029354b96cd 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar
+++ dInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
@@ -11,7 +11,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/MemoryAllocationLib.h> #include <Library/PcdLib.h> #include <Library/PchCycleDecodingLib.h>+#include <Library/PchPmcLib.h> #include <Library/PchResetLib.h>+#include <Library/PciLib.h> #include <Library/SiliconInitLib.h> #include <Library/TimerLib.h> #include <Library/PeiLib.h>@@ -267,25 +269,31 @@ AspireVn7Dash572GBoardBootModeDetect (
VOID ) {- UINT16 ABase;+ EFI_BOOT_MODE BootMode; UINT32 SleepType; DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); - // TODO: Perform advanced detection (recovery/capsule)- // FIXME: This violates PI specification? But BOOT_WITH* would always take precedence- // over BOOT_ON_S{4,5}...- PchAcpiBaseGet (&ABase);- SleepType = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT_SLP_TYP;+ // Known sane defaults; TODO: Consider "default"?+ BootMode = BOOT_WITH_FULL_CONFIGURATION; - switch (SleepType) {- case V_PCH_ACPI_PM1_CNT_S3:- return BOOT_ON_S3_RESUME;- case V_PCH_ACPI_PM1_CNT_S4:- return BOOT_ON_S4_RESUME;-// case V_PCH_ACPI_PM1_CNT_S5:-// return BOOT_ON_S5_RESUME;- default:- return BOOT_WITH_FULL_CONFIGURATION;+ // TODO: Perform advanced detection (capsule/recovery)+ // TODO: Perform "IsFirstBoot" test with VariablePpi for "minimal"/"assume"+ if (GetSleepTypeAfterWakeup (&SleepType)) {+ switch (SleepType) {+ case V_PCH_ACPI_PM1_CNT_S3:+ BootMode = BOOT_ON_S3_RESUME;+ break;+ case V_PCH_ACPI_PM1_CNT_S4:+ BootMode = BOOT_ON_S4_RESUME;+ break;+ case V_PCH_ACPI_PM1_CNT_S5:+ BootMode = BOOT_ON_S5_RESUME;+ break;+ } }++ DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));++ return BootMode; }diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index cd9f979d313c..c53114e15450 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/Boar
+++ dInitLib/PeiBoardInitPreMemLib.inf
@@ -25,11 +25,14 @@
TimerLib PchCycleDecodingLib PchResetLib+ PciLib IoLib EcLib BoardEcLib GpioLib PeiLib+ PeiServicesLib+ PchPmcLib [Packages] MinPlatformPkg/MinPlatformPkg.decdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
index efe29c617a02..20c42a7c1c20 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg
+++ .dsc
@@ -249,6 +249,7 @@
# Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf ####################################### # Platform Package@@ -712,6 +713,26 @@
!endif } +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {+ <LibraryClasses>+ # On S3 resume, RSC is in end-of-BS state+ # - Moreover: Library cannot effectively use some end-of-BS events+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf+ # Reverse-ranked priority list+# TODO: Requires testing+# - Strongly suspect DebugLibSerialPort constructor presents PeiDxeSerialPortLibMem dependency on services as a bug+!if FALSE # $(USE_MEMORY_LOGGING) == TRUE+ SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/DxeSerialPortLibMem.inf+!endif+ # Also, can debug CpuExceptionHandlerLib+!if $(USE_HDMI_DEBUG_PORT) == TRUE+ SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPortLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf+!endif+ }+!endif+ !endif #######################################diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
index 3ed7aa0a2b10..490c3ee6bf76 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg
+++ Pcd.dsc
@@ -127,10 +127,7 @@
# PcdIpmiFeatureEnable will not be enabled (no BMC) # TODO: Can be build-time (user) choice gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable |FALSE- # TODO: Continue developing support. Broken at present.- # - PeiSmmAccessLib in IntelSiliconPkg seems like a stub- # - May require a PeiSmmControlLib to SMM communicate- gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |FALSE+ gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable |TRUE # TODO: Definitions (now added SmbiosDxe) gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable |TRUE # Requires actual hook-up@@ -335,6 +332,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|4 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 # # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags@@ -360,13 +358,8 @@
# 0x7F, 0xFF, 0x04, 0x00}<BR> gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x7F, 0xFF, 0x04, 0x00} -!if $(TARGET) == RELEASE- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x800-!else- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B # TODO-!endif- # TODO: Consider using reserved space instead for debug log- gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x200+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0x4800+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100 !if $(TARGET) == RELEASE gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 !else@@ -447,7 +440,6 @@
# Edk2 Configuration ###################################### gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 ###################################### # Platform Configurationdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
index 3764f7c3ac09..04cd2e741489 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Libra
+++ ry/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/DebugLib.h> #include <Library/ConfigBlockLib.h> #include <Library/PeiLib.h>+#include <Library/PeiServicesLib.h> #include <Library/BaseMemoryLib.h> #include <Library/MemoryAllocationLib.h> #include <Library/CpuPlatformLib.h>@@ -549,6 +550,7 @@ SiliconPolicyUpdatePostMem (
) { EFI_STATUS Status;+ EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size;@@ -557,6 +559,9 @@ SiliconPolicyUpdatePostMem (
DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); + Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);+ GtConfig = NULL; Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig); ASSERT_EFI_ERROR (Status);@@ -571,7 +576,11 @@ SiliconPolicyUpdatePostMem (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); if (Buffer == NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n"));- } else {+ //+ // Graphics initialization is unnecessary,+ // OS has present framebuffer.+ //+ } else if (BootMode != BOOT_ON_S3_RESUME) { MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); if ((MemBuffer != NULL) && (Buffer != NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
index 1ce26fc3dcec..31a45292209d 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Libra
+++ ry/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -23,6 +23,7 @@
BaseMemoryLib MemoryAllocationLib PeiLib+ PeiServicesLib CpuPlatformLib PchPcieRpLib PchInfoLibdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index dbc84631acaa..ce309bd378d2 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/
+++ PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/DebugLib.h> #include <Library/PeiLib.h> #include <Library/ConfigBlockLib.h>+#include <Library/PeiServicesLib.h> #include <FspEas.h> #include <FspmUpd.h>@@ -36,11 +37,15 @@ PeiFspMiscUpdUpdatePreMem (
) { EFI_STATUS Status;+ EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; + Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);+ // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. //@@ -75,7 +80,11 @@ PeiFspMiscUpdUpdatePreMem (
&VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));- if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {+ //+ // Do not set CleanMemory on S3 resume+ // TODO: Handle advanced features later - capsule update is in-memory list+ //+ if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) { FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK); } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index 133b8c963f65..6fd45cc79f61 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/
+++ PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h> #include <Library/PeiSaPolicyLib.h> #include <Library/PeiLib.h>+#include <Library/PeiServicesLib.h> /** Performs FSP SA PEI Policy initialization.@@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd ) {+ EFI_STATUS Status;+ EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);+ FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1; Size = 0;@@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); if (Buffer == NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n"));- } else {+ //+ // Graphics initialization is unnecessary,+ // OS has present framebuffer.+ //+ } else if (BootMode != BOOT_ON_S3_RESUME) { MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); if ((MemBuffer != NULL) && (Buffer != NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index d6c91cd2b94b..5b3a6921d0ee 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLi
+++ b/PeiBoardInitPreMemLib.inf
@@ -23,6 +23,7 @@
PcdLib SiliconInitLib PchResetLib+ PchPmcLib [Packages] MinPlatformPkg/MinPlatformPkg.decdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c
index 051dac0b204d..1cd2baf4a4dd 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLi
+++ b/PeiGalagoPro3InitPreMemLib.c
@@ -14,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/HobLib.h> #include <Library/PcdLib.h> #include <Library/PchCycleDecodingLib.h>+#include <Library/PchPmcLib.h> #include <Library/PciLib.h> #include <Library/PcdLib.h> #include <Library/BaseMemoryLib.h>@@ -236,5 +237,29 @@ GalagoPro3BoardBootModeDetect (
VOID ) {- return BOOT_WITH_FULL_CONFIGURATION;+ EFI_BOOT_MODE BootMode;+ UINT32 SleepType;++ DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));++ // Known sane defaults+ BootMode = BOOT_WITH_FULL_CONFIGURATION;++ if (GetSleepTypeAfterWakeup (&SleepType)) {+ switch (SleepType) {+ case V_PCH_ACPI_PM1_CNT_S3:+ BootMode = BOOT_ON_S3_RESUME;+ break;+ case V_PCH_ACPI_PM1_CNT_S4:+ BootMode = BOOT_ON_S4_RESUME;+ break;+ case V_PCH_ACPI_PM1_CNT_S5:+ BootMode = BOOT_ON_S5_RESUME;+ break;+ }+ }++ DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));++ return BootMode; }diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index fe31f421356e..20ddac1d994d 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLi
+++ b/PeiMultiBoardInitPreMemLib.inf
@@ -25,6 +25,7 @@
SiliconInitLib MultiBoardInitSupportLib PchResetLib+ PchPmcLib [Packages] MinPlatformPkg/MinPlatformPkg.decdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
index f0e9a21ccad9..219ef20e55f0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc
@@ -180,6 +180,7 @@
# Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf ####################################### # Platform Package@@ -494,6 +495,20 @@
!endif } +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {+ <LibraryClasses>+ # On S3 resume, RSC is in end-of-BS state+ # - Moreover: Libraries cannot effectively use some end-of-BS events+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf+ # Reverse-ranked priority list+!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdI2cHdmiDebugPortEnable == TRUE+ SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPortLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf+!endif+ }+!endif+ !endif #######################################diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
index 8180312f5ca5..7a73f5a831c6 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc
@@ -279,6 +279,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 # # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags@@ -380,7 +381,6 @@
###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 ###################################### # Platform Configurationdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
index 699f4297fad6..71b03f2da464 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Librar
+++ y/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
@@ -11,11 +11,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/DebugLib.h> #include <Library/PeiLib.h> #include <Library/ConfigBlockLib.h>+#include <Library/PeiServicesLib.h> #include <FspEas.h> #include <FspmUpd.h> #include <FspsUpd.h>- #include <Library/DebugLib.h> #include <Library/DebugPrintErrorLevelLib.h> #include <Library/PciLib.h>@@ -36,11 +36,15 @@ PeiFspMiscUpdUpdatePreMem (
) { EFI_STATUS Status;+ EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; + Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);+ // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and fast boot paths. //@@ -73,7 +77,11 @@ PeiFspMiscUpdUpdatePreMem (
&VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status));- if (MOR_CLEAR_MEMORY_VALUE (MorControl)) {+ //+ // Do not set CleanMemory on S3 resume+ // TODO: Handle advanced features later - capsule update is in-memory list+ //+ if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode != BOOT_ON_S3_RESUME) { FspmUpd->FspmConfig.CleanMemory = (BOOLEAN)(MorControl & MOR_CLEAR_MEMORY_BIT_MASK); } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
index d6ec3e38dd7e..e855207af0d1 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Librar
+++ y/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
@@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h> #include <Library/PeiSaPolicyLib.h> #include <Library/PeiLib.h>+#include <Library/PeiServicesLib.h> /** Performs FSP SA PEI Policy initialization.@@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate (
IN OUT FSPS_UPD *FspsUpd ) {+ EFI_STATUS Status;+ EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);+ FspsUpd->FspsConfig.PeiGraphicsPeimInit = 1; Size = 0;@@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); if (Buffer == NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n"));- } else {+ //+ // Graphics initialization is unnecessary,+ // OS has present framebuffer.+ //+ } else if (BootMode != BOOT_ON_S3_RESUME) { MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); if ((MemBuffer != NULL) && (Buffer != NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
index 850fc514188b..e0022e8d6118 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInit
+++ Lib/PeiBoardInitPreMemLib.inf
@@ -24,6 +24,7 @@
SiliconInitLib EcLib PchResetLib+ PchPmcLib [Packages] MinPlatformPkg/MinPlatformPkg.decdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c
index 87ae3b531ed6..02cd37227e50 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInit
+++ Lib/PeiKabylakeRvp3InitPreMemLib.c
@@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/HobLib.h> #include <Library/PcdLib.h> #include <Library/PchCycleDecodingLib.h>+#include <Library/PchPmcLib.h> #include <Library/PciLib.h> #include <Library/PcdLib.h> #include <Library/BaseMemoryLib.h>@@ -330,5 +331,29 @@ KabylakeRvp3BoardBootModeDetect (
VOID ) {- return BOOT_WITH_FULL_CONFIGURATION;+ EFI_BOOT_MODE BootMode;+ UINT32 SleepType;++ DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));++ // Known sane defaults+ BootMode = BOOT_WITH_FULL_CONFIGURATION;++ if (GetSleepTypeAfterWakeup (&SleepType)) {+ switch (SleepType) {+ case V_PCH_ACPI_PM1_CNT_S3:+ BootMode = BOOT_ON_S3_RESUME;+ break;+ case V_PCH_ACPI_PM1_CNT_S4:+ BootMode = BOOT_ON_S4_RESUME;+ break;+ case V_PCH_ACPI_PM1_CNT_S5:+ BootMode = BOOT_ON_S5_RESUME;+ break;+ }+ }++ DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode));++ return BootMode; }diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
index 23fe6b6f03c5..0112bf84a193 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInit
+++ Lib/PeiMultiBoardInitPreMemLib.inf
@@ -26,6 +26,7 @@
MultiBoardInitSupportLib EcLib PchResetLib+ PchPmcLib [Packages] MinPlatformPkg/MinPlatformPkg.decdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
index 37837eeb04bf..1634d9b31f00 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc
@@ -202,6 +202,7 @@
# Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.inf+ SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSmramc/PeiSmmAccessLib.inf ####################################### # Platform Package@@ -506,6 +507,17 @@
!endif } +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable == TRUE+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {+ <LibraryClasses>+ # On S3 resume, RSC is in end-of-BS state+ # - Moreover: Libraries cannot effectively use some end-of-BS events+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf+ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull.inf+ # TODO: Insert a reverse-ranked priority list of compatible libraries here+ }+!endif+ !endif #######################################diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
index cfd032814850..87510748783f 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d
+++ sc
@@ -279,6 +279,7 @@
gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 # # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags@@ -349,7 +350,6 @@
###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148- gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 ###################################### # Platform Configurationdiff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
index 22aadc0221df..bd3da7f38416 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/Pe
+++ iSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
@@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/DebugLib.h> #include <Library/ConfigBlockLib.h> #include <Library/PeiLib.h>+#include <Library/PeiServicesLib.h> #include <Library/BaseMemoryLib.h> #include <Library/MemoryAllocationLib.h> #include <Library/CpuPlatformLib.h>@@ -513,6 +514,7 @@ SiliconPolicyUpdatePostMem (
) { EFI_STATUS Status;+ EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size;@@ -521,6 +523,9 @@ SiliconPolicyUpdatePostMem (
DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); + Status = PeiServicesGetBootMode (&BootMode);+ ASSERT_EFI_ERROR (Status);+ GtConfig = NULL; Status = GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VOID *)&GtConfig); ASSERT_EFI_ERROR (Status);@@ -535,7 +540,11 @@ SiliconPolicyUpdatePostMem (
PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RAW, 0, &Buffer, &Size); if (Buffer == NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n"));- } else {+ //+ // Graphics initialization is unnecessary,+ // OS has present framebuffer.+ //+ } else if (BootMode != BOOT_ON_S3_RESUME) { MemBuffer = (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); if ((MemBuffer != NULL) && (Buffer != NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size);diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
index 25eae88f5989..e9a23593e133 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/Pe
+++ iSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
@@ -23,6 +23,7 @@
BaseMemoryLib MemoryAllocationLib PeiLib+ PeiServicesLib CpuPlatformLib PchPcieRpLib PchInfoLib--
2.37.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms][PATCH v3 3/4] MinPlatformPkg: Implement working S3 resume
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 3/4] MinPlatformPkg: " Benjamin Doron
@ 2022-09-13 1:00 ` Isaac Oram
0 siblings, 0 replies; 11+ messages in thread
From: Isaac Oram @ 2022-09-13 1:00 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Chiu, Chasel, Desimone, Nathaniel L, Sinha, Ankit, Gao, Liming,
Dong, Eric
Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Monday, September 12, 2022 10:13 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>
Subject: [edk2-platforms][PATCH v3 3/4] MinPlatformPkg: Implement working S3 resume
Consume S3 resume memory allocation on resume flow.
Also, include complementary FirmwarePerformanceDataTablePei module in MinPlatform FV for S3 resume performance measurement.
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
---
.../FspWrapperHobProcessLib.c | 69 ++++++++++++++++++-
.../PeiFspWrapperHobProcessLib.inf | 2 +
.../Include/Dsc/CorePeiInclude.dsc | 2 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 4 ++
4 files changed, 76 insertions(+), 1 deletion(-)
diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
index 7ee4d3a31c49..9bd6fe6290c5 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/FspWrapperHobProcessLib.c
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobP
+++ rocessLib/FspWrapperHobProcessLib.c
@@ -16,14 +16,17 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/HobLib.h> #include <Library/PcdLib.h> #include <Library/FspWrapperPlatformLib.h>+#include <Guid/AcpiS3Context.h> #include <Guid/GuidHobFspEas.h> #include <Guid/MemoryTypeInformation.h> #include <Guid/GraphicsInfoHob.h> #include <Guid/PcdDataBaseHobGuid.h> #include <Guid/ZeroGuid.h> #include <Ppi/Capsule.h>+#include <Ppi/ReadOnlyVariable2.h> #include <FspEas.h>+#include <AcpiS3MemoryNvData.h> // // Additional pages are used by DXE memory manager.@@ -130,6 +133,55 @@ GetPeiMemSize (
return MinSize + Size + PEI_ADDITIONAL_MEMORY_SIZE; } +/**+ Get S3 PEI memory information.++ @note At this point, memory is ready, and PeiServices are available to use.+ Platform can get some data from SMRAM directly.++ @param[out] S3PeiMemSize PEI memory size to be installed in S3 phase.+ @param[out] S3PeiMemBase PEI memory base to be installed in S3 phase.++ @return If S3 PEI memory information is got successfully.+**/+EFI_STATUS+EFIAPI+GetS3MemoryInfo (+ OUT UINT64 *S3PeiMemSize,+ OUT EFI_PHYSICAL_ADDRESS *S3PeiMemBase+ )+{+ EFI_STATUS Status;+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;+ UINTN DataSize;+ ACPI_S3_MEMORY S3MemoryInfo;++ *S3PeiMemBase = 0;+ *S3PeiMemSize = 0;++ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, (VOID **) &VariablePpi);+ ASSERT_EFI_ERROR (Status);++ DataSize = sizeof (S3MemoryInfo);+ Status = VariablePpi->GetVariable (+ VariablePpi,+ ACPI_S3_MEMORY_NV_NAME,+ &gEfiAcpiVariableGuid,+ NULL,+ &DataSize,+ &S3MemoryInfo+ );+ ASSERT_EFI_ERROR (Status);++ if (EFI_ERROR (Status)) {+ return Status;+ }++ *S3PeiMemBase = S3MemoryInfo.S3PeiMemBase;+ *S3PeiMemSize = S3MemoryInfo.S3PeiMemSize;+ return EFI_SUCCESS;+}+ /** Post FSP-M HOB process for Memory Resource Descriptor. @@ -280,7 +332,7 @@ PostFspmHobProcess (
0x1000 ); -+ if (BootMode != BOOT_ON_S3_RESUME) { // // Capsule mode //@@ -337,7 +389,22 @@ PostFspmHobProcess (
if (Capsule != NULL) { Status = Capsule->CreateState ((EFI_PEI_SERVICES **)PeiServices, CapsuleBuffer, CapsuleBufferLength); }+ } else {+ Status = GetS3MemoryInfo (&PeiMemSize, &PeiMemBase);+ ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "S3 resume PeiMemBase : 0x%08x\n", PeiMemBase));+ DEBUG ((DEBUG_INFO, "S3 resume PeiMemSize : 0x%08x\n", PeiMemSize));++ //+ // Install efi memory+ //+ Status = PeiServicesInstallPeiMemory (+ PeiMemBase,+ PeiMemSize+ );+ ASSERT_EFI_ERROR (Status);+ } // // Create a memory allocation HOB at fixed location for MP Services PPI AP wait loop.diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
index b846e7af1d2d..e2aac36bf018 100644
--- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/PeiFspWrapperHobP
+++ rocessLib/PeiFspWrapperHobProcessLib.inf
@@ -75,7 +75,9 @@
gZeroGuid gEfiGraphicsInfoHobGuid gEfiGraphicsDeviceInfoHobGuid+ gEfiAcpiVariableGuid [Ppis] gEfiPeiCapsulePpiGuid ## CONSUMES+ gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES gEdkiiSiliconInitializedPpiGuid ## PRODUCESdiff --git a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
index 08e50cac075f..f271fb26b189 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+++ b/Platform/Intel/MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
@@ -41,3 +41,5 @@
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256.inf } !endif++ MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.infdiff --git a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
index 3c2716d6728a..3edc239e5264 100644
--- a/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fdf
+++ b/Platform/Intel/MinPlatformPkg/Include/Fdf/CorePostMemoryInclude.fd
+++ f
@@ -6,3 +6,7 @@
# SPDX-License-Identifier: BSD-2-Clause-Patent # ##++!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE+ INF MdeModulePkg/Universal/Acpi/FirmwarePerformanceDataTablePei/FirmwarePerformancePei.inf+!endif--
2.37.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [edk2-platforms][PATCH v3 0/4] Implement S3 resume
2022-09-12 17:12 [edk2-platforms][PATCH v3 0/4] Implement S3 resume Benjamin Doron
` (3 preceding siblings ...)
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 4/4] KabylakeOpenBoardPkg: Example of board S3 Benjamin Doron
@ 2022-10-12 1:31 ` Isaac Oram
[not found] ` <171D2E406AE360FA.17458@groups.io>
5 siblings, 0 replies; 11+ messages in thread
From: Isaac Oram @ 2022-10-12 1:31 UTC (permalink / raw)
To: Benjamin Doron, devel@edk2.groups.io
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Sinha, Ankit,
Chiu, Chasel, Gao, Liming, Dong, Eric, Soller, Jeremy
Series Reviewed-by: Isaac Oram <Isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Monday, September 12, 2022 10:13 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>; Soller, Jeremy <jeremy@system76.com>
Subject: [edk2-platforms][PATCH v3 0/4] Implement S3 resume
MinPlatform is an open-source EDK2 firmware project that can boot some mainstream boards. However, it lacked working support for S3 resume, an important feature for mobile platforms, which means that its applicability as-is to mainstream use is limited. Therefore, I have now implemented working S3 resume support on MinPlatform. This patch series comprises a majority of one of my work products for GSoC 2022.
The BootScript-related modules are EDK2 open-source and fairly straightforward to include. However, the partial dependency PiSmmCommunicationPei (for signalling SMM) creates a dependency on both the SmmAccess and SmmControl PPIs, so these are implemented here as libraries, ported from the DXE drivers. As the register definitions are generic, one library shim is implemented for compatibility, so the library can be generic too. SmmAccess shall be required regardless of SMM signalling, for the LockBox.
Like all boots, S3 resume will require working DRAM. To my understanding, we do not need to parse the memory map HOBs again, so some memory is allocated in DXE phase (to reserve it), the address stashed in a variable and consumed on S3 resume flows. Some optimisation can be performed here, regarding how much is necessary.
Stashing in a variable is imperfect, but the details must be available without DRAM. As the FSP HOBs are published later, SmmAccess cannot be used to retrieve from the LockBox.
Per my suspicions, notes from my mentors, Nate and Ankit, and the coreboot code, the PAMs are opened for access to the AP wake vectors.
Presently, all are opened, more research can be performed here.
As noted, either FSP or PiSmmCpuDxeSmm can apply boot CPU structures (GDT, IDT, MTRRs, etc). Per my research and findings by my mentors, the closed-source module CpuInitDxe would be required, so this implementation includes CpuS3DataDxe and open-source code will perform this task instead.
Unfortunately, board-specific code has some tasks to perform too. I've implemented these for Kabylake, the platform I can test. This includes detecting the boot mode, policy (memory overwrite is contraindicated, do not pass a VBT so FSP does not initialise graphics again) and ensuring a special provision, if desired, for debugging BootScriptExecutorDxe.
One major bug that blocked progress was simply specific to debugging.
DebugLibReportStatusCode should not be used for that module, because RSC has uninstalled the serial port handler at end-of-BS. Furthermore, it's obvious that the boot services are now unavailable. So, DebugLibSerialPort should be used. As an aside, due to AutoGen ordering, gBS cannot be used in SerialPortInitialize(). What really makes this module a unique case is the fact that it's behaviour is very like runtime drivers. For the integrity of the platform's security, the module is copied to the LockBox at DxeSmmReadyToLock. This caused one major bug that was blocking progress: libraries cannot attempt to modify globals (the data section) with end-of-BS events; they will never reach the true copy. So, rather than using flags to control code flow, it must be coded this way instead. For instance, there is now a special variant of I2cHdmiDebugSerialPortLib that does not use gBS in SerialPortWrite().
Previous revisions of this patch-set tested on my Aspire VN7-572G (Skylake). It's my belief and intention that this implementation be ready for other platforms too (some Intel-specific assumptions made), with a minimum of porting effort, though readying for some debugging is recommended.
Some potential bugs include:
- Power failure is being set (PMC PWR_FLR), so BootMode == 0x0. This bit
is RW/1C, so mitigate it. Until finalised and I close the laptop
chassis, I don't know if this is a bug in Kabylake's PchPmcLib.
- Very early in testing I saw a memory init error, which means that
self-refresh failed. A BaseMemoryTest() predictably failed too,
inserted before the PEI core installs memory. Either this was fixed
in the code as I finished the implementation, or it's a bug. A major
difference in build options is SerialPortSpiFlash ->
I2cHdmiDebugSerialPortLib, but this seemed irrelevant. If it's simply
the finalised implementation, I think this isn't worth a diff against
the reflog.
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Benjamin Doron (4):
MinPlatformPkg: Add SmmLockBox to build
S3FeaturePkg: Implement working S3 resume
MinPlatformPkg: Implement working S3 resume
KabylakeOpenBoardPkg: Example of board S3
.../S3FeaturePkg/Include/PostMemory.fdf | 12 ++
.../S3FeaturePkg/Include/PreMemory.fdf | 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc | 36 +++-
.../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++
.../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++
.../S3FeaturePkg/S3FeaturePkg.dsc | 3 +
.../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++-
.../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../PeiAspireVn7Dash572GInitPreMemLib.c | 38 +++--
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 +
.../AspireVn7Dash572G/OpenBoardPkg.dsc | 21 +++
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 16 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../PeiFspMiscUpdUpdateLib.c | 11 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 ++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../GalagoPro3/OpenBoardPkg.dsc | 15 ++
.../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../PeiKabylakeRvp3InitPreMemLib.c | 27 ++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../KabylakeRvp3/OpenBoardPkg.dsc | 12 ++
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../FspWrapperHobProcessLib.c | 69 +++++++-
.../PeiFspWrapperHobProcessLib.inf | 2 +
.../Include/AcpiS3MemoryNvData.h | 22 +++
.../Include/Dsc/CoreDxeInclude.dsc | 1 +
.../Include/Dsc/CorePeiInclude.dsc | 2 +
.../Include/Fdf/CoreOsBootInclude.fdf | 1 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 4 +
39 files changed, 665 insertions(+), 52 deletions(-) create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
--
2.37.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [edk2-devel] [edk2-platforms][PATCH v3 0/4] Implement S3 resume
[not found] ` <171D2E406AE360FA.17458@groups.io>
@ 2022-10-12 1:32 ` Isaac Oram
0 siblings, 0 replies; 11+ messages in thread
From: Isaac Oram @ 2022-10-12 1:32 UTC (permalink / raw)
To: devel@edk2.groups.io, Oram, Isaac W, Benjamin Doron
Cc: Chaganty, Rangasai V, Desimone, Nathaniel L, Sinha, Ankit,
Chiu, Chasel, Gao, Liming, Dong, Eric, Soller, Jeremy
Pushed as ee8d078e39..4d99e03828
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Isaac Oram
Sent: Tuesday, October 11, 2022 6:31 PM
To: Benjamin Doron <benjamin.doron00@gmail.com>; devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>; Soller, Jeremy <jeremy@system76.com>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v3 0/4] Implement S3 resume
Series Reviewed-by: Isaac Oram <Isaac.w.oram@intel.com>
-----Original Message-----
From: Benjamin Doron <benjamin.doron00@gmail.com>
Sent: Monday, September 12, 2022 10:13 AM
To: devel@edk2.groups.io
Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Dong, Eric <eric.dong@intel.com>; Soller, Jeremy <jeremy@system76.com>
Subject: [edk2-platforms][PATCH v3 0/4] Implement S3 resume
MinPlatform is an open-source EDK2 firmware project that can boot some mainstream boards. However, it lacked working support for S3 resume, an important feature for mobile platforms, which means that its applicability as-is to mainstream use is limited. Therefore, I have now implemented working S3 resume support on MinPlatform. This patch series comprises a majority of one of my work products for GSoC 2022.
The BootScript-related modules are EDK2 open-source and fairly straightforward to include. However, the partial dependency PiSmmCommunicationPei (for signalling SMM) creates a dependency on both the SmmAccess and SmmControl PPIs, so these are implemented here as libraries, ported from the DXE drivers. As the register definitions are generic, one library shim is implemented for compatibility, so the library can be generic too. SmmAccess shall be required regardless of SMM signalling, for the LockBox.
Like all boots, S3 resume will require working DRAM. To my understanding, we do not need to parse the memory map HOBs again, so some memory is allocated in DXE phase (to reserve it), the address stashed in a variable and consumed on S3 resume flows. Some optimisation can be performed here, regarding how much is necessary.
Stashing in a variable is imperfect, but the details must be available without DRAM. As the FSP HOBs are published later, SmmAccess cannot be used to retrieve from the LockBox.
Per my suspicions, notes from my mentors, Nate and Ankit, and the coreboot code, the PAMs are opened for access to the AP wake vectors.
Presently, all are opened, more research can be performed here.
As noted, either FSP or PiSmmCpuDxeSmm can apply boot CPU structures (GDT, IDT, MTRRs, etc). Per my research and findings by my mentors, the closed-source module CpuInitDxe would be required, so this implementation includes CpuS3DataDxe and open-source code will perform this task instead.
Unfortunately, board-specific code has some tasks to perform too. I've implemented these for Kabylake, the platform I can test. This includes detecting the boot mode, policy (memory overwrite is contraindicated, do not pass a VBT so FSP does not initialise graphics again) and ensuring a special provision, if desired, for debugging BootScriptExecutorDxe.
One major bug that blocked progress was simply specific to debugging.
DebugLibReportStatusCode should not be used for that module, because RSC has uninstalled the serial port handler at end-of-BS. Furthermore, it's obvious that the boot services are now unavailable. So, DebugLibSerialPort should be used. As an aside, due to AutoGen ordering, gBS cannot be used in SerialPortInitialize(). What really makes this module a unique case is the fact that it's behaviour is very like runtime drivers. For the integrity of the platform's security, the module is copied to the LockBox at DxeSmmReadyToLock. This caused one major bug that was blocking progress: libraries cannot attempt to modify globals (the data section) with end-of-BS events; they will never reach the true copy. So, rather than using flags to control code flow, it must be coded this way instead. For instance, there is now a special variant of I2cHdmiDebugSerialPortLib that does not use gBS in SerialPortWrite().
Previous revisions of this patch-set tested on my Aspire VN7-572G (Skylake). It's my belief and intention that this implementation be ready for other platforms too (some Intel-specific assumptions made), with a minimum of porting effort, though readying for some debugging is recommended.
Some potential bugs include:
- Power failure is being set (PMC PWR_FLR), so BootMode == 0x0. This bit
is RW/1C, so mitigate it. Until finalised and I close the laptop
chassis, I don't know if this is a bug in Kabylake's PchPmcLib.
- Very early in testing I saw a memory init error, which means that
self-refresh failed. A BaseMemoryTest() predictably failed too,
inserted before the PEI core installs memory. Either this was fixed
in the code as I finished the implementation, or it's a bug. A major
difference in build options is SerialPortSpiFlash ->
I2cHdmiDebugSerialPortLib, but this seemed irrelevant. If it's simply
the finalised implementation, I think this isn't worth a diff against
the reflog.
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Ankit Sinha <ankit.sinha@intel.com>
Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Benjamin Doron (4):
MinPlatformPkg: Add SmmLockBox to build
S3FeaturePkg: Implement working S3 resume
MinPlatformPkg: Implement working S3 resume
KabylakeOpenBoardPkg: Example of board S3
.../S3FeaturePkg/Include/PostMemory.fdf | 12 ++
.../S3FeaturePkg/Include/PreMemory.fdf | 8 +-
.../S3FeaturePkg/Include/S3Feature.dsc | 36 +++-
.../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++
.../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++
.../S3FeaturePkg/S3FeaturePkg.dsc | 3 +
.../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++-
.../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../PeiAspireVn7Dash572GInitPreMemLib.c | 38 +++--
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 +
.../AspireVn7Dash572G/OpenBoardPkg.dsc | 21 +++
.../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 16 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../PeiFspMiscUpdUpdateLib.c | 11 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 ++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../GalagoPro3/OpenBoardPkg.dsc | 15 ++
.../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiFspMiscUpdUpdateLib.c | 12 +-
.../PeiSaPolicyUpdate.c | 12 +-
.../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 +
.../PeiKabylakeRvp3InitPreMemLib.c | 27 ++-
.../PeiMultiBoardInitPreMemLib.inf | 1 +
.../KabylakeRvp3/OpenBoardPkg.dsc | 12 ++
.../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +-
.../PeiSiliconPolicyUpdateLib.c | 11 +-
.../PeiSiliconPolicyUpdateLib.inf | 1 +
.../FspWrapperHobProcessLib.c | 69 +++++++-
.../PeiFspWrapperHobProcessLib.inf | 2 +
.../Include/AcpiS3MemoryNvData.h | 22 +++
.../Include/Dsc/CoreDxeInclude.dsc | 1 +
.../Include/Dsc/CorePeiInclude.dsc | 2 +
.../Include/Fdf/CoreOsBootInclude.fdf | 1 +
.../Include/Fdf/CorePostMemoryInclude.fdf | 4 +
39 files changed, 665 insertions(+), 52 deletions(-) create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c
create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf
create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h
--
2.37.2
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-10-12 1:32 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2022-09-12 17:12 [edk2-platforms][PATCH v3 0/4] Implement S3 resume Benjamin Doron
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 1/4] MinPlatformPkg: Add SmmLockBox to build Benjamin Doron
2022-09-12 23:31 ` Isaac Oram
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 2/4] S3FeaturePkg: Implement working S3 resume Benjamin Doron
2022-09-12 23:31 ` Isaac Oram
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 3/4] MinPlatformPkg: " Benjamin Doron
2022-09-13 1:00 ` Isaac Oram
2022-09-12 17:12 ` [edk2-platforms][PATCH v3 4/4] KabylakeOpenBoardPkg: Example of board S3 Benjamin Doron
2022-09-12 23:32 ` Isaac Oram
2022-10-12 1:31 ` [edk2-platforms][PATCH v3 0/4] Implement S3 resume Isaac Oram
[not found] ` <171D2E406AE360FA.17458@groups.io>
2022-10-12 1:32 ` [edk2-devel] " Isaac Oram
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox