From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qt1-f176.google.com (mail-qt1-f176.google.com [209.85.160.176]) by mx.groups.io with SMTP id smtpd.web10.1225.1663002823569858575 for ; Mon, 12 Sep 2022 10:13:43 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20210112 header.b=WaltrcDT; spf=pass (domain: gmail.com, ip: 209.85.160.176, mailfrom: benjamin.doron00@gmail.com) Received: by mail-qt1-f176.google.com with SMTP id y2so6712304qtv.5 for ; Mon, 12 Sep 2022 10:13:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=8mMFxNWvzb9fjnLiGrp9KCTzgqboPEzPy2uKY1RmM8s=; b=WaltrcDTCYn6P5TrGL2bhM7Sl5rN2thJTXxcoNHm3vQ4ZIYGAZdExpHooTI3g+rZ0v efU1Ryfr13E2i6uJzb8mcrPU3L8cY1OG/QIdA2WgvGaYTrCjMX2Q9mG0yt/s1AOfxUQt h4WI5wz3wZc5qT1SP3HDlYIf1sqaAxBCd1/lzAjGOKnSEBUHxX6XvS9+6VOV0Hz8UlTg 39pi8n2GmGMSvl1yXUyLGdCZPd83R/6cSBc36ZfdGxUWY532lb/WM9rYCYZZKgSOLQ+b u2VwRH8giFxtIi78qSEx2R24a2NZ8+o8SeFVWyUsppn8dvj2HZAh7A7nodvovXpa0WAB 8cOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=8mMFxNWvzb9fjnLiGrp9KCTzgqboPEzPy2uKY1RmM8s=; b=FIYQh06cGdqZUDxo0zLYZ+BNTn+aFqnhOyt/iOwIurUSt3l9Lsa0XLAx4BVObh0Api bevLEICyuQ4eJ/SWZfGd4winweQXgLjbHgMzKs0LQESvqfbV/DrETGSFfNg/YNGtWawH H37xnIpIbkJz+gKnGMSYZjDfPkMihXaL9ffCIm/jRpSwzPJIvxvrerAel3VL/LXQYcTI vjeuza1BovK2eF1o2X/tIYwsmGCCWl2FhnHVRMDlci80afgGfpoKyxVk14s+Yd03jHPI F6ZQ4rAMJyrbs9Z9jryKUsa1m3fzHRznxUjkqI5gzM+EKSfxu9lS4gCPApQ5Duoka1/p VQPQ== X-Gm-Message-State: ACgBeo15vg+CpB/8qOaYad32mC/gjbybhmnHpAHURr4goKijxRR3ophi 0Amx0YE7CkvI5R3Zot8exl82p2aWwQI= X-Google-Smtp-Source: AA6agR5SKuzk7mmZ648qsB3T92WDCcsXbajM/nWBiBgQe3s1qy8wNJZTM8oLFQtFxMsB/DtnYni1wQ== X-Received: by 2002:a05:622a:134a:b0:35b:b5fa:5e12 with SMTP id w10-20020a05622a134a00b0035bb5fa5e12mr4170615qtk.48.1663002822351; Mon, 12 Sep 2022 10:13:42 -0700 (PDT) Return-Path: Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:579e:d875:fc8f:d092]) by smtp.gmail.com with ESMTPSA id s5-20020ac87585000000b00346414a0ca1sm6863540qtq.1.2022.09.12.10.13.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Sep 2022 10:13:41 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Sai Chaganty , Isaac Oram , Nate DeSimone , Ankit Sinha , Chasel Chiu , Liming Gao , Eric Dong , Jeremy Soller Subject: [edk2-platforms][PATCH v3 0/4] Implement S3 resume Date: Mon, 12 Sep 2022 13:12:46 -0400 Message-Id: <20220912171250.1515536-1-benjamin.doron00@gmail.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit MinPlatform is an open-source EDK2 firmware project that can boot some mainstream boards. However, it lacked working support for S3 resume, an important feature for mobile platforms, which means that its applicability as-is to mainstream use is limited. Therefore, I have now implemented working S3 resume support on MinPlatform. This patch series comprises a majority of one of my work products for GSoC 2022. The BootScript-related modules are EDK2 open-source and fairly straightforward to include. However, the partial dependency PiSmmCommunicationPei (for signalling SMM) creates a dependency on both the SmmAccess and SmmControl PPIs, so these are implemented here as libraries, ported from the DXE drivers. As the register definitions are generic, one library shim is implemented for compatibility, so the library can be generic too. SmmAccess shall be required regardless of SMM signalling, for the LockBox. Like all boots, S3 resume will require working DRAM. To my understanding, we do not need to parse the memory map HOBs again, so some memory is allocated in DXE phase (to reserve it), the address stashed in a variable and consumed on S3 resume flows. Some optimisation can be performed here, regarding how much is necessary. Stashing in a variable is imperfect, but the details must be available without DRAM. As the FSP HOBs are published later, SmmAccess cannot be used to retrieve from the LockBox. Per my suspicions, notes from my mentors, Nate and Ankit, and the coreboot code, the PAMs are opened for access to the AP wake vectors. Presently, all are opened, more research can be performed here. As noted, either FSP or PiSmmCpuDxeSmm can apply boot CPU structures (GDT, IDT, MTRRs, etc). Per my research and findings by my mentors, the closed-source module CpuInitDxe would be required, so this implementation includes CpuS3DataDxe and open-source code will perform this task instead. Unfortunately, board-specific code has some tasks to perform too. I've implemented these for Kabylake, the platform I can test. This includes detecting the boot mode, policy (memory overwrite is contraindicated, do not pass a VBT so FSP does not initialise graphics again) and ensuring a special provision, if desired, for debugging BootScriptExecutorDxe. One major bug that blocked progress was simply specific to debugging. DebugLibReportStatusCode should not be used for that module, because RSC has uninstalled the serial port handler at end-of-BS. Furthermore, it's obvious that the boot services are now unavailable. So, DebugLibSerialPort should be used. As an aside, due to AutoGen ordering, gBS cannot be used in SerialPortInitialize(). What really makes this module a unique case is the fact that it's behaviour is very like runtime drivers. For the integrity of the platform's security, the module is copied to the LockBox at DxeSmmReadyToLock. This caused one major bug that was blocking progress: libraries cannot attempt to modify globals (the data section) with end-of-BS events; they will never reach the true copy. So, rather than using flags to control code flow, it must be coded this way instead. For instance, there is now a special variant of I2cHdmiDebugSerialPortLib that does not use gBS in SerialPortWrite(). Previous revisions of this patch-set tested on my Aspire VN7-572G (Skylake). It's my belief and intention that this implementation be ready for other platforms too (some Intel-specific assumptions made), with a minimum of porting effort, though readying for some debugging is recommended. Some potential bugs include: - Power failure is being set (PMC PWR_FLR), so BootMode == 0x0. This bit is RW/1C, so mitigate it. Until finalised and I close the laptop chassis, I don't know if this is a bug in Kabylake's PchPmcLib. - Very early in testing I saw a memory init error, which means that self-refresh failed. A BaseMemoryTest() predictably failed too, inserted before the PEI core installs memory. Either this was fixed in the code as I finished the implementation, or it's a bug. A major difference in build options is SerialPortSpiFlash -> I2cHdmiDebugSerialPortLib, but this seemed irrelevant. If it's simply the finalised implementation, I think this isn't worth a diff against the reflog. Cc: Sai Chaganty Cc: Isaac Oram Cc: Nate DeSimone Cc: Ankit Sinha Cc: Chasel Chiu Cc: Liming Gao Cc: Eric Dong Cc: Jeremy Soller Signed-off-by: Benjamin Doron Benjamin Doron (4): MinPlatformPkg: Add SmmLockBox to build S3FeaturePkg: Implement working S3 resume MinPlatformPkg: Implement working S3 resume KabylakeOpenBoardPkg: Example of board S3 .../S3FeaturePkg/Include/PostMemory.fdf | 12 ++ .../S3FeaturePkg/Include/PreMemory.fdf | 8 +- .../S3FeaturePkg/Include/S3Feature.dsc | 36 +++- .../S3FeaturePkg/S3Dxe/S3Dxe.c | 155 ++++++++++++++++++ .../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++ .../S3FeaturePkg/S3FeaturePkg.dsc | 3 + .../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++- .../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +- .../PeiFspMiscUpdUpdateLib.c | 12 +- .../PeiSaPolicyUpdate.c | 12 +- .../PeiAspireVn7Dash572GInitPreMemLib.c | 38 +++-- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 + .../AspireVn7Dash572G/OpenBoardPkg.dsc | 21 +++ .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 16 +- .../PeiSiliconPolicyUpdateLib.c | 11 +- .../PeiSiliconPolicyUpdateLib.inf | 1 + .../PeiFspMiscUpdUpdateLib.c | 11 +- .../PeiSaPolicyUpdate.c | 12 +- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 + .../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 ++- .../PeiMultiBoardInitPreMemLib.inf | 1 + .../GalagoPro3/OpenBoardPkg.dsc | 15 ++ .../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +- .../PeiFspMiscUpdUpdateLib.c | 12 +- .../PeiSaPolicyUpdate.c | 12 +- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 + .../PeiKabylakeRvp3InitPreMemLib.c | 27 ++- .../PeiMultiBoardInitPreMemLib.inf | 1 + .../KabylakeRvp3/OpenBoardPkg.dsc | 12 ++ .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +- .../PeiSiliconPolicyUpdateLib.c | 11 +- .../PeiSiliconPolicyUpdateLib.inf | 1 + .../FspWrapperHobProcessLib.c | 69 +++++++- .../PeiFspWrapperHobProcessLib.inf | 2 + .../Include/AcpiS3MemoryNvData.h | 22 +++ .../Include/Dsc/CoreDxeInclude.dsc | 1 + .../Include/Dsc/CorePeiInclude.dsc | 2 + .../Include/Fdf/CoreOsBootInclude.fdf | 1 + .../Include/Fdf/CorePostMemoryInclude.fdf | 4 + 39 files changed, 665 insertions(+), 52 deletions(-) create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h -- 2.37.2