From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web12.4298.1663148422122567689 for ; Wed, 14 Sep 2022 02:40:23 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from code-server.gen (unknown [10.2.9.245]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Bx32uDoSFj4gAZAA--.25565S2; Wed, 14 Sep 2022 17:40:19 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Bob Feng , Liming Gao , Yuwei Chen , Dongyan Qian , Baoqi Zhang , Yang Zhou , Xiaotian Wu Subject: [PATCH v2 15/34] BaseTools: BaseTools changes for LoongArch platform. Date: Wed, 14 Sep 2022 17:40:19 +0800 Message-Id: <20220914094019.3696219-1-lichao@loongson.cn> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Bx32uDoSFj4gAZAA--.25565S2 X-Coremail-Antispam: 1UD129KBjvAXoWfCw18CF43XryDKF1xCF1Dtrb_yoW5uryrJo W7Ja48G3WkCa1I9FZrG347WFsrCFy5K3WfGrn8J3Z5JFWxKFs8CFWDAryxZw4rJrW0qan8 W34q9ayDAFy3KryUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYe7AC8VAFwI0_Gr0_Xr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVW5JVW7JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8 Jr0_Cr1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxV W0oVCq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv 7VC0I7IYx2IY67AKxVWUAVWUtwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r 1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE-syl 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r 4UJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAI cVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbKsjUUUUUU== X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAJCGMgctwUuAAisj Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053 C code changes for building EDK2 LoongArch platform. For definitions of PE/COFF and LOONGARCH relocation types, see the "Machine Types" and "Basic Relocation Types" sections of this URL for LOONGARCH values: https://docs.microsoft.com/en-us/windows/win32/debug/pe-format Cc: Bob Feng Cc: Liming Gao Cc: Yuwei Chen Signed-off-by: Chao Li Co-authored-by: Dongyan Qian Co-authored-by: Baoqi Zhang Co-authored-by: Yang Zhou Co-authored-by: Xiaotian Wu --- BaseTools/Source/C/Common/BasePeCoff.c | 15 +- BaseTools/Source/C/Common/PeCoffLoaderEx.c | 79 +++++ BaseTools/Source/C/GenFv/GenFvInternalLib.c | 125 +++++++- BaseTools/Source/C/GenFw/Elf64Convert.c | 293 +++++++++++++++++- BaseTools/Source/C/GenFw/elf_common.h | 94 ++++++ .../C/Include/IndustryStandard/PeImage.h | 57 ++-- BaseTools/Source/C/Makefiles/header.makefile | 6 + 7 files changed, 636 insertions(+), 33 deletions(-) diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Co= mmon/BasePeCoff.c index 62fbb2985c..30400d1341 100644 --- a/BaseTools/Source/C/Common/BasePeCoff.c +++ b/BaseTools/Source/C/Common/BasePeCoff.c @@ -5,6 +5,7 @@ Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
=0D Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -68,6 +69,14 @@ PeCoffLoaderRelocateRiscVImage ( IN UINT64 Adjust=0D );=0D =0D +RETURN_STATUS=0D +PeCoffLoaderRelocateLoongArch64Image (=0D + IN UINT16 *Reloc,=0D + IN OUT CHAR8 *Fixup,=0D + IN OUT CHAR8 **FixupData,=0D + IN UINT64 Adjust=0D + );=0D +=0D STATIC=0D RETURN_STATUS=0D PeCoffLoaderGetPeHeader (=0D @@ -184,7 +193,8 @@ Returns: ImageContext->Machine !=3D EFI_IMAGE_MACHINE_ARMT && \=0D ImageContext->Machine !=3D EFI_IMAGE_MACHINE_EBC && \=0D ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64 && \=0D - ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64) {=0D + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64 && \=0D + ImageContext->Machine !=3D EFI_IMAGE_MACHINE_LOONGARCH64) {=0D if (ImageContext->Machine =3D=3D IMAGE_FILE_MACHINE_ARM) {=0D //=0D // There are two types of ARM images. Pure ARM and ARM/Thumb.=0D @@ -815,6 +825,9 @@ Returns: case EFI_IMAGE_MACHINE_RISCV64:=0D Status =3D PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupD= ata, Adjust);=0D break;=0D + case EFI_IMAGE_MACHINE_LOONGARCH64:=0D + Status =3D PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup, &= FixupData, Adjust);=0D + break;=0D default:=0D Status =3D RETURN_UNSUPPORTED;=0D break;=0D diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/= C/Common/PeCoffLoaderEx.c index 799f282970..2cc428d733 100644 --- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c +++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c @@ -4,6 +4,7 @@ IA32 and X64 Specific relocation fixups Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.
=0D Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.
=0D +Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re= served.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D --*/=0D @@ -332,3 +333,81 @@ PeCoffLoaderRelocateArmImage ( =0D return RETURN_SUCCESS;=0D }=0D +=0D +/**=0D + Performs a LoongArch specific relocation fixup.=0D +=0D + @param[in] Reloc Pointer to the relocation record.=0D + @param[in, out] Fixup Pointer to the address to fix up.=0D + @param[in, out] FixupData Pointer to a buffer to log the fixups.=0D + @param[in] Adjust The offset to adjust the fixup.=0D +=0D + @return Status code.=0D +**/=0D +RETURN_STATUS=0D +PeCoffLoaderRelocateLoongArch64Image (=0D + IN UINT16 *Reloc,=0D + IN OUT CHAR8 *Fixup,=0D + IN OUT CHAR8 **FixupData,=0D + IN UINT64 Adjust=0D + )=0D +{=0D + UINT8 RelocType;=0D + UINT64 Value;=0D + UINT64 Tmp1;=0D + UINT64 Tmp2;=0D +=0D + RelocType =3D ((*Reloc) >> 12);=0D + Value =3D 0;=0D + Tmp1 =3D 0;=0D + Tmp2 =3D 0;=0D +=0D + switch (RelocType) {=0D + case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA:=0D + // The next four instructions are used to load a 64 bit address, rel= ocate all of them=0D + Value =3D (*(UINT32 *)Fixup & 0x1ffffe0) << 7 | // lu12i.w 20b= its from bit5=0D + (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori 12bit= s from bit10=0D + Tmp1 =3D *((UINT32 *)Fixup + 2) & 0x1ffffe0; // lu32i.d 20b= its from bit5=0D + Tmp2 =3D *((UINT32 *)Fixup + 3) & 0x3ffc00; // lu52i.d 12b= its from bit10=0D + Value =3D Value | (Tmp1 << 27) | (Tmp2 << 42);=0D + Value +=3D Adjust;=0D +=0D + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 1= 2) & 0xfffff) << 5);=0D + if (*FixupData !=3D NULL) {=0D + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN= T32));=0D + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D + *FixupData =3D *FixupData + sizeof (UINT32);=0D + }=0D +=0D + Fixup +=3D sizeof (UINT32);=0D + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | ((Value & 0xff= f) << 10);=0D + if (*FixupData !=3D NULL) {=0D + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN= T32));=0D + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D + *FixupData =3D *FixupData + sizeof (UINT32);=0D + }=0D +=0D + Fixup +=3D sizeof (UINT32);=0D + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 3= 2) & 0xfffff) << 5);=0D + if (*FixupData !=3D NULL) {=0D + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN= T32));=0D + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D + *FixupData =3D *FixupData + sizeof (UINT32);=0D + }=0D +=0D + Fixup +=3D sizeof (UINT32);=0D + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value >> 52= ) & 0xfff) << 10);=0D + if (*FixupData !=3D NULL) {=0D + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN= T32));=0D + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D + *FixupData =3D *FixupData + sizeof (UINT32);=0D + }=0D +=0D + break;=0D + default:=0D + Error (NULL, 0, 3000, "", "PeCoffLoaderRelocateLoongArch64Image: Fix= up[0x%x] Adjust[0x%llx] *Reloc[0x%x], type[0x%x].", *(UINT32 *)Fixup, Adjus= t, *Reloc, RelocType);=0D + return RETURN_UNSUPPORTED;=0D + }=0D +=0D + return RETURN_SUCCESS;=0D +}=0D diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source= /C/GenFv/GenFvInternalLib.c index d650a527a5..575b99b6ad 100644 --- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c +++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c @@ -5,6 +5,7 @@ Copyright (c) 2004 - 2018, Intel Corporation. All rights re= served.
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D Portions Copyright (c) 2016 HP Development Company, L.P.
=0D Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D @@ -57,6 +58,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =0D BOOLEAN mArm =3D FALSE;=0D BOOLEAN mRiscV =3D FALSE;=0D +BOOLEAN mLoongArch =3D FALSE;=0D STATIC UINT32 MaxFfsAlignment =3D 0;=0D BOOLEAN VtfFileFlag =3D FALSE;=0D =0D @@ -2416,6 +2418,98 @@ Returns: return EFI_SUCCESS;=0D }=0D =0D +EFI_STATUS=0D +UpdateLoongArchResetVectorIfNeeded (=0D + IN MEMORY_FILE *FvImage,=0D + IN FV_INFO *FvInfo=0D + )=0D +/*++=0D +=0D +Routine Description:=0D + This parses the FV looking for SEC and patches that address into the=0D + beginning of the FV header.=0D +=0D + For LoongArch ISA, the reset vector is at 0x1c000000.=0D +=0D + We relocate it to SecCoreEntry and copy the ResetVector code to the=0D + beginning of the FV.=0D +=0D +Arguments:=0D + FvImage Memory file for the FV memory image=0D + FvInfo Information read from INF file.=0D +=0D +Returns:=0D +=0D + EFI_SUCCESS Function Completed successfully.=0D + EFI_ABORTED Error encountered.=0D + EFI_INVALID_PARAMETER A required parameter was NULL.=0D + EFI_NOT_FOUND PEI Core file not found.=0D +=0D +--*/=0D +{=0D + EFI_STATUS Status;=0D + EFI_FILE_SECTION_POINTER SecPe32;=0D + BOOLEAN UpdateVectorSec =3D FALSE;=0D + UINT16 MachineType =3D 0;=0D + EFI_PHYSICAL_ADDRESS SecCoreEntryAddress =3D 0;=0D +=0D + //=0D + // Verify input parameters=0D + //=0D + if (FvImage =3D=3D NULL || FvInfo =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + //=0D + // Locate an SEC Core instance and if found extract the machine type and= entry point address=0D + //=0D + Status =3D FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FI= LETYPE_SECURITY_CORE, &SecPe32);=0D + if (!EFI_ERROR(Status)) {=0D +=0D + Status =3D GetCoreMachineType(SecPe32, &MachineType);=0D + if (EFI_ERROR(Status)) {=0D + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type= for SEC Core.");=0D + return EFI_ABORTED;=0D + }=0D +=0D + Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe3= 2, &SecCoreEntryAddress);=0D + if (EFI_ERROR(Status)) {=0D + Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point = address for SEC Core.");=0D + return EFI_ABORTED;=0D + }=0D +=0D + UpdateVectorSec =3D TRUE;=0D + }=0D +=0D + if (!UpdateVectorSec)=0D + return EFI_SUCCESS;=0D +=0D + if (MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) {=0D + UINT32 ResetVector[1];=0D +=0D + memset(ResetVector, 0, sizeof (ResetVector));=0D +=0D + /* if we found an SEC core entry point then generate a branch instruct= ion */=0D + if (UpdateVectorSec) {=0D + VerboseMsg("UpdateLoongArchResetVectorIfNeeded updating LOONGARCH64 = SEC vector");=0D +=0D + ResetVector[0] =3D ((SecCoreEntryAddress - FvInfo->BaseAddress) & 0x= 3FFFFFF) >> 2;=0D + ResetVector[0] =3D ((ResetVector[0] & 0x0FFFF) << 10) | ((ResetVecto= r[0] >> 16) & 0x3FF);=0D + ResetVector[0] |=3D 0x54000000; /* bl offset */=0D + }=0D +=0D + //=0D + // Copy to the beginning of the FV=0D + //=0D + memcpy(FvImage->FileImage, ResetVector, sizeof (ResetVector));=0D + } else {=0D + Error(NULL, 0, 3000, "Invalid", "Unknown machine type");=0D + return EFI_ABORTED;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D EFI_STATUS=0D GetPe32Info (=0D IN UINT8 *Pe32,=0D @@ -2509,7 +2603,7 @@ Returns: //=0D if ((*MachineType !=3D EFI_IMAGE_MACHINE_IA32) && (*MachineType !=3D EF= I_IMAGE_MACHINE_X64) && (*MachineType !=3D EFI_IMAGE_MACHINE_EBC) &&=0D (*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D EFI= _IMAGE_MACHINE_AARCH64) &&=0D - (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64)) {=0D + (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64) && (*MachineType !=3D = EFI_IMAGE_MACHINE_LOONGARCH64)) {=0D Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE3= 2 file.");=0D return EFI_UNSUPPORTED;=0D }=0D @@ -2953,7 +3047,7 @@ Returns: goto Finish;=0D }=0D =0D - if (!mArm && !mRiscV) {=0D + if (!mArm && !mRiscV && !mLoongArch) {=0D //=0D // Update reset vector (SALE_ENTRY for IPF)=0D // Now for IA32 and IA64 platform, the fv which has bsf file must ha= ve the=0D @@ -3004,6 +3098,19 @@ Returns: FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea= der->HeaderLength / sizeof (UINT16));=0D }=0D =0D + if (mLoongArch) {=0D + Status =3D UpdateLoongArchResetVectorIfNeeded (&FvImageMemoryFile, &mF= vDataInfo);=0D + if (EFI_ERROR (Status)) {=0D + Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector.= ");=0D + goto Finish;=0D + }=0D + //=0D + // Update Checksum for FvHeader=0D + //=0D + FvHeader->Checksum =3D 0;=0D + FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea= der->HeaderLength / sizeof (UINT16));=0D + }=0D +=0D //=0D // Update FV Alignment attribute to the largest alignment of all the FFS= files in the FV=0D //=0D @@ -3450,6 +3557,12 @@ Returns: VerboseMsg("Located ARM/AArch64 SEC/PEI core in child FV");=0D mArm =3D TRUE;=0D }=0D +=0D + // Machine type is LOONGARCH64, set a flag so LoongArch64 reset vect= or processed.=0D + if ((MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64)) {=0D + VerboseMsg("Located LoongArch64 SEC core in child FV");=0D + mLoongArch =3D TRUE;=0D + }=0D }=0D =0D //=0D @@ -3608,6 +3721,10 @@ Returns: mRiscV =3D TRUE;=0D }=0D =0D + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) ) {=0D + mLoongArch =3D TRUE;=0D + }=0D +=0D //=0D // Keep Image Context for PE image in FV=0D //=0D @@ -3885,6 +4002,10 @@ Returns: mArm =3D TRUE;=0D }=0D =0D + if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) ) {=0D + mLoongArch =3D TRUE;=0D + }=0D +=0D //=0D // Keep Image Context for TE image in FV=0D //=0D diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G= enFw/Elf64Convert.c index ca3c8f8bee..ede2f0ef90 100644 --- a/BaseTools/Source/C/GenFw/Elf64Convert.c +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c @@ -4,6 +4,7 @@ Elf64 convert solution Copyright (c) 2010 - 2021, Intel Corporation. All rights reserved.
=0D Portions copyright (c) 2013-2022, ARM Ltd. All rights reserved.
=0D Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -177,7 +178,7 @@ InitializeElf64 ( Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN= ");=0D return FALSE;=0D }=0D - if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D EM= _AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64))) {=0D + if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D EM= _AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64) || (mEhdr->e_machine =3D= =3D EM_LOONGARCH))) {=0D Warning (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 mac= hine.");=0D }=0D if (mEhdr->e_version !=3D EV_CURRENT) {=0D @@ -799,6 +800,7 @@ ScanSections64 ( case EM_X86_64:=0D case EM_AARCH64:=0D case EM_RISCV64:=0D + case EM_LOONGARCH:=0D mCoffOffset +=3D sizeof (EFI_IMAGE_NT_HEADERS64);=0D break;=0D default:=0D @@ -1088,6 +1090,10 @@ ScanSections64 ( NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_RISCV64;=0D NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M= AGIC;=0D break;=0D + case EM_LOONGARCH:=0D + NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_LOONGARCH64;= =0D + NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M= AGIC;=0D + break;=0D =0D default:=0D VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_m= achine);=0D @@ -1333,10 +1339,10 @@ WriteSections64 ( }=0D =0D //=0D - // Skip error on EM_RISCV64 becasue no symble name is built=0D - // from RISC-V toolchain.=0D + // Skip error on EM_RISCV64 and EM_LOONGARCH because no symbol n= ame is built=0D + // from RISC-V and LoongArch toolchain.=0D //=0D - if (mEhdr->e_machine !=3D EM_RISCV64) {=0D + if ((mEhdr->e_machine !=3D EM_RISCV64) && (mEhdr->e_machine !=3D= EM_LOONGARCH)) {=0D Error (NULL, 0, 3000, "Invalid",=0D "%s: Bad definition for symbol '%s'@%#llx or unsupporte= d symbol type. "=0D "For example, absolute and undefined symbols are not su= pported.",=0D @@ -1618,6 +1624,178 @@ WriteSections64 ( // Write section for RISC-V 64 architecture.=0D //=0D WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym);=0D + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH) {=0D + switch (ELF_R_TYPE(Rel->r_info)) {=0D + INT64 Offset;=0D + INT32 Lo, Hi;=0D +=0D + case R_LARCH_SOP_PUSH_ABSOLUTE:=0D + //=0D + // Absolute relocation.=0D + //=0D + *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoff= SectionsOffset[Sym->st_shndx];=0D + break;=0D +=0D + case R_LARCH_MARK_LA:=0D + case R_LARCH_64:=0D + case R_LARCH_NONE:=0D + case R_LARCH_32:=0D + case R_LARCH_RELATIVE:=0D + case R_LARCH_COPY:=0D + case R_LARCH_JUMP_SLOT:=0D + case R_LARCH_TLS_DTPMOD32:=0D + case R_LARCH_TLS_DTPMOD64:=0D + case R_LARCH_TLS_DTPREL32:=0D + case R_LARCH_TLS_DTPREL64:=0D + case R_LARCH_TLS_TPREL32:=0D + case R_LARCH_TLS_TPREL64:=0D + case R_LARCH_IRELATIVE:=0D + case R_LARCH_MARK_PCREL:=0D + case R_LARCH_SOP_PUSH_PCREL:=0D + case R_LARCH_SOP_PUSH_DUP:=0D + case R_LARCH_SOP_PUSH_GPREL:=0D + case R_LARCH_SOP_PUSH_TLS_TPREL:=0D + case R_LARCH_SOP_PUSH_TLS_GOT:=0D + case R_LARCH_SOP_PUSH_TLS_GD:=0D + case R_LARCH_SOP_PUSH_PLT_PCREL:=0D + case R_LARCH_SOP_ASSERT:=0D + case R_LARCH_SOP_NOT:=0D + case R_LARCH_SOP_SUB:=0D + case R_LARCH_SOP_SL:=0D + case R_LARCH_SOP_SR:=0D + case R_LARCH_SOP_ADD:=0D + case R_LARCH_SOP_AND:=0D + case R_LARCH_SOP_IF_ELSE:=0D + case R_LARCH_SOP_POP_32_S_10_5:=0D + case R_LARCH_SOP_POP_32_U_10_12:=0D + case R_LARCH_SOP_POP_32_S_10_12:=0D + case R_LARCH_SOP_POP_32_S_10_16:=0D + case R_LARCH_SOP_POP_32_S_10_16_S2:=0D + case R_LARCH_SOP_POP_32_S_5_20:=0D + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:=0D + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:=0D + case R_LARCH_SOP_POP_32_U:=0D + case R_LARCH_ADD8:=0D + case R_LARCH_ADD16:=0D + case R_LARCH_ADD24:=0D + case R_LARCH_ADD32:=0D + case R_LARCH_ADD64:=0D + case R_LARCH_SUB8:=0D + case R_LARCH_SUB16:=0D + case R_LARCH_SUB24:=0D + case R_LARCH_SUB32:=0D + case R_LARCH_SUB64:=0D + case R_LARCH_GNU_VTINHERIT:=0D + case R_LARCH_GNU_VTENTRY:=0D + case R_LARCH_B16:=0D + case R_LARCH_B21:=0D + case R_LARCH_B26:=0D + case R_LARCH_ABS_HI20:=0D + case R_LARCH_ABS_LO12:=0D + case R_LARCH_ABS64_LO20:=0D + case R_LARCH_ABS64_HI12:=0D + case R_LARCH_PCALA_LO12:=0D + case R_LARCH_PCALA64_LO20:=0D + case R_LARCH_PCALA64_HI12:=0D + case R_LARCH_GOT_PC_LO12:=0D + case R_LARCH_GOT64_PC_LO20:=0D + case R_LARCH_GOT64_PC_HI12:=0D + case R_LARCH_GOT64_HI20:=0D + case R_LARCH_GOT64_LO12:=0D + case R_LARCH_GOT64_LO20:=0D + case R_LARCH_GOT64_HI12:=0D + case R_LARCH_TLS_LE_HI20:=0D + case R_LARCH_TLS_LE_LO12:=0D + case R_LARCH_TLS_LE64_LO20:=0D + case R_LARCH_TLS_LE64_HI12:=0D + case R_LARCH_TLS_IE_PC_HI20:=0D + case R_LARCH_TLS_IE_PC_LO12:=0D + case R_LARCH_TLS_IE64_PC_LO20:=0D + case R_LARCH_TLS_IE64_PC_HI12:=0D + case R_LARCH_TLS_IE64_HI20:=0D + case R_LARCH_TLS_IE64_LO12:=0D + case R_LARCH_TLS_IE64_LO20:=0D + case R_LARCH_TLS_IE64_HI12:=0D + case R_LARCH_TLS_LD_PC_HI20:=0D + case R_LARCH_TLS_LD64_HI20:=0D + case R_LARCH_TLS_GD_PC_HI20:=0D + case R_LARCH_TLS_GD64_HI20:=0D + case R_LARCH_RELAX:=0D + //=0D + // These types are not used or do not require fixup.=0D + //=0D + break;=0D +=0D + case R_LARCH_GOT_PC_HI20:=0D + Offset =3D Sym->st_value - (UINTN)(Targ - mCoffFile);=0D + if (Offset < 0) {=0D + Offset =3D (UINTN)(Targ - mCoffFile) - Sym->st_value;=0D + Hi =3D (Offset / 0x1000) << 12;=0D + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20;=0D + if ((Lo < 0) && (Lo > -2048)) {=0D + Hi +=3D 0x1000;=0D + Lo =3D ~(0x1000 - Lo) + 1;=0D + }=0D + Hi =3D ~Hi + 1;=0D + Lo =3D ~Lo + 1;=0D + } else {=0D + Hi =3D (Offset / 0x1000) << 12;=0D + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20;=0D + if (Lo < 0) {=0D + Hi +=3D 0x1000;=0D + Lo =3D ~(0x1000 - Lo) + 1;=0D + }=0D + }=0D + // Re-encode the offset as an PCADD.D + ADDI.D(Convert LD.D) i= nstruction=0D + *(UINT32 *)Targ &=3D 0x1f;=0D + *(UINT32 *)Targ |=3D 0x1c000000;=0D + *(UINT32 *)Targ |=3D (((Hi >> 12) & 0xfffff) << 5);=0D + *(UINT32 *)(Targ + 4) &=3D 0x3ff;=0D + *(UINT32 *)(Targ + 4) |=3D 0x2c00000 | ((Lo & 0xfff) << 10);=0D + break;=0D +=0D + //=0D + // Attempt to convert instruction.=0D + //=0D + case R_LARCH_PCALA_HI20:=0D + // Decode the PCALAU12I + ADDI.D instruction=0D + Offset =3D ((INT32)((*(UINT32 *)Targ & 0x1ffffe0) << 7));=0D + Offset +=3D ((INT32)((*(UINT32 *)(Targ + 4) & 0x3ffc00) << 10)= >> 20);=0D + //=0D + // PCALA offset is relative to the previous page boundary,=0D + // whereas PCADD offset is relative to the instruction itself.= =0D + // So fix up the offset so it points to the page containing=0D + // the symbol.=0D + //=0D + Offset -=3D (UINTN)(Targ - mCoffFile) & 0xfff;=0D + if (Offset < 0) {=0D + Offset =3D -Offset;=0D + Hi =3D (Offset / 0x1000) << 12;=0D + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20;=0D + if ((Lo < 0) && (Lo > -2048)) {=0D + Hi +=3D 0x1000;=0D + Lo =3D ~(0x1000 - Lo) + 1;=0D + }=0D + Hi =3D ~Hi + 1;=0D + Lo =3D ~Lo + 1;=0D + } else {=0D + Hi =3D (Offset / 0x1000) << 12;=0D + Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20;=0D + if (Lo < 0) {=0D + Hi +=3D 0x1000;=0D + Lo =3D ~(0x1000 - Lo) + 1;=0D + }=0D + }=0D + // Re-encode the offset as an PCADD.D + ADDI.D instruction=0D + *(UINT32 *)Targ &=3D 0x1f;=0D + *(UINT32 *)Targ |=3D 0x1c000000;=0D + *(UINT32 *)Targ |=3D (((Hi >> 12) & 0xfffff) << 5);=0D + *(UINT32 *)(Targ + 4) &=3D 0xffc003ff;=0D + *(UINT32 *)(Targ + 4) |=3D (Lo & 0xfff) << 10;=0D + break;=0D + default:=0D + Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupp= orted ELF EM_LOONGARCH relocation 0x%x.", mInImageName, (unsigned) ELF64_R_= TYPE(Rel->r_info));=0D + }=0D } else {=0D Error (NULL, 0, 3000, "Invalid", "Not a supported machine type")= ;=0D }=0D @@ -1850,6 +2028,113 @@ WriteRelocations64 ( default:=0D Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s u= nsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R= _TYPE(Rel->r_info));=0D }=0D + } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH) {=0D + switch (ELF_R_TYPE(Rel->r_info)) {=0D + case R_LARCH_MARK_LA:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]= =0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA);=0D + break;=0D + case R_LARCH_64:=0D + CoffAddFixup(=0D + (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]= =0D + + (Rel->r_offset - SecShdr->sh_addr)),=0D + EFI_IMAGE_REL_BASED_DIR64);=0D + break;=0D + case R_LARCH_NONE:=0D + case R_LARCH_32:=0D + case R_LARCH_RELATIVE:=0D + case R_LARCH_COPY:=0D + case R_LARCH_JUMP_SLOT:=0D + case R_LARCH_TLS_DTPMOD32:=0D + case R_LARCH_TLS_DTPMOD64:=0D + case R_LARCH_TLS_DTPREL32:=0D + case R_LARCH_TLS_DTPREL64:=0D + case R_LARCH_TLS_TPREL32:=0D + case R_LARCH_TLS_TPREL64:=0D + case R_LARCH_IRELATIVE:=0D + case R_LARCH_MARK_PCREL:=0D + case R_LARCH_SOP_PUSH_PCREL:=0D + case R_LARCH_SOP_PUSH_ABSOLUTE:=0D + case R_LARCH_SOP_PUSH_DUP:=0D + case R_LARCH_SOP_PUSH_GPREL:=0D + case R_LARCH_SOP_PUSH_TLS_TPREL:=0D + case R_LARCH_SOP_PUSH_TLS_GOT:=0D + case R_LARCH_SOP_PUSH_TLS_GD:=0D + case R_LARCH_SOP_PUSH_PLT_PCREL:=0D + case R_LARCH_SOP_ASSERT:=0D + case R_LARCH_SOP_NOT:=0D + case R_LARCH_SOP_SUB:=0D + case R_LARCH_SOP_SL:=0D + case R_LARCH_SOP_SR:=0D + case R_LARCH_SOP_ADD:=0D + case R_LARCH_SOP_AND:=0D + case R_LARCH_SOP_IF_ELSE:=0D + case R_LARCH_SOP_POP_32_S_10_5:=0D + case R_LARCH_SOP_POP_32_U_10_12:=0D + case R_LARCH_SOP_POP_32_S_10_12:=0D + case R_LARCH_SOP_POP_32_S_10_16:=0D + case R_LARCH_SOP_POP_32_S_10_16_S2:=0D + case R_LARCH_SOP_POP_32_S_5_20:=0D + case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:=0D + case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:=0D + case R_LARCH_SOP_POP_32_U:=0D + case R_LARCH_ADD8:=0D + case R_LARCH_ADD16:=0D + case R_LARCH_ADD24:=0D + case R_LARCH_ADD32:=0D + case R_LARCH_ADD64:=0D + case R_LARCH_SUB8:=0D + case R_LARCH_SUB16:=0D + case R_LARCH_SUB24:=0D + case R_LARCH_SUB32:=0D + case R_LARCH_SUB64:=0D + case R_LARCH_GNU_VTINHERIT:=0D + case R_LARCH_GNU_VTENTRY:=0D + case R_LARCH_B16:=0D + case R_LARCH_B21:=0D + case R_LARCH_B26:=0D + case R_LARCH_ABS_HI20:=0D + case R_LARCH_ABS_LO12:=0D + case R_LARCH_ABS64_LO20:=0D + case R_LARCH_ABS64_HI12:=0D + case R_LARCH_PCALA_HI20:=0D + case R_LARCH_PCALA_LO12:=0D + case R_LARCH_PCALA64_LO20:=0D + case R_LARCH_PCALA64_HI12:=0D + case R_LARCH_GOT_PC_HI20:=0D + case R_LARCH_GOT_PC_LO12:=0D + case R_LARCH_GOT64_PC_LO20:=0D + case R_LARCH_GOT64_PC_HI12:=0D + case R_LARCH_GOT64_HI20:=0D + case R_LARCH_GOT64_LO12:=0D + case R_LARCH_GOT64_LO20:=0D + case R_LARCH_GOT64_HI12:=0D + case R_LARCH_TLS_LE_HI20:=0D + case R_LARCH_TLS_LE_LO12:=0D + case R_LARCH_TLS_LE64_LO20:=0D + case R_LARCH_TLS_LE64_HI12:=0D + case R_LARCH_TLS_IE_PC_HI20:=0D + case R_LARCH_TLS_IE_PC_LO12:=0D + case R_LARCH_TLS_IE64_PC_LO20:=0D + case R_LARCH_TLS_IE64_PC_HI12:=0D + case R_LARCH_TLS_IE64_HI20:=0D + case R_LARCH_TLS_IE64_LO12:=0D + case R_LARCH_TLS_IE64_LO20:=0D + case R_LARCH_TLS_IE64_HI12:=0D + case R_LARCH_TLS_LD_PC_HI20:=0D + case R_LARCH_TLS_LD64_HI20:=0D + case R_LARCH_TLS_GD_PC_HI20:=0D + case R_LARCH_TLS_GD64_HI20:=0D + case R_LARCH_RELAX:=0D + //=0D + // These types are not used or do not require fixup in PE = format files.=0D + //=0D + break;=0D + default:=0D + Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): = %s unsupported ELF EM_LOONGARCH relocation 0x%x.", mInImageName, (unsigned)= ELF64_R_TYPE(Rel->r_info));=0D + }=0D } else {=0D Error (NULL, 0, 3000, "Not Supported", "This tool does not sup= port relocations for ELF with e_machine %u (processor type).", (unsigned) m= Ehdr->e_machine);=0D }=0D diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/Gen= Fw/elf_common.h index b67f59e7a0..7b7fdeb329 100644 --- a/BaseTools/Source/C/GenFw/elf_common.h +++ b/BaseTools/Source/C/GenFw/elf_common.h @@ -4,6 +4,7 @@ Ported ELF include files from FreeBSD Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.
=0D Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D Portion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All= rights reserved.
=0D +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D =0D @@ -181,6 +182,7 @@ typedef struct { #define EM_AARCH64 183 /* ARM 64bit Architecture */=0D #define EM_RISCV64 243 /* 64bit RISC-V Architecture */=0D #define EM_RISCV 244 /* 32bit RISC-V Architecture */=0D +#define EM_LOONGARCH 258 /* LoongArch Architecture */=0D =0D /* Non-standard or deprecated. */=0D #define EM_486 6 /* Intel i486. */=0D @@ -1042,4 +1044,96 @@ typedef struct { #define R_RISCV_SET8 54=0D #define R_RISCV_SET16 55=0D #define R_RISCV_SET32 56=0D +=0D +/*=0D + * LoongArch relocation types=0D + */=0D +#define R_LARCH_NONE 0=0D +#define R_LARCH_32 1=0D +#define R_LARCH_64 2=0D +#define R_LARCH_RELATIVE 3=0D +#define R_LARCH_COPY 4=0D +#define R_LARCH_JUMP_SLOT 5=0D +#define R_LARCH_TLS_DTPMOD32 6=0D +#define R_LARCH_TLS_DTPMOD64 7=0D +#define R_LARCH_TLS_DTPREL32 8=0D +#define R_LARCH_TLS_DTPREL64 9=0D +#define R_LARCH_TLS_TPREL32 10=0D +#define R_LARCH_TLS_TPREL64 11=0D +#define R_LARCH_IRELATIVE 12=0D +#define R_LARCH_MARK_LA 20=0D +#define R_LARCH_MARK_PCREL 21=0D +#define R_LARCH_SOP_PUSH_PCREL 22=0D +#define R_LARCH_SOP_PUSH_ABSOLUTE 23=0D +#define R_LARCH_SOP_PUSH_DUP 24=0D +#define R_LARCH_SOP_PUSH_GPREL 25=0D +#define R_LARCH_SOP_PUSH_TLS_TPREL 26=0D +#define R_LARCH_SOP_PUSH_TLS_GOT 27=0D +#define R_LARCH_SOP_PUSH_TLS_GD 28=0D +#define R_LARCH_SOP_PUSH_PLT_PCREL 29=0D +#define R_LARCH_SOP_ASSERT 30=0D +#define R_LARCH_SOP_NOT 31=0D +#define R_LARCH_SOP_SUB 32=0D +#define R_LARCH_SOP_SL 33=0D +#define R_LARCH_SOP_SR 34=0D +#define R_LARCH_SOP_ADD 35=0D +#define R_LARCH_SOP_AND 36=0D +#define R_LARCH_SOP_IF_ELSE 37=0D +#define R_LARCH_SOP_POP_32_S_10_5 38=0D +#define R_LARCH_SOP_POP_32_U_10_12 39=0D +#define R_LARCH_SOP_POP_32_S_10_12 40=0D +#define R_LARCH_SOP_POP_32_S_10_16 41=0D +#define R_LARCH_SOP_POP_32_S_10_16_S2 42=0D +#define R_LARCH_SOP_POP_32_S_5_20 43=0D +#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44=0D +#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45=0D +#define R_LARCH_SOP_POP_32_U 46=0D +#define R_LARCH_ADD8 47=0D +#define R_LARCH_ADD16 48=0D +#define R_LARCH_ADD24 49=0D +#define R_LARCH_ADD32 50=0D +#define R_LARCH_ADD64 51=0D +#define R_LARCH_SUB8 52=0D +#define R_LARCH_SUB16 53=0D +#define R_LARCH_SUB24 54=0D +#define R_LARCH_SUB32 55=0D +#define R_LARCH_SUB64 56=0D +#define R_LARCH_GNU_VTINHERIT 57=0D +#define R_LARCH_GNU_VTENTRY 58=0D +#define R_LARCH_B16 64=0D +#define R_LARCH_B21 65=0D +#define R_LARCH_B26 66=0D +#define R_LARCH_ABS_HI20 67=0D +#define R_LARCH_ABS_LO12 68=0D +#define R_LARCH_ABS64_LO20 69=0D +#define R_LARCH_ABS64_HI12 70=0D +#define R_LARCH_PCALA_HI20 71=0D +#define R_LARCH_PCALA_LO12 72=0D +#define R_LARCH_PCALA64_LO20 73=0D +#define R_LARCH_PCALA64_HI12 74=0D +#define R_LARCH_GOT_PC_HI20 75=0D +#define R_LARCH_GOT_PC_LO12 76=0D +#define R_LARCH_GOT64_PC_LO20 77=0D +#define R_LARCH_GOT64_PC_HI12 78=0D +#define R_LARCH_GOT64_HI20 79=0D +#define R_LARCH_GOT64_LO12 80=0D +#define R_LARCH_GOT64_LO20 81=0D +#define R_LARCH_GOT64_HI12 82=0D +#define R_LARCH_TLS_LE_HI20 83=0D +#define R_LARCH_TLS_LE_LO12 84=0D +#define R_LARCH_TLS_LE64_LO20 85=0D +#define R_LARCH_TLS_LE64_HI12 86=0D +#define R_LARCH_TLS_IE_PC_HI20 87=0D +#define R_LARCH_TLS_IE_PC_LO12 88=0D +#define R_LARCH_TLS_IE64_PC_LO20 89=0D +#define R_LARCH_TLS_IE64_PC_HI12 90=0D +#define R_LARCH_TLS_IE64_HI20 91=0D +#define R_LARCH_TLS_IE64_LO12 92=0D +#define R_LARCH_TLS_IE64_LO20 93=0D +#define R_LARCH_TLS_IE64_HI12 94=0D +#define R_LARCH_TLS_LD_PC_HI20 95=0D +#define R_LARCH_TLS_LD64_HI20 96=0D +#define R_LARCH_TLS_GD_PC_HI20 97=0D +#define R_LARCH_TLS_GD64_HI20 98=0D +#define R_LARCH_RELAX 99=0D #endif /* !_SYS_ELF_COMMON_H_ */=0D diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTo= ols/Source/C/Include/IndustryStandard/PeImage.h index 21c968e650..77ded3f611 100644 --- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h +++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h @@ -7,6 +7,7 @@ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.
=0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -36,23 +37,25 @@ //=0D // PE32+ Machine type for EFI images=0D //=0D -#define IMAGE_FILE_MACHINE_I386 0x014c=0D -#define IMAGE_FILE_MACHINE_EBC 0x0EBC=0D -#define IMAGE_FILE_MACHINE_X64 0x8664=0D -#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only=0D -#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/T= humb 2 Little Endian=0D -#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Lit= tle Endian=0D -#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA=0D +#define IMAGE_FILE_MACHINE_I386 0x014c=0D +#define IMAGE_FILE_MACHINE_EBC 0x0EBC=0D +#define IMAGE_FILE_MACHINE_X64 0x8664=0D +#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only=0D +#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thum= b/Thumb 2 Little Endian=0D +#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, = Little Endian=0D +#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA=0D +#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 // 64bit LoongArch Architec= ture=0D =0D //=0D // Support old names for backward compatible=0D //=0D -#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386=0D -#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC=0D -#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64=0D -#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT=0D -#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64=0D -#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64=0D +#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386=0D +#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC=0D +#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64=0D +#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT=0D +#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64=0D +#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64=0D +#define EFI_IMAGE_MACHINE_LOONGARCH64 IMAGE_FILE_MACHINE_LOONGARCH64=0D =0D #define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ=0D #define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE=0D @@ -500,19 +503,21 @@ typedef struct { //=0D // Based relocation types.=0D //=0D -#define EFI_IMAGE_REL_BASED_ABSOLUTE 0=0D -#define EFI_IMAGE_REL_BASED_HIGH 1=0D -#define EFI_IMAGE_REL_BASED_LOW 2=0D -#define EFI_IMAGE_REL_BASED_HIGHLOW 3=0D -#define EFI_IMAGE_REL_BASED_HIGHADJ 4=0D -#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5=0D -#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5=0D -#define EFI_IMAGE_REL_BASED_RISCV_HI20 5=0D -#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7=0D -#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7=0D -#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8=0D -#define EFI_IMAGE_REL_BASED_IA64_IMM64 9=0D -#define EFI_IMAGE_REL_BASED_DIR64 10=0D +#define EFI_IMAGE_REL_BASED_ABSOLUTE 0=0D +#define EFI_IMAGE_REL_BASED_HIGH 1=0D +#define EFI_IMAGE_REL_BASED_LOW 2=0D +#define EFI_IMAGE_REL_BASED_HIGHLOW 3=0D +#define EFI_IMAGE_REL_BASED_HIGHADJ 4=0D +#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5=0D +#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5=0D +#define EFI_IMAGE_REL_BASED_RISCV_HI20 5=0D +#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7=0D +#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7=0D +#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8=0D +#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8=0D +#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8=0D +#define EFI_IMAGE_REL_BASED_IA64_IMM64 9=0D +#define EFI_IMAGE_REL_BASED_DIR64 10=0D =0D =0D ///=0D diff --git a/BaseTools/Source/C/Makefiles/header.makefile b/BaseTools/Sourc= e/C/Makefiles/header.makefile index 0df728f327..4e88a4fbd8 100644 --- a/BaseTools/Source/C/Makefiles/header.makefile +++ b/BaseTools/Source/C/Makefiles/header.makefile @@ -31,6 +31,9 @@ ifndef HOST_ARCH ifneq (,$(findstring riscv64,$(uname_m)))=0D HOST_ARCH=3DRISCV64=0D endif=0D + ifneq (,$(findstring loongarch64,$(uname_m)))=0D + HOST_ARCH=3DLOONGARCH64=0D + endif=0D ifndef HOST_ARCH=0D $(info Could not detected HOST_ARCH from uname results)=0D $(error HOST_ARCH is not defined!)=0D @@ -70,6 +73,9 @@ ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/AArch64/ else ifeq ($(HOST_ARCH), RISCV64)=0D ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/RiscV64/=0D =0D +else ifeq ($(HOST_ARCH), LOONGARCH64)=0D +ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/LoongArch64/=0D +=0D else=0D $(error Bad HOST_ARCH)=0D endif=0D --=20 2.27.0