From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web10.4259.1663148510684340366 for ; Wed, 14 Sep 2022 02:41:53 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from code-server.gen (unknown [10.2.9.245]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dx_2vYoSFjWwEZAA--.29629S2; Wed, 14 Sep 2022 17:41:44 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu , Baoqi Zhang Subject: [PATCH v2 28/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code. Date: Wed, 14 Sep 2022 17:41:44 +0800 Message-Id: <20220914094144.3697283-1-lichao@loongson.cn> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Dx_2vYoSFjWwEZAA--.29629S2 X-Coremail-Antispam: 1UD129KBjvJXoW3Aw17WFW7Zr1DGw45Zw1DZFb_yoW3urWUpr WxtrWDKan2gw43GFy8J395GF15Aws2gw4UKFZ0yw10k3s0qrykZrsYqr48Kr18Zw17Ww18 WFy3KF4rua1UAFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUk2b7Iv0xC_Kw4lb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I2 0VC2zVCF04k26cxKx2IYs7xG6rWj6s0DM7CIcVAFz4kK6r1j6r18M28lY4IEw2IIxxk0rw A2F7IY1VAKz4vEj48ve4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Ar0_tr1l84ACjcxK6xII jxv20xvEc7CjxVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4 vEx4A2jsIEc7CjxVAFwI0_GcCE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xv F2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2jsIE14v26r4j6F 4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCY02Avz4vE-syl42xK82IY c2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s 026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r126r1DMIIYrxkI7VAKI48JMIIF 0xvE2Ix0cI8IcVAFwI0_Xr0_Ar1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIx AIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2 jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjxUy4EEUUUUU X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQAJCGMgctwUuAAysz Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053 Support LoongArch cache related functions. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Co-authored-by: Baoqi Zhang --- .../BaseSynchronizationLib.inf | 5 + .../LoongArch64/Synchronization.c | 246 ++++++++++++++++++ 2 files changed, 251 insertions(+) create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synch= ronization.c diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 02ba12961a..10021f3352 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -4,6 +4,7 @@ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
= =0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
= =0D # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights= reserved.
=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -82,6 +83,10 @@ Synchronization.c=0D RiscV64/Synchronization.S=0D =0D +[Sources.LOONGARCH64]=0D + Synchronization.c=0D + LoongArch64/Synchronization.c=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronizat= ion.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c new file mode 100644 index 0000000000..b7789f3212 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c @@ -0,0 +1,246 @@ +/** @file=0D + LoongArch synchronization functions.=0D +=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include =0D +=0D +/**=0D + Performs an atomic compare exchange operation on a 16-bit=0D + unsigned integer.=0D +=0D + Performs an atomic compare exchange operation on the 16-bit=0D + unsigned integer specified by Value. If Value is equal to=0D + CompareValue, then Value is set to ExchangeValue and=0D + CompareValue is returned. If Value is not equal to=0D + CompareValue, then Value is returned. The compare exchange=0D + operation must be performed using MP safe mechanisms.=0D +=0D + @param[in] Value A pointer to the 16-bit value for the=0D + compare exchange operation.=0D + @param[in] CompareValue 16-bit value used in compare operation.=0D + @param[in] ExchangeValue 16-bit value used in exchange operation.=0D +=0D + @return The original *Value before exchange.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +InternalSyncCompareExchange16 (=0D + IN volatile UINT16 *Value,=0D + IN UINT16 CompareValue,=0D + IN UINT16 ExchangeValue=0D + )=0D +{=0D + UINT32 RetValue;=0D + UINT32 Temp;=0D + UINT32 Shift;=0D + UINT64 Mask;=0D + UINT64 LocalCompareValue;=0D + UINT64 LocalExchangeValue;=0D + volatile UINT32 *Ptr32;=0D +=0D + /* Check that ptr is naturally aligned */=0D + ASSERT (!((UINT64)Value & (sizeof (Value) - 1)));=0D +=0D + /* Mask inputs to the correct size. */=0D + Mask =3D (((~0UL) - (1UL << (0)) + 1) & (~0UL >> (64 - 1 -= ((sizeof (UINT16) * 8) - 1))));=0D + LocalCompareValue =3D ((UINT64)CompareValue) & Mask;=0D + LocalExchangeValue =3D ((UINT64)ExchangeValue) & Mask;=0D +=0D + /*=0D + * Calculate a shift & mask that correspond to the value we wish to=0D + * compare & exchange within the naturally aligned 4 byte integer=0D + * that includes it.=0D + */=0D + Shift =3D (UINT64)Value & 0x3;=0D + Shift *=3D 8; /* BITS_PER_BYTE */=0D + LocalCompareValue <<=3D Shift;=0D + LocalExchangeValue <<=3D Shift;=0D + Mask <<=3D Shift;=0D +=0D + /*=0D + * Calculate a pointer to the naturally aligned 4 byte integer that=0D + * includes our byte of interest, and load its value.=0D + */=0D + Ptr32 =3D (UINT32 *)((UINT64)Value & ~0x3);=0D +=0D + __asm__ __volatile__ (=0D + "1: \n"=0D + "ll.w %0, %3 \n"=0D + "and %1, %0, %4 \n"=0D + "bne %1, %5, 2f \n"=0D + "andn %1, %0, %4 \n"=0D + "or %1, %1, %6 \n"=0D + "sc.w %1, %2 \n"=0D + "beqz %1, 1b \n"=0D + "b 3f \n"=0D + "2: \n"=0D + "dbar 0 \n"=0D + "3: \n"=0D + : "=3D&r" (RetValue), "=3D&r" (Temp), "=3D" "ZC" (*Ptr32)=0D + : "ZC" (*Ptr32), "Jr" (Mask), "Jr" (LocalCompareValue), "Jr" (LocalExc= hangeValue)=0D + : "memory"=0D + );=0D +=0D + return (RetValue & Mask) >> Shift;=0D +}=0D +=0D +/**=0D + Performs an atomic compare exchange operation on a 32-bit=0D + unsigned integer.=0D +=0D + Performs an atomic compare exchange operation on the 32-bit=0D + unsigned integer specified by Value. If Value is equal to=0D + CompareValue, then Value is set to ExchangeValue and=0D + CompareValue is returned. If Value is not equal to=0D + CompareValue, then Value is returned. The compare exchange=0D + operation must be performed using MP safe mechanisms.=0D +=0D + @param[in] Value A pointer to the 32-bit value for the=0D + compare exchange operation.=0D + @param[in] CompareValue 32-bit value used in compare operation.=0D + @param[in] ExchangeValue 32-bit value used in exchange operation.=0D +=0D + @return The original *Value before exchange.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +InternalSyncCompareExchange32 (=0D + IN volatile UINT32 *Value,=0D + IN UINT32 CompareValue,=0D + IN UINT32 ExchangeValue=0D + )=0D +{=0D + UINT32 RetValue;=0D +=0D + __asm__ __volatile__ (=0D + "1: \n"=0D + "ll.w %0, %2 \n"=0D + "bne %0, %3, 2f \n"=0D + "move %0, %4 \n"=0D + "sc.w %0, %1 \n"=0D + "beqz %0, 1b \n"=0D + "b 3f \n"=0D + "2: \n"=0D + "dbar 0 \n"=0D + "3: \n"=0D + : "=3D&r" (RetValue), "=3D" "ZC" (*Value)=0D + : "ZC" (*Value), "Jr" (CompareValue), "Jr" (ExchangeValue)=0D + : "memory"=0D + );=0D + return RetValue;=0D +}=0D +=0D +/**=0D + Performs an atomic compare exchange operation on a 64-bit unsigned integ= er.=0D +=0D + Performs an atomic compare exchange operation on the 64-bit unsigned int= eger specified=0D + by Value. If Value is equal to CompareValue, then Value is set to Excha= ngeValue and=0D + CompareValue is returned. If Value is not equal to CompareValue, then V= alue is returned.=0D + The compare exchange operation must be performed using MP safe mechanism= s.=0D +=0D + @param[in] Value A pointer to the 64-bit value for the compare = exchange=0D + operation.=0D + @param[in] CompareValue 64-bit value used in compare operation.=0D + @param[in] ExchangeValue 64-bit value used in exchange operation.=0D +=0D + @return The original *Value before exchange.=0D +=0D +**/=0D +UINT64=0D +EFIAPI=0D +InternalSyncCompareExchange64 (=0D + IN volatile UINT64 *Value,=0D + IN UINT64 CompareValue,=0D + IN UINT64 ExchangeValue=0D + )=0D +{=0D + UINT64 RetValue;=0D +=0D + __asm__ __volatile__ (=0D + "1: \n"=0D + "ll.d %0, %2 \n"=0D + "bne %0, %3, 2f \n"=0D + "move %0, %4 \n"=0D + "sc.d %0, %1 \n"=0D + "beqz %0, 1b \n"=0D + "b 3f \n"=0D + "2: \n"=0D + "dbar 0 \n"=0D + "3: \n"=0D + : "=3D&r" (RetValue), "=3D" "ZC" (*Value)=0D + : "ZC" (*Value), "Jr" (CompareValue), "Jr" (ExchangeValue)=0D + : "memory"=0D + );=0D + return RetValue;=0D +}=0D +=0D +/**=0D + Performs an atomic increment of an 32-bit unsigned integer.=0D +=0D + Performs an atomic increment of the 32-bit unsigned integer specified by= =0D + Value and returns the incremented value. The increment operation must be= =0D + performed using MP safe mechanisms. The state of the return value is not= =0D + guaranteed to be MP safe.=0D +=0D + @param[in] Value A pointer to the 32-bit value to increment.=0D +=0D + @return The incremented value.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +InternalSyncIncrement (=0D + IN volatile UINT32 *Value=0D + )=0D +{=0D + UINT32 Temp;=0D +=0D + Temp =3D *Value;=0D + __asm__ __volatile__ (=0D + "dbar 0 \n"=0D + "amadd.w %1, %2, %0 \n"=0D + : "+ZB" (*Value), "=3D&r" (Temp)=0D + : "r" (1)=0D + : "memory"=0D + );=0D + return *Value;=0D +}=0D +=0D +/**=0D + Performs an atomic decrement of an 32-bit unsigned integer.=0D +=0D + Performs an atomic decrement of the 32-bit unsigned integer specified by= =0D + Value and returns the decrement value. The decrement operation must be=0D + performed using MP safe mechanisms. The state of the return value is not= =0D + guaranteed to be MP safe.=0D +=0D + @param[in] Value A pointer to the 32-bit value to decrement.=0D +=0D + @return The decrement value.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +InternalSyncDecrement (=0D + IN volatile UINT32 *Value=0D + )=0D +{=0D + UINT32 Temp;=0D +=0D + Temp =3D *Value;=0D + __asm__ __volatile__ (=0D + "dbar 0 \n"=0D + "amadd.w %1, %2, %0 \n"=0D + : "+ZB" (*Value), "=3D&r" (Temp)=0D + : "r" (-1)=0D + : "memory"=0D + );=0D + return *Value;=0D +}=0D --=20 2.27.0