From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by mx.groups.io with SMTP id smtpd.web08.25932.1664180733681558031 for ; Mon, 26 Sep 2022 01:25:34 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=lo7/62gg; spf=pass (domain: kernel.org, ip: 145.40.68.75, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 23473B819A0; Mon, 26 Sep 2022 08:25:32 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DC1C2C433C1; Mon, 26 Sep 2022 08:25:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664180730; bh=yQm2T86Pe9CM6RwF6HnFRpze7cr5TYDR8iiOPX9tcDQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lo7/62gg8C8Yiw+W1ILel7K5ynzZK8HJ35STQJHZEMshnSrNRlVof53x50TKvwqdT 1OzmvnuUNCeatJlA4QUrsPNG6PSEW6VXAOarZTYOfHBYoz5T7kJUbomIHjfoYuTE0o ZyergwLoe0NHeSOgepofpoQyVNmKAaO8l4uln2achUd9hkPfm4j2FAQcpWm2cSHXZw 1tl9vAEks0dFrz6lcv1dXrxtlc3i/UGPQ/l6yqzdnaespRe8aDZNQQShKv8mytg6pX QUblfP/LsIvieVwaBcoBPkXCHfYe9TmyxEq6YTpJRuRrN/8RrsZMHq+8sOBjcvulGR kO+7TygIG3qlA== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Alexander Graf Subject: [PATCH v3 09/16] ArmPlatformPkg/PrePeiCore: permit entry with the MMU enabled Date: Mon, 26 Sep 2022 10:25:04 +0200 Message-Id: <20220926082511.2110797-10-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926082511.2110797-1-ardb@kernel.org> References: <20220926082511.2110797-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Some platforms may set up a preliminary ID map in flash and enter EFI with the MMU and caches enabled, as this removes a lot of the complexity around cache coherency. Let's take this into account, and avoid touching the MMU controls or perform cache invalidation when the MMU is enabled at entry. Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/PrePeiCore/PrePeiCore.c | 22 +++++++++++--------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c b/ArmPlatformPkg/PrePei= Core/PrePeiCore.c index 9c4b25df953d..8b86c6e69abd 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCore.c +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCore.c @@ -58,17 +58,19 @@ CEntryPoint ( IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint=0D )=0D {=0D - // Data Cache enabled on Primary core when MMU is enabled.=0D - ArmDisableDataCache ();=0D - // Invalidate instruction cache=0D - ArmInvalidateInstructionCache ();=0D - // Enable Instruction Caches on all cores.=0D - ArmEnableInstructionCache ();=0D + if (!ArmMmuEnabled ()) {=0D + // Data Cache enabled on Primary core when MMU is enabled.=0D + ArmDisableDataCache ();=0D + // Invalidate instruction cache=0D + ArmInvalidateInstructionCache ();=0D + // Enable Instruction Caches on all cores.=0D + ArmEnableInstructionCache ();=0D =0D - InvalidateDataCacheRange (=0D - (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),=0D - PcdGet32 (PcdCPUCorePrimaryStackSize)=0D - );=0D + InvalidateDataCacheRange (=0D + (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),=0D + PcdGet32 (PcdCPUCorePrimaryStackSize)=0D + );=0D + }=0D =0D //=0D // Note: Doesn't have to Enable CPU interface in non-secure world,=0D --=20 2.35.1