From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by mx.groups.io with SMTP id smtpd.web10.25935.1664180729537666112 for ; Mon, 26 Sep 2022 01:25:29 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=nU+A3YJt; spf=pass (domain: kernel.org, ip: 139.178.84.217, mailfrom: ardb@kernel.org) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id EB7BA61904; Mon, 26 Sep 2022 08:25:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0C214C4347C; Mon, 26 Sep 2022 08:25:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1664180728; bh=5TuYyVTR6g8/u9EYEvJ9sS79OBYDbxzbdnb3K8AGVo4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nU+A3YJt04jZeyp7GMQTtPHn+kfUMwv6+PbHg1RWEM6hzMemjHCB5Sp6RvMZOU7Tv T+miLfF1+Bu/+zu9GkRumqa3zthHj55zlmt/XqKBXAPQCn794h7CctLLOdxMw5RJ/t 1+LggRMhGSnEFQHpxoxlPkaUwrzQGXQxFhKpmYErh3y8VbSpwX16j7Ry1riEU7GjYC NKMktn2zz3gueUZwCPsm7pX8l2csb1ZMBm39VojtI/g6afwgxchLXTV436cBc0S/xb b9Xw+tGfpuxpXk+bhRBwRoIDb8gxr3AMW3VRLkSliiCyAn2TsjE8fiSuiM+LNW/6n3 byIEKkUh0xoxA== From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Alexander Graf Subject: [PATCH v3 07/16] ArmPkg/ArmMmuLib: permit initial configuration with MMU enabled Date: Mon, 26 Sep 2022 10:25:02 +0200 Message-Id: <20220926082511.2110797-8-ardb@kernel.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220926082511.2110797-1-ardb@kernel.org> References: <20220926082511.2110797-1-ardb@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Permit the use of this library with the MMU and caches already enabled. This removes the need for any cache maintenance for coherency, and is generally better for robustness and performance, especially when running under virtualization. Note that this means we have to defer assignment of TTBR0 until the page tables are ready to be used, and so UpdateRegionMapping() can no longer read back TTBR0 directly to discover the root table address. Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 48 +++++++++++--------- 1 file changed, 26 insertions(+), 22 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Libr= ary/ArmMmuLib/AArch64/ArmMmuLibCore.c index 4d75788ed2b2..ae59e9a7d04e 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -357,6 +357,7 @@ UpdateRegionMapping ( IN UINT64 RegionLength,=0D IN UINT64 AttributeSetMask,=0D IN UINT64 AttributeClearMask,=0D + IN UINT64 *RootTable,=0D IN BOOLEAN TableIsLive=0D )=0D {=0D @@ -373,7 +374,7 @@ UpdateRegionMapping ( RegionStart + RegionLength,=0D AttributeSetMask,=0D AttributeClearMask,=0D - ArmGetTTBR0BaseAddress (),=0D + RootTable,=0D GetRootTableLevel (T0SZ),=0D TableIsLive=0D );=0D @@ -391,6 +392,7 @@ FillTranslationTable ( MemoryRegion->Length,=0D ArmMemoryAttributeToPageAttribute (MemoryRegion->Attributes) | = TT_AF,=0D 0,=0D + RootTable,=0D FALSE=0D );=0D }=0D @@ -466,6 +468,7 @@ ArmSetMemoryAttributes ( Length,=0D PageAttributes,=0D PageAttributeMask,=0D + ArmGetTTBR0BaseAddress (),=0D TRUE=0D );=0D }=0D @@ -484,6 +487,7 @@ SetMemoryRegionAttribute ( Length,=0D Attributes,=0D BlockEntryMask,=0D + ArmGetTTBR0BaseAddress (),=0D TRUE=0D );=0D }=0D @@ -675,14 +679,6 @@ ArmConfigureMmu ( return EFI_OUT_OF_RESOURCES;=0D }=0D =0D - //=0D - // We set TTBR0 just after allocating the table to retrieve its location= from=0D - // the subsequent functions without needing to pass this value across th= e=0D - // functions. The MMU is only enabled after the translation tables are=0D - // populated.=0D - //=0D - ArmSetTTBR0 (TranslationTable);=0D -=0D if (TranslationTableBase !=3D NULL) {=0D *TranslationTableBase =3D TranslationTable;=0D }=0D @@ -691,14 +687,17 @@ ArmConfigureMmu ( *TranslationTableSize =3D RootTableEntryCount * sizeof (UINT64);=0D }=0D =0D - //=0D - // Make sure we are not inadvertently hitting in the caches=0D - // when populating the page tables.=0D - //=0D - InvalidateDataCacheRange (=0D - TranslationTable,=0D - RootTableEntryCount * sizeof (UINT64)=0D - );=0D + if (!ArmMmuEnabled ()) {=0D + //=0D + // Make sure we are not inadvertently hitting in the caches=0D + // when populating the page tables.=0D + //=0D + InvalidateDataCacheRange (=0D + TranslationTable,=0D + RootTableEntryCount * sizeof (UINT64)=0D + );=0D + }=0D +=0D ZeroMem (TranslationTable, RootTableEntryCount * sizeof (UINT64));=0D =0D while (MemoryTable->Length !=3D 0) {=0D @@ -723,12 +722,17 @@ ArmConfigureMmu ( MAIR_ATTR (TT_ATTR_INDX_MEMORY_WRITE_BACK, MAIR_ATTR_NORMAL_MEMORY_WRI= TE_BACK)=0D );=0D =0D - ArmDisableAlignmentCheck ();=0D - ArmEnableStackAlignmentCheck ();=0D - ArmEnableInstructionCache ();=0D - ArmEnableDataCache ();=0D + ArmSetTTBR0 (TranslationTable);=0D +=0D + if (!ArmMmuEnabled ()) {=0D + ArmDisableAlignmentCheck ();=0D + ArmEnableStackAlignmentCheck ();=0D + ArmEnableInstructionCache ();=0D + ArmEnableDataCache ();=0D +=0D + ArmEnableMmu ();=0D + }=0D =0D - ArmEnableMmu ();=0D return EFI_SUCCESS;=0D =0D FreeTranslationTable:=0D --=20 2.35.1