From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web09.9613.1664277275137850335 for ; Tue, 27 Sep 2022 04:14:35 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from code-server.gen (unknown [10.2.9.245]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cxrmv02jJjirsiAA--.49762S25; Tue, 27 Sep 2022 19:14:33 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [PATCH v3 23/34] MdePkg/Include: LoongArch definitions. Date: Tue, 27 Sep 2022 19:13:43 +0800 Message-Id: <20220927111354.4107719-24-lichao@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220927111354.4107719-1-lichao@loongson.cn> References: <20220927111354.4107719-1-lichao@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Cxrmv02jJjirsiAA--.49762S25 X-Coremail-Antispam: 1UD129KBjvJXoW3trWrAr17tF1kuw47XFyUAwb_yoWkXw48pF 10kFZ7Ka47KFZ3Ww1rGF1j9rn7Grs7G34UG3yDur4vkFWqv34vgw4DKF4fJrWDZr4kK340 vwnYy3yUur1xt3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQACCGMxll4dbgAisA Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053 Add LoongArch processor related definitions. For the Http boot and PXE boot types seeing this URL section "Processor Architecture Type" for the LOONGARCH values: https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml For definitions of PE/COFF and LOONGARCH relocation types, see the "Machine Types" and "Basic Relocation Types" sections of this URL for LOONGARCH values: https://docs.microsoft.com/en-us/windows/win32/debug/pe-format For the register definitions of exceptions context, see the UEFI V2.10 18.2.2, 18.2.4 and 18.2.5 sections of this URL for LOONGARCH definitions: https://uefi.org/specs/UEFI/2.10/18_Protocols_Debugger_Support.html Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Reviewed-by: Michael D Kinney Reviewed-by: Liming Gao --- MdePkg/Include/IndustryStandard/PeImage.h | 9 ++ MdePkg/Include/Protocol/DebugSupport.h | 107 ++++++++++++++++++++-- MdePkg/Include/Protocol/PxeBaseCode.h | 3 + MdePkg/Include/Uefi/UefiBaseType.h | 14 +++ MdePkg/Include/Uefi/UefiSpec.h | 16 ++-- 5 files changed, 136 insertions(+), 13 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/Ind= ustryStandard/PeImage.h index 3109dc20f8..dd4cc25483 100644 --- a/MdePkg/Include/IndustryStandard/PeImage.h +++ b/MdePkg/Include/IndustryStandard/PeImage.h @@ -10,6 +10,7 @@ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
=0D Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development= LP. All rights reserved.
=0D +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights reserved.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -38,6 +39,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define IMAGE_FILE_MACHINE_RISCV32 0x5032=0D #define IMAGE_FILE_MACHINE_RISCV64 0x5064=0D #define IMAGE_FILE_MACHINE_RISCV128 0x5128=0D +#define IMAGE_FILE_MACHINE_LOONGARCH32 0x6232=0D +#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264=0D =0D //=0D // EXE file formats=0D @@ -503,6 +506,12 @@ typedef struct { #define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7=0D #define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8=0D =0D +//=0D +// Relocation types of LoongArch processor.=0D +//=0D +#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8=0D +#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8=0D +=0D ///=0D /// Line number format.=0D ///=0D diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protoc= ol/DebugSupport.h index ec5b92a5c5..2b0ae2d157 100644 --- a/MdePkg/Include/Protocol/DebugSupport.h +++ b/MdePkg/Include/Protocol/DebugSupport.h @@ -654,17 +654,110 @@ typedef struct { UINT64 X31;=0D } EFI_SYSTEM_CONTEXT_RISCV64;=0D =0D +//=0D +// LoongArch processor exception types.=0D +//=0D +#define EXCEPT_LOONGARCH_INT 0=0D +#define EXCEPT_LOONGARCH_PIL 1=0D +#define EXCEPT_LOONGARCH_PIS 2=0D +#define EXCEPT_LOONGARCH_PIF 3=0D +#define EXCEPT_LOONGARCH_PME 4=0D +#define EXCEPT_LOONGARCH_PNR 5=0D +#define EXCEPT_LOONGARCH_PNX 6=0D +#define EXCEPT_LOONGARCH_PPI 7=0D +#define EXCEPT_LOONGARCH_ADE 8=0D +#define EXCEPT_LOONGARCH_ALE 9=0D +#define EXCEPT_LOONGARCH_BCE 10=0D +#define EXCEPT_LOONGARCH_SYS 11=0D +#define EXCEPT_LOONGARCH_BRK 12=0D +#define EXCEPT_LOONGARCH_INE 13=0D +#define EXCEPT_LOONGARCH_IPE 14=0D +#define EXCEPT_LOONGARCH_FPD 15=0D +#define EXCEPT_LOONGARCH_SXD 16=0D +#define EXCEPT_LOONGARCH_ASXD 17=0D +#define EXCEPT_LOONGARCH_FPE 18=0D +#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type = in the ISA spec, the TLB refill is defined for an independent exception.=0D +=0D +//=0D +// LoongArch processor Interrupt types.=0D +//=0D +#define EXCEPT_LOONGARCH_INT_SIP0 0=0D +#define EXCEPT_LOONGARCH_INT_SIP1 1=0D +#define EXCEPT_LOONGARCH_INT_IP0 2=0D +#define EXCEPT_LOONGARCH_INT_IP1 3=0D +#define EXCEPT_LOONGARCH_INT_IP2 4=0D +#define EXCEPT_LOONGARCH_INT_IP3 5=0D +#define EXCEPT_LOONGARCH_INT_IP4 6=0D +#define EXCEPT_LOONGARCH_INT_IP5 7=0D +#define EXCEPT_LOONGARCH_INT_IP6 8=0D +#define EXCEPT_LOONGARCH_INT_IP7 9=0D +#define EXCEPT_LOONGARCH_INT_PMC 10=0D +#define EXCEPT_LOONGARCH_INT_TIMER 11=0D +#define EXCEPT_LOONGARCH_INT_IPI 12=0D +=0D +//=0D +// For coding convenience, define the maximum valid=0D +// LoongArch interrupt.=0D +//=0D +#define MAX_LOONGARCH_INTERRUPT 14=0D +=0D +typedef struct {=0D + UINT64 R0;=0D + UINT64 R1;=0D + UINT64 R2;=0D + UINT64 R3;=0D + UINT64 R4;=0D + UINT64 R5;=0D + UINT64 R6;=0D + UINT64 R7;=0D + UINT64 R8;=0D + UINT64 R9;=0D + UINT64 R10;=0D + UINT64 R11;=0D + UINT64 R12;=0D + UINT64 R13;=0D + UINT64 R14;=0D + UINT64 R15;=0D + UINT64 R16;=0D + UINT64 R17;=0D + UINT64 R18;=0D + UINT64 R19;=0D + UINT64 R20;=0D + UINT64 R21;=0D + UINT64 R22;=0D + UINT64 R23;=0D + UINT64 R24;=0D + UINT64 R25;=0D + UINT64 R26;=0D + UINT64 R27;=0D + UINT64 R28;=0D + UINT64 R29;=0D + UINT64 R30;=0D + UINT64 R31;=0D +=0D + UINT64 CRMD; // CuRrent MoDe information=0D + UINT64 PRMD; // PRe-exception MoDe information=0D + UINT64 EUEN; // Extended component Unit ENable=0D + UINT64 MISC; // MISCellaneous controller=0D + UINT64 ECFG; // Exception ConFiGuration=0D + UINT64 ESTAT; // Exception STATus=0D + UINT64 ERA; // Exception Return Address=0D + UINT64 BADV; // BAD Virtual address=0D + UINT64 BADI; // BAD Instruction=0D +} EFI_SYSTEM_CONTEXT_LOONGARCH64;=0D +=0D ///=0D /// Universal EFI_SYSTEM_CONTEXT definition.=0D ///=0D typedef union {=0D - EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;=0D - EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;=0D - EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;=0D - EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;=0D - EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;=0D - EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;=0D - EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;=0D + EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;=0D + EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;=0D + EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;=0D + EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;=0D + EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;=0D + EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;=0D + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;=0D + EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLoongArch64;=0D } EFI_SYSTEM_CONTEXT;=0D =0D //=0D diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protoco= l/PxeBaseCode.h index 11872d602d..6787941a5d 100644 --- a/MdePkg/Include/Protocol/PxeBaseCode.h +++ b/MdePkg/Include/Protocol/PxeBaseCode.h @@ -4,6 +4,7 @@ =0D Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
=0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.
=0D +Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re= served.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -158,6 +159,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT; #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B=0D #elif defined (MDE_CPU_RISCV64)=0D #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B=0D +#elif defined (MDE_CPU_LOONGARCH64)=0D +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0027=0D #endif=0D =0D ///=0D diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiB= aseType.h index 4a34ce8e25..83975a08eb 100644 --- a/MdePkg/Include/Uefi/UefiBaseType.h +++ b/MdePkg/Include/Uefi/UefiBaseType.h @@ -4,6 +4,7 @@ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
=0D Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.
=0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.
=0D +Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re= served.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -246,6 +247,12 @@ typedef union { #define EFI_IMAGE_MACHINE_RISCV64 0x5064=0D #define EFI_IMAGE_MACHINE_RISCV128 0x5128=0D =0D +///=0D +/// PE32+ Machine type for LoongArch 32/64 images.=0D +///=0D +#define EFI_IMAGE_MACHINE_LOONGARCH32 0x6232=0D +#define EFI_IMAGE_MACHINE_LOONGARCH64 0x6264=0D +=0D #if !defined (EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined (EFI_IMAGE_MACHINE= _CROSS_TYPE_VALUE)=0D #if defined (MDE_CPU_IA32)=0D =0D @@ -278,6 +285,13 @@ typedef union { #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \=0D ((Machine) =3D=3D EFI_IMAGE_MACHINE_RISCV64)=0D =0D +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)=0D +=0D + #elif defined (MDE_CPU_LOONGARCH64)=0D +=0D +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \=0D + ((Machine) =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64)=0D +=0D #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)=0D =0D #elif defined (MDE_CPU_EBC)=0D diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h index 2b38b100f6..3abebbb8d9 100644 --- a/MdePkg/Include/Uefi/UefiSpec.h +++ b/MdePkg/Include/Uefi/UefiSpec.h @@ -7,6 +7,7 @@ =0D Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
=0D Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.
=0D +Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re= served.
=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -2195,12 +2196,13 @@ typedef struct { //=0D // EFI File location to boot from on removable media devices=0D //=0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI= "=0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI= "=0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"= =0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"= =0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI= "=0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.= EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32= .EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64= .EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.= EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.= EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64= .EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISC= V64.EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_LOONGARCH64 L"\\EFI\\BOOT\\BOOTLOON= GARCH64.EFI"=0D =0D #if !defined (EFI_REMOVABLE_MEDIA_FILE_NAME)=0D #if defined (MDE_CPU_IA32)=0D @@ -2214,6 +2216,8 @@ typedef struct { #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH= 64=0D #elif defined (MDE_CPU_RISCV64)=0D #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV= 64=0D + #elif defined (MDE_CPU_LOONGARCH64)=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_LOONG= ARCH64=0D #else=0D #error Unknown Processor Type=0D #endif=0D --=20 2.27.0