* [PATCH v3 01/34] MdePkg: Added file of DebugSupport.h to MdePkg.ci.yaml
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 02/34] MdePkg: Added LoongArch jump buffer register definition " Chao Li
` (32 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
DebugSupport.h is all defined by UEFI Spec, most of the code
doesn't fit EDKII coding style, add it to IgnoreFiles field to
make CI ECC check pass.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/MdePkg.ci.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 054233ebc7..9d141aa3cb 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -52,6 +52,7 @@
"Include/IndustryStandard/UefiTcgPlatform.h",
"Include/Library/PcdLib.h",
"Include/Library/SafeIntLib.h",
+ "Include/Protocol/DebugSupport.h",
"Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c"
]
},
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 02/34] MdePkg: Added LoongArch jump buffer register definition to MdePkg.ci.yaml
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
2022-09-27 11:13 ` [PATCH v3 01/34] MdePkg: Added file of DebugSupport.h to MdePkg.ci.yaml Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 03/34] FatPkg: Add LOONGARCH64 architecture for EDK2 CI Chao Li
` (31 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
If the new Arch register is defined in BaseLib.h when running
the CI tests, it will give an ECC check error. Add the
LoongArch register defined in the IgnoreFiles field to make
the CI ECC check pass.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/MdePkg.ci.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 9d141aa3cb..19bc0138cb 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -27,6 +27,18 @@
"8005", "void",
"8005", "va_list.__ap",
"8005", "__stack_chk_guard",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S0",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S1",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S2",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S3",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S4",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S5",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S6",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S7",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S8",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.SP",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.FP",
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.RA",
"8001", "MSG_IPv6_DP",
"8001", "MSG_IPv4_DP",
"8001", "DEFAULT_ToS",
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 03/34] FatPkg: Add LOONGARCH64 architecture for EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
2022-09-27 11:13 ` [PATCH v3 01/34] MdePkg: Added file of DebugSupport.h to MdePkg.ci.yaml Chao Li
2022-09-27 11:13 ` [PATCH v3 02/34] MdePkg: Added LoongArch jump buffer register definition " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 04/34] FmpDevicePkg: " Chao Li
` (30 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Ray Ni, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH64 architecture for EDK2 CI testing.
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
FatPkg/FatPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/FatPkg/FatPkg.dsc b/FatPkg/FatPkg.dsc
index 6fa439e440..076b577972 100644
--- a/FatPkg/FatPkg.dsc
+++ b/FatPkg/FatPkg.dsc
@@ -5,6 +5,7 @@
# for EDK II Prime release.
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -15,7 +16,7 @@
PLATFORM_GUID = 25b55dbc-9d0b-4a32-80da-46e1273d622c
PLATFORM_VERSION = 0.3
DSC_SPECIFICATION = 0x00010005
- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
OUTPUT_DIRECTORY = Build/Fat
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 04/34] FmpDevicePkg: Add LOONGARCH64 architecture for EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (2 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 03/34] FatPkg: Add LOONGARCH64 architecture for EDK2 CI Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 05/34] NetworkPkg: " Chao Li
` (29 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Liming Gao, Michael D Kinney, Guomin Jiang, Wei6 Xu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH64 architecture for EDK2 CI testing.
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Cc: Wei6 Xu <wei6.xu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
FmpDevicePkg/FmpDevicePkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/FmpDevicePkg/FmpDevicePkg.dsc b/FmpDevicePkg/FmpDevicePkg.dsc
index 7b1af285dd..f9f26c54bb 100644
--- a/FmpDevicePkg/FmpDevicePkg.dsc
+++ b/FmpDevicePkg/FmpDevicePkg.dsc
@@ -9,6 +9,7 @@
# Copyright (c) Microsoft Corporation.<BR>
# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -20,7 +21,7 @@
PLATFORM_VERSION = 0.1
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/FmpDevicePkg
- SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64
+ SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64|LOONGARCH64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 05/34] NetworkPkg: Add LOONGARCH64 architecture for EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (3 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 04/34] FmpDevicePkg: " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 06/34] NetworkPkg/HttpBootDxe: " Chao Li
` (28 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Maciej Rabeda, Jiaxin Wu, Siyuan Fu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH64 architecture for EDK2 CI testing.
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
---
NetworkPkg/NetworkPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/NetworkPkg/NetworkPkg.dsc b/NetworkPkg/NetworkPkg.dsc
index 762134023d..6c231c97b5 100644
--- a/NetworkPkg/NetworkPkg.dsc
+++ b/NetworkPkg/NetworkPkg.dsc
@@ -4,6 +4,7 @@
# (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>
# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -14,7 +15,7 @@
PLATFORM_VERSION = 0.98
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/NetworkPkg
- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 06/34] NetworkPkg/HttpBootDxe: Add LOONGARCH64 architecture for EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (4 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 05/34] NetworkPkg: " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 07/34] CryptoPkg: " Chao Li
` (27 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Maciej Rabeda, Jiaxin Wu, Siyuan Fu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH architecture for EDK2 CI testing.
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Jiaxin Wu <jiaxin.wu@intel.com>
---
NetworkPkg/HttpBootDxe/HttpBootDhcp4.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h b/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h
index d76f0e84d6..f00fabead2 100644
--- a/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h
+++ b/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h
@@ -3,6 +3,7 @@
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -40,6 +41,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define EFI_HTTP_BOOT_CLIENT_SYSTEM_ARCHITECTURE HTTP_CLIENT_ARCH_RISCV64
#elif defined (MDE_CPU_EBC)
#define EFI_HTTP_BOOT_CLIENT_SYSTEM_ARCHITECTURE HTTP_CLIENT_ARCH_EBC
+#elif defined (MDE_CPU_LOONGARCH64)
+#define EFI_HTTP_BOOT_CLIENT_SYSTEM_ARCHITECTURE HTTP_CLIENT_ARCH_LOONGARCH64
#endif
/// DHCP offer types among HTTP boot.
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 07/34] CryptoPkg: Add LOONGARCH64 architecture for EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (5 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 06/34] NetworkPkg/HttpBootDxe: " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 08/34] MdePkg/Include: Add LOONGARCH related definitions " Chao Li
` (26 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Jiewen Yao, Jian J Wang, Xiaoyu Lu, Guomin Jiang, Jiewen Yao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH64 architecture for EDK2 CI testing.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Xiaoyu Lu <xiaoyu1.lu@intel.com>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
---
CryptoPkg/CryptoPkg.dsc | 3 ++-
CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf | 6 +++++-
CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf | 4 ++++
CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf | 3 ++-
CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf | 3 ++-
CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf | 3 ++-
CryptoPkg/Library/Include/CrtLibSupport.h | 3 ++-
CryptoPkg/Library/OpensslLib/OpensslLib.inf | 2 ++
CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf | 2 ++
CryptoPkg/Library/TlsLib/TlsLib.inf | 3 ++-
CryptoPkg/Library/TlsLibNull/TlsLibNull.inf | 3 ++-
11 files changed, 27 insertions(+), 8 deletions(-)
diff --git a/CryptoPkg/CryptoPkg.dsc b/CryptoPkg/CryptoPkg.dsc
index e4e7bc0dbf..8c6906acf0 100644
--- a/CryptoPkg/CryptoPkg.dsc
+++ b/CryptoPkg/CryptoPkg.dsc
@@ -4,6 +4,7 @@
#
# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -19,7 +20,7 @@
PLATFORM_VERSION = 0.98
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/CryptoPkg
- SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64
+ SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64|LOONGARCH64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
diff --git a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf b/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
index 9634bd5fea..8896e47095 100644
--- a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
@@ -8,6 +8,7 @@
#
# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -24,7 +25,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
@@ -78,6 +79,9 @@
[Sources.RISCV64]
Rand/CryptRand.c
+[Sources.LOONGARCH64]
+ Rand/CryptRand.c
+
[Packages]
MdePkg/MdePkg.dec
CryptoPkg/CryptoPkg.dec
diff --git a/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf b/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
index 845708bf1a..bb66604e32 100644
--- a/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
@@ -13,6 +13,7 @@
#
# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -80,6 +81,9 @@
[Sources.RISCV64]
Rand/CryptRand.c
+[Sources.LOONGARCH64]
+ Rand/CryptRand.c
+
[Packages]
MdePkg/MdePkg.dec
CryptoPkg/CryptoPkg.dec
diff --git a/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf b/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf
index 9cb8d42ff4..80afb62f76 100644
--- a/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf
+++ b/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf
@@ -8,6 +8,7 @@
#
# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -24,7 +25,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
diff --git a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
index baa4433cbe..b4945de336 100644
--- a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
@@ -4,6 +4,7 @@
#
# Copyright (C) Microsoft Corporation. All rights reserved.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -22,7 +23,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
#
[Packages]
diff --git a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf
index 038ca71890..e7d153db0b 100644
--- a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf
@@ -4,6 +4,7 @@
#
# Copyright (C) Microsoft Corporation. All rights reserved.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -21,7 +22,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
#
[Packages]
diff --git a/CryptoPkg/Library/Include/CrtLibSupport.h b/CryptoPkg/Library/Include/CrtLibSupport.h
index e49060124f..5072c343da 100644
--- a/CryptoPkg/Library/Include/CrtLibSupport.h
+++ b/CryptoPkg/Library/Include/CrtLibSupport.h
@@ -4,6 +4,7 @@
Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -46,7 +47,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define CONFIG_HEADER_BN_H
#if !defined (SIXTY_FOUR_BIT) && !defined (THIRTY_TWO_BIT)
- #if defined (MDE_CPU_X64) || defined (MDE_CPU_AARCH64) || defined (MDE_CPU_IA64) || defined (MDE_CPU_RISCV64)
+ #if defined (MDE_CPU_X64) || defined (MDE_CPU_AARCH64) || defined (MDE_CPU_IA64) || defined (MDE_CPU_RISCV64) || defined (MDE_CPU_LOONGARCH64)
//
// With GCC we would normally use SIXTY_FOUR_BIT_LONG, but MSVC needs
// SIXTY_FOUR_BIT, because 'long' is 32-bit and only 'long long' is
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLib.inf b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
index c899b811b1..f0ca72eeed 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -675,6 +676,7 @@
GCC:*_*_ARM_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-error=unused-but-set-variable
GCC:*_*_AARCH64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
GCC:*_*_RISCV64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
+ GCC:*_*_LOONGARCH64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
GCC:*_CLANG35_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized
GCC:*_CLANG38_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized
GCC:*_CLANGPDB_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized -Wno-error=incompatible-pointer-types -Wno-error=pointer-sign -Wno-error=implicit-function-declaration -Wno-error=ignored-pragma-optimize
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
index 0ec3724541..195016fd3d 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -624,6 +625,7 @@
GCC:*_*_ARM_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-error=unused-but-set-variable
GCC:*_*_AARCH64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
GCC:*_*_RISCV64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
+ GCC:*_*_LOONGARCH64_CC_FLAGS = $(OPENSSL_FLAGS) -Wno-error=maybe-uninitialized -Wno-format -Wno-error=unused-but-set-variable
GCC:*_CLANG35_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized
GCC:*_CLANG38_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized
GCC:*_CLANGPDB_*_CC_FLAGS = -std=c99 -Wno-error=uninitialized -Wno-error=incompatible-pointer-types -Wno-error=pointer-sign -Wno-error=implicit-function-declaration -Wno-error=ignored-pragma-optimize
diff --git a/CryptoPkg/Library/TlsLib/TlsLib.inf b/CryptoPkg/Library/TlsLib/TlsLib.inf
index bc61cda745..20b0ea6832 100644
--- a/CryptoPkg/Library/TlsLib/TlsLib.inf
+++ b/CryptoPkg/Library/TlsLib/TlsLib.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2016-2020 Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -19,7 +20,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
diff --git a/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf b/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf
index b2920ddacf..12d7cc764a 100644
--- a/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf
+++ b/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2016-2020 Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -19,7 +20,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 08/34] MdePkg/Include: Add LOONGARCH related definitions EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (6 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 07/34] CryptoPkg: " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 09/34] SecurityPkg: Add LOONGARCH64 architecture for " Chao Li
` (25 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
HTTP/PXE boot LOONGARCH64 related definitions for EDK2 CI.
For the LOONGARCH values, please seeing following URL section
"Processor Architecture Types":
https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/Include/IndustryStandard/Dhcp.h | 45 ++++++++++++++------------
1 file changed, 25 insertions(+), 20 deletions(-)
diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/IndustryStandard/Dhcp.h
index f209f1b2eb..46ab4f8e75 100644
--- a/MdePkg/Include/IndustryStandard/Dhcp.h
+++ b/MdePkg/Include/IndustryStandard/Dhcp.h
@@ -4,6 +4,7 @@
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -256,27 +257,31 @@ typedef enum {
///
/// Processor Architecture Types
-/// These identifiers are defined by IETF:
-/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml
+/// These identifiers are defined by IANA:
+/// https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml
///
-#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE
-#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE
-#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE
-#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE
-#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
-#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
-#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
-#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
-#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
-#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
+#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE
+#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE
+#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE
+#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE
+#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE
+#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE
+#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for PXE
+#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for PXE
+#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for PXE
+#define PXE_CLIENT_ARCH_LOONGARCH32 0x0025 /// LoongArch uefi 32 for PXE
+#define PXE_CLIENT_ARCH_LOONGARCH64 0x0027 /// LoongArch uefi 64 for PXE
-#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
-#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
-#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
-#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
-#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
-#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
-#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
-#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
+#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from http
+#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from http
+#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http
+#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot from http
+#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boot from http
+#define HTTP_CLIENT_ARCH_LOONGARCH32 0x0026 /// LoongArch uefi 32 boot from http
+#define HTTP_CLIENT_ARCH_LOONGARCH64 0x0028 /// LoongArch uefi 64 boot from http
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 09/34] SecurityPkg: Add LOONGARCH64 architecture for EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (7 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 08/34] MdePkg/Include: Add LOONGARCH related definitions " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 10/34] ShellPkg: " Chao Li
` (24 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Jiewen Yao, Jian J Wang, Jiewen Yao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH64 architecture to SecurityPkg for EDK2 CI testing.
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Jiewen Yao <Jiewen.yao@intel.com>
---
SecurityPkg/SecurityPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/SecurityPkg/SecurityPkg.dsc b/SecurityPkg/SecurityPkg.dsc
index f48187650f..6bf53c5658 100644
--- a/SecurityPkg/SecurityPkg.dsc
+++ b/SecurityPkg/SecurityPkg.dsc
@@ -3,6 +3,7 @@
#
# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>
# (C) Copyright 2015-2020 Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -13,7 +14,7 @@
PLATFORM_VERSION = 0.98
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/SecurityPkg
- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 10/34] ShellPkg: Add LOONGARCH64 architecture for EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (8 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 09/34] SecurityPkg: Add LOONGARCH64 architecture for " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 11/34] UnitTestFrameworkPkg: " Chao Li
` (23 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Ray Ni, Zhichao Gao, Michael D Kinney
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH64 architecture to ShellPkg for EDK2 CI testing.
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zhichao Gao <zhichao.gao@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
---
ShellPkg/ShellPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/ShellPkg/ShellPkg.dsc b/ShellPkg/ShellPkg.dsc
index 38fde3dc71..dd0d88603f 100644
--- a/ShellPkg/ShellPkg.dsc
+++ b/ShellPkg/ShellPkg.dsc
@@ -4,6 +4,7 @@
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2018 - 2020, Arm Limited. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -15,7 +16,7 @@
PLATFORM_VERSION = 1.02
DSC_SPECIFICATION = 0x00010006
OUTPUT_DIRECTORY = Build/Shell
- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 11/34] UnitTestFrameworkPkg: Add LOONGARCH64 architecture for EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (9 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 10/34] ShellPkg: " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 12/34] MdePkg/DxeServicesLib: Add LOONGARCH64 architecture Chao Li
` (22 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH64 architecture to UnitTestFramworkPkg for LOONGARCH64 EDK2
CI.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
index 23baef87d6..e4f9fb6eb6 100644
--- a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
+++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
@@ -3,6 +3,7 @@
#
# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -14,7 +15,7 @@
PLATFORM_VERSION = 1.00
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/UnitTestFrameworkPkg
- SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64
+ SUPPORTED_ARCHITECTURES = IA32|X64|ARM|AARCH64|RISCV64|LOONGARCH64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 12/34] MdePkg/DxeServicesLib: Add LOONGARCH64 architecture
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (10 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 11/34] UnitTestFrameworkPkg: " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 13/34] MdeModulePkg: Use LockBoxNullLib for LOONGARCH64 Chao Li
` (21 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH64 architecture to MdePkg/DxeServiceLib.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/Library/DxeServicesLib/DxeServicesLib.inf | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf b/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
index ec3e8711c2..a93541847f 100644
--- a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+++ b/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
@@ -22,13 +22,13 @@
LIBRARY_CLASS = DxeServicesLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
DxeServicesLib.c
-[Sources.IA32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
+[Sources.IA32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]
Allocate.c
[Sources.X64]
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 13/34] MdeModulePkg: Use LockBoxNullLib for LOONGARCH64
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (11 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 12/34] MdePkg/DxeServicesLib: Add LOONGARCH64 architecture Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 14/34] .python/SpellCheck: Add "Loongson" and "LOONGARCH" to "words" section Chao Li
` (20 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Jian J Wang, Liming Gao, Michael D Kinney
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
LoongArch doesn't have SMM by now.
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdeModulePkg/MdeModulePkg.dsc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
index 45a8ec84ad..659482ab73 100644
--- a/MdeModulePkg/MdeModulePkg.dsc
+++ b/MdeModulePkg/MdeModulePkg.dsc
@@ -15,7 +15,7 @@
PLATFORM_VERSION = 0.98
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/MdeModule
- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
@@ -193,7 +193,7 @@
#
NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
-[LibraryClasses.EBC, LibraryClasses.RISCV64]
+[LibraryClasses.EBC, LibraryClasses.RISCV64, LibraryClasses.LOONGARCH64]
LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
[PcdsFeatureFlag]
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 14/34] .python/SpellCheck: Add "Loongson" and "LOONGARCH" to "words" section
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (12 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 13/34] MdeModulePkg: Use LockBoxNullLib for LOONGARCH64 Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 15/34] BaseTools: Update GenFw/GenFv to support LoongArch platform Chao Li
` (19 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add Loongson and LOONGARCH to "words" section in cspell.base.yaml file
to avoid spelling check error.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
.pytool/Plugin/SpellCheck/cspell.base.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/.pytool/Plugin/SpellCheck/cspell.base.yaml b/.pytool/Plugin/SpellCheck/cspell.base.yaml
index f0d5791876..92e65ec6f6 100644
--- a/.pytool/Plugin/SpellCheck/cspell.base.yaml
+++ b/.pytool/Plugin/SpellCheck/cspell.base.yaml
@@ -289,6 +289,8 @@
"unrecovered",
"cmocka",
"unenrolling",
- "unconfigure"
+ "unconfigure",
+ "Loongson",
+ "LOONGARCH"
]
}
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 15/34] BaseTools: Update GenFw/GenFv to support LoongArch platform.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (13 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 14/34] .python/SpellCheck: Add "Loongson" and "LOONGARCH" to "words" section Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 16/34] BaseTools: Updated for GCC5 tool chain for LoongArch platfrom Chao Li
` (18 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel
Cc: Bob Feng, Liming Gao, Yuwei Chen, Dongyan Qian, Baoqi Zhang,
Yang Zhou, Xiaotian Wu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
C code changes for building EDK2 LoongArch platform.
For definitions of PE/COFF and LOONGARCH relocation types, see the
"Machine Types" and "Basic Relocation Types" sections of this URL for
LOONGARCH values:
https://docs.microsoft.com/en-us/windows/win32/debug/pe-format
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Dongyan Qian <qiandongyan@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Co-authored-by: Yang Zhou <zhouyang@loongson.cn>
Co-authored-by: Xiaotian Wu <wuxiaotian@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
BaseTools/Source/C/Common/PeCoffLoaderEx.c | 79 +++++
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 125 +++++++-
BaseTools/Source/C/GenFw/Elf64Convert.c | 293 +++++++++++++++++-
BaseTools/Source/C/GenFw/elf_common.h | 94 ++++++
.../C/Include/IndustryStandard/PeImage.h | 57 ++--
| 6 +
7 files changed, 636 insertions(+), 33 deletions(-)
diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Common/BasePeCoff.c
index 62fbb2985c..30400d1341 100644
--- a/BaseTools/Source/C/Common/BasePeCoff.c
+++ b/BaseTools/Source/C/Common/BasePeCoff.c
@@ -5,6 +5,7 @@
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -68,6 +69,14 @@ PeCoffLoaderRelocateRiscVImage (
IN UINT64 Adjust
);
+RETURN_STATUS
+PeCoffLoaderRelocateLoongArch64Image (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ );
+
STATIC
RETURN_STATUS
PeCoffLoaderGetPeHeader (
@@ -184,7 +193,8 @@ Returns:
ImageContext->Machine != EFI_IMAGE_MACHINE_ARMT && \
ImageContext->Machine != EFI_IMAGE_MACHINE_EBC && \
ImageContext->Machine != EFI_IMAGE_MACHINE_AARCH64 && \
- ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64) {
+ ImageContext->Machine != EFI_IMAGE_MACHINE_RISCV64 && \
+ ImageContext->Machine != EFI_IMAGE_MACHINE_LOONGARCH64) {
if (ImageContext->Machine == IMAGE_FILE_MACHINE_ARM) {
//
// There are two types of ARM images. Pure ARM and ARM/Thumb.
@@ -815,6 +825,9 @@ Returns:
case EFI_IMAGE_MACHINE_RISCV64:
Status = PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupData, Adjust);
break;
+ case EFI_IMAGE_MACHINE_LOONGARCH64:
+ Status = PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup, &FixupData, Adjust);
+ break;
default:
Status = RETURN_UNSUPPORTED;
break;
diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
index 799f282970..2cc428d733 100644
--- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
+++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
@@ -4,6 +4,7 @@ IA32 and X64 Specific relocation fixups
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
--*/
@@ -332,3 +333,81 @@ PeCoffLoaderRelocateArmImage (
return RETURN_SUCCESS;
}
+
+/**
+ Performs a LoongArch specific relocation fixup.
+
+ @param[in] Reloc Pointer to the relocation record.
+ @param[in, out] Fixup Pointer to the address to fix up.
+ @param[in, out] FixupData Pointer to a buffer to log the fixups.
+ @param[in] Adjust The offset to adjust the fixup.
+
+ @return Status code.
+**/
+RETURN_STATUS
+PeCoffLoaderRelocateLoongArch64Image (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ UINT8 RelocType;
+ UINT64 Value;
+ UINT64 Tmp1;
+ UINT64 Tmp2;
+
+ RelocType = ((*Reloc) >> 12);
+ Value = 0;
+ Tmp1 = 0;
+ Tmp2 = 0;
+
+ switch (RelocType) {
+ case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA:
+ // The next four instructions are used to load a 64 bit address, relocate all of them
+ Value = (*(UINT32 *)Fixup & 0x1ffffe0) << 7 | // lu12i.w 20bits from bit5
+ (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori 12bits from bit10
+ Tmp1 = *((UINT32 *)Fixup + 2) & 0x1ffffe0; // lu32i.d 20bits from bit5
+ Tmp2 = *((UINT32 *)Fixup + 3) & 0x3ffc00; // lu52i.d 12bits from bit10
+ Value = Value | (Tmp1 << 27) | (Tmp2 << 42);
+ Value += Adjust;
+
+ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 12) & 0xfffff) << 5);
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
+ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
+ *FixupData = *FixupData + sizeof (UINT32);
+ }
+
+ Fixup += sizeof (UINT32);
+ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x3ffc00) | ((Value & 0xfff) << 10);
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
+ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
+ *FixupData = *FixupData + sizeof (UINT32);
+ }
+
+ Fixup += sizeof (UINT32);
+ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 32) & 0xfffff) << 5);
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
+ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
+ *FixupData = *FixupData + sizeof (UINT32);
+ }
+
+ Fixup += sizeof (UINT32);
+ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value >> 52) & 0xfff) << 10);
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
+ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
+ *FixupData = *FixupData + sizeof (UINT32);
+ }
+
+ break;
+ default:
+ Error (NULL, 0, 3000, "", "PeCoffLoaderRelocateLoongArch64Image: Fixup[0x%x] Adjust[0x%llx] *Reloc[0x%x], type[0x%x].", *(UINT32 *)Fixup, Adjust, *Reloc, RelocType);
+ return RETURN_UNSUPPORTED;
+ }
+
+ return RETURN_SUCCESS;
+}
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
index d28ac8f6eb..5c3d54f5f7 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -5,6 +5,7 @@ Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Portions Copyright (c) 2016 HP Development Company, L.P.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -57,6 +58,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
BOOLEAN mArm = FALSE;
BOOLEAN mRiscV = FALSE;
+BOOLEAN mLoongArch = FALSE;
STATIC UINT32 MaxFfsAlignment = 0;
BOOLEAN VtfFileFlag = FALSE;
@@ -2416,6 +2418,98 @@ Returns:
return EFI_SUCCESS;
}
+EFI_STATUS
+UpdateLoongArchResetVectorIfNeeded (
+ IN MEMORY_FILE *FvImage,
+ IN FV_INFO *FvInfo
+ )
+/*++
+
+Routine Description:
+ This parses the FV looking for SEC and patches that address into the
+ beginning of the FV header.
+
+ For LoongArch ISA, the reset vector is at 0x1c000000.
+
+ We relocate it to SecCoreEntry and copy the ResetVector code to the
+ beginning of the FV.
+
+Arguments:
+ FvImage Memory file for the FV memory image
+ FvInfo Information read from INF file.
+
+Returns:
+
+ EFI_SUCCESS Function Completed successfully.
+ EFI_ABORTED Error encountered.
+ EFI_INVALID_PARAMETER A required parameter was NULL.
+ EFI_NOT_FOUND PEI Core file not found.
+
+--*/
+{
+ EFI_STATUS Status;
+ EFI_FILE_SECTION_POINTER SecPe32;
+ BOOLEAN UpdateVectorSec = FALSE;
+ UINT16 MachineType = 0;
+ EFI_PHYSICAL_ADDRESS SecCoreEntryAddress = 0;
+
+ //
+ // Verify input parameters
+ //
+ if (FvImage == NULL || FvInfo == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Locate an SEC Core instance and if found extract the machine type and entry point address
+ //
+ Status = FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FILETYPE_SECURITY_CORE, &SecPe32);
+ if (!EFI_ERROR(Status)) {
+
+ Status = GetCoreMachineType(SecPe32, &MachineType);
+ if (EFI_ERROR(Status)) {
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type for SEC Core.");
+ return EFI_ABORTED;
+ }
+
+ Status = GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe32, &SecCoreEntryAddress);
+ if (EFI_ERROR(Status)) {
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point address for SEC Core.");
+ return EFI_ABORTED;
+ }
+
+ UpdateVectorSec = TRUE;
+ }
+
+ if (!UpdateVectorSec)
+ return EFI_SUCCESS;
+
+ if (MachineType == EFI_IMAGE_MACHINE_LOONGARCH64) {
+ UINT32 ResetVector[1];
+
+ memset(ResetVector, 0, sizeof (ResetVector));
+
+ /* if we found an SEC core entry point then generate a branch instruction */
+ if (UpdateVectorSec) {
+ VerboseMsg("UpdateLoongArchResetVectorIfNeeded updating LOONGARCH64 SEC vector");
+
+ ResetVector[0] = ((SecCoreEntryAddress - FvInfo->BaseAddress) & 0x3FFFFFF) >> 2;
+ ResetVector[0] = ((ResetVector[0] & 0x0FFFF) << 10) | ((ResetVector[0] >> 16) & 0x3FF);
+ ResetVector[0] |= 0x50000000; /* b offset */
+ }
+
+ //
+ // Copy to the beginning of the FV
+ //
+ memcpy(FvImage->FileImage, ResetVector, sizeof (ResetVector));
+ } else {
+ Error(NULL, 0, 3000, "Invalid", "Unknown machine type");
+ return EFI_ABORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
EFI_STATUS
GetPe32Info (
IN UINT8 *Pe32,
@@ -2509,7 +2603,7 @@ Returns:
//
if ((*MachineType != EFI_IMAGE_MACHINE_IA32) && (*MachineType != EFI_IMAGE_MACHINE_X64) && (*MachineType != EFI_IMAGE_MACHINE_EBC) &&
(*MachineType != EFI_IMAGE_MACHINE_ARMT) && (*MachineType != EFI_IMAGE_MACHINE_AARCH64) &&
- (*MachineType != EFI_IMAGE_MACHINE_RISCV64)) {
+ (*MachineType != EFI_IMAGE_MACHINE_RISCV64) && (*MachineType != EFI_IMAGE_MACHINE_LOONGARCH64)) {
Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE32 file.");
return EFI_UNSUPPORTED;
}
@@ -2953,7 +3047,7 @@ Returns:
goto Finish;
}
- if (!mArm && !mRiscV) {
+ if (!mArm && !mRiscV && !mLoongArch) {
//
// Update reset vector (SALE_ENTRY for IPF)
// Now for IA32 and IA64 platform, the fv which has bsf file must have the
@@ -3004,6 +3098,19 @@ Returns:
FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
}
+ if (mLoongArch) {
+ Status = UpdateLoongArchResetVectorIfNeeded (&FvImageMemoryFile, &mFvDataInfo);
+ if (EFI_ERROR (Status)) {
+ Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector.");
+ goto Finish;
+ }
+ //
+ // Update Checksum for FvHeader
+ //
+ FvHeader->Checksum = 0;
+ FvHeader->Checksum = CalculateChecksum16 ((UINT16 *) FvHeader, FvHeader->HeaderLength / sizeof (UINT16));
+ }
+
//
// Update FV Alignment attribute to the largest alignment of all the FFS files in the FV
//
@@ -3450,6 +3557,12 @@ Returns:
VerboseMsg("Located ARM/AArch64 SEC/PEI core in child FV");
mArm = TRUE;
}
+
+ // Machine type is LOONGARCH64, set a flag so LoongArch64 reset vector processed.
+ if ((MachineType == EFI_IMAGE_MACHINE_LOONGARCH64)) {
+ VerboseMsg("Located LoongArch64 SEC core in child FV");
+ mLoongArch = TRUE;
+ }
}
//
@@ -3608,6 +3721,10 @@ Returns:
mRiscV = TRUE;
}
+ if ( (ImageContext.Machine == EFI_IMAGE_MACHINE_LOONGARCH64) ) {
+ mLoongArch = TRUE;
+ }
+
//
// Keep Image Context for PE image in FV
//
@@ -3885,6 +4002,10 @@ Returns:
mArm = TRUE;
}
+ if ( (ImageContext.Machine == EFI_IMAGE_MACHINE_LOONGARCH64) ) {
+ mLoongArch = TRUE;
+ }
+
//
// Keep Image Context for TE image in FV
//
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index ca3c8f8bee..ede2f0ef90 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -4,6 +4,7 @@ Elf64 convert solution
Copyright (c) 2010 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2013-2022, ARM Ltd. All rights reserved.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -177,7 +178,7 @@ InitializeElf64 (
Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN");
return FALSE;
}
- if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64))) {
+ if (!((mEhdr->e_machine == EM_X86_64) || (mEhdr->e_machine == EM_AARCH64) || (mEhdr->e_machine == EM_RISCV64) || (mEhdr->e_machine == EM_LOONGARCH))) {
Warning (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 machine.");
}
if (mEhdr->e_version != EV_CURRENT) {
@@ -799,6 +800,7 @@ ScanSections64 (
case EM_X86_64:
case EM_AARCH64:
case EM_RISCV64:
+ case EM_LOONGARCH:
mCoffOffset += sizeof (EFI_IMAGE_NT_HEADERS64);
break;
default:
@@ -1088,6 +1090,10 @@ ScanSections64 (
NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_RISCV64;
NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
break;
+ case EM_LOONGARCH:
+ NtHdr->Pe32Plus.FileHeader.Machine = EFI_IMAGE_MACHINE_LOONGARCH64;
+ NtHdr->Pe32Plus.OptionalHeader.Magic = EFI_IMAGE_NT_OPTIONAL_HDR64_MAGIC;
+ break;
default:
VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_machine);
@@ -1333,10 +1339,10 @@ WriteSections64 (
}
//
- // Skip error on EM_RISCV64 becasue no symble name is built
- // from RISC-V toolchain.
+ // Skip error on EM_RISCV64 and EM_LOONGARCH because no symbol name is built
+ // from RISC-V and LoongArch toolchain.
//
- if (mEhdr->e_machine != EM_RISCV64) {
+ if ((mEhdr->e_machine != EM_RISCV64) && (mEhdr->e_machine != EM_LOONGARCH)) {
Error (NULL, 0, 3000, "Invalid",
"%s: Bad definition for symbol '%s'@%#llx or unsupported symbol type. "
"For example, absolute and undefined symbols are not supported.",
@@ -1618,6 +1624,178 @@ WriteSections64 (
// Write section for RISC-V 64 architecture.
//
WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym);
+ } else if (mEhdr->e_machine == EM_LOONGARCH) {
+ switch (ELF_R_TYPE(Rel->r_info)) {
+ INT64 Offset;
+ INT32 Lo, Hi;
+
+ case R_LARCH_SOP_PUSH_ABSOLUTE:
+ //
+ // Absolute relocation.
+ //
+ *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ break;
+
+ case R_LARCH_MARK_LA:
+ case R_LARCH_64:
+ case R_LARCH_NONE:
+ case R_LARCH_32:
+ case R_LARCH_RELATIVE:
+ case R_LARCH_COPY:
+ case R_LARCH_JUMP_SLOT:
+ case R_LARCH_TLS_DTPMOD32:
+ case R_LARCH_TLS_DTPMOD64:
+ case R_LARCH_TLS_DTPREL32:
+ case R_LARCH_TLS_DTPREL64:
+ case R_LARCH_TLS_TPREL32:
+ case R_LARCH_TLS_TPREL64:
+ case R_LARCH_IRELATIVE:
+ case R_LARCH_MARK_PCREL:
+ case R_LARCH_SOP_PUSH_PCREL:
+ case R_LARCH_SOP_PUSH_DUP:
+ case R_LARCH_SOP_PUSH_GPREL:
+ case R_LARCH_SOP_PUSH_TLS_TPREL:
+ case R_LARCH_SOP_PUSH_TLS_GOT:
+ case R_LARCH_SOP_PUSH_TLS_GD:
+ case R_LARCH_SOP_PUSH_PLT_PCREL:
+ case R_LARCH_SOP_ASSERT:
+ case R_LARCH_SOP_NOT:
+ case R_LARCH_SOP_SUB:
+ case R_LARCH_SOP_SL:
+ case R_LARCH_SOP_SR:
+ case R_LARCH_SOP_ADD:
+ case R_LARCH_SOP_AND:
+ case R_LARCH_SOP_IF_ELSE:
+ case R_LARCH_SOP_POP_32_S_10_5:
+ case R_LARCH_SOP_POP_32_U_10_12:
+ case R_LARCH_SOP_POP_32_S_10_12:
+ case R_LARCH_SOP_POP_32_S_10_16:
+ case R_LARCH_SOP_POP_32_S_10_16_S2:
+ case R_LARCH_SOP_POP_32_S_5_20:
+ case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:
+ case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:
+ case R_LARCH_SOP_POP_32_U:
+ case R_LARCH_ADD8:
+ case R_LARCH_ADD16:
+ case R_LARCH_ADD24:
+ case R_LARCH_ADD32:
+ case R_LARCH_ADD64:
+ case R_LARCH_SUB8:
+ case R_LARCH_SUB16:
+ case R_LARCH_SUB24:
+ case R_LARCH_SUB32:
+ case R_LARCH_SUB64:
+ case R_LARCH_GNU_VTINHERIT:
+ case R_LARCH_GNU_VTENTRY:
+ case R_LARCH_B16:
+ case R_LARCH_B21:
+ case R_LARCH_B26:
+ case R_LARCH_ABS_HI20:
+ case R_LARCH_ABS_LO12:
+ case R_LARCH_ABS64_LO20:
+ case R_LARCH_ABS64_HI12:
+ case R_LARCH_PCALA_LO12:
+ case R_LARCH_PCALA64_LO20:
+ case R_LARCH_PCALA64_HI12:
+ case R_LARCH_GOT_PC_LO12:
+ case R_LARCH_GOT64_PC_LO20:
+ case R_LARCH_GOT64_PC_HI12:
+ case R_LARCH_GOT64_HI20:
+ case R_LARCH_GOT64_LO12:
+ case R_LARCH_GOT64_LO20:
+ case R_LARCH_GOT64_HI12:
+ case R_LARCH_TLS_LE_HI20:
+ case R_LARCH_TLS_LE_LO12:
+ case R_LARCH_TLS_LE64_LO20:
+ case R_LARCH_TLS_LE64_HI12:
+ case R_LARCH_TLS_IE_PC_HI20:
+ case R_LARCH_TLS_IE_PC_LO12:
+ case R_LARCH_TLS_IE64_PC_LO20:
+ case R_LARCH_TLS_IE64_PC_HI12:
+ case R_LARCH_TLS_IE64_HI20:
+ case R_LARCH_TLS_IE64_LO12:
+ case R_LARCH_TLS_IE64_LO20:
+ case R_LARCH_TLS_IE64_HI12:
+ case R_LARCH_TLS_LD_PC_HI20:
+ case R_LARCH_TLS_LD64_HI20:
+ case R_LARCH_TLS_GD_PC_HI20:
+ case R_LARCH_TLS_GD64_HI20:
+ case R_LARCH_RELAX:
+ //
+ // These types are not used or do not require fixup.
+ //
+ break;
+
+ case R_LARCH_GOT_PC_HI20:
+ Offset = Sym->st_value - (UINTN)(Targ - mCoffFile);
+ if (Offset < 0) {
+ Offset = (UINTN)(Targ - mCoffFile) - Sym->st_value;
+ Hi = (Offset / 0x1000) << 12;
+ Lo = (INT32)((Offset & 0xfff) << 20) >> 20;
+ if ((Lo < 0) && (Lo > -2048)) {
+ Hi += 0x1000;
+ Lo = ~(0x1000 - Lo) + 1;
+ }
+ Hi = ~Hi + 1;
+ Lo = ~Lo + 1;
+ } else {
+ Hi = (Offset / 0x1000) << 12;
+ Lo = (INT32)((Offset & 0xfff) << 20) >> 20;
+ if (Lo < 0) {
+ Hi += 0x1000;
+ Lo = ~(0x1000 - Lo) + 1;
+ }
+ }
+ // Re-encode the offset as an PCADD.D + ADDI.D(Convert LD.D) instruction
+ *(UINT32 *)Targ &= 0x1f;
+ *(UINT32 *)Targ |= 0x1c000000;
+ *(UINT32 *)Targ |= (((Hi >> 12) & 0xfffff) << 5);
+ *(UINT32 *)(Targ + 4) &= 0x3ff;
+ *(UINT32 *)(Targ + 4) |= 0x2c00000 | ((Lo & 0xfff) << 10);
+ break;
+
+ //
+ // Attempt to convert instruction.
+ //
+ case R_LARCH_PCALA_HI20:
+ // Decode the PCALAU12I + ADDI.D instruction
+ Offset = ((INT32)((*(UINT32 *)Targ & 0x1ffffe0) << 7));
+ Offset += ((INT32)((*(UINT32 *)(Targ + 4) & 0x3ffc00) << 10) >> 20);
+ //
+ // PCALA offset is relative to the previous page boundary,
+ // whereas PCADD offset is relative to the instruction itself.
+ // So fix up the offset so it points to the page containing
+ // the symbol.
+ //
+ Offset -= (UINTN)(Targ - mCoffFile) & 0xfff;
+ if (Offset < 0) {
+ Offset = -Offset;
+ Hi = (Offset / 0x1000) << 12;
+ Lo = (INT32)((Offset & 0xfff) << 20) >> 20;
+ if ((Lo < 0) && (Lo > -2048)) {
+ Hi += 0x1000;
+ Lo = ~(0x1000 - Lo) + 1;
+ }
+ Hi = ~Hi + 1;
+ Lo = ~Lo + 1;
+ } else {
+ Hi = (Offset / 0x1000) << 12;
+ Lo = (INT32)((Offset & 0xfff) << 20) >> 20;
+ if (Lo < 0) {
+ Hi += 0x1000;
+ Lo = ~(0x1000 - Lo) + 1;
+ }
+ }
+ // Re-encode the offset as an PCADD.D + ADDI.D instruction
+ *(UINT32 *)Targ &= 0x1f;
+ *(UINT32 *)Targ |= 0x1c000000;
+ *(UINT32 *)Targ |= (((Hi >> 12) & 0xfffff) << 5);
+ *(UINT32 *)(Targ + 4) &= 0xffc003ff;
+ *(UINT32 *)(Targ + 4) |= (Lo & 0xfff) << 10;
+ break;
+ default:
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupported ELF EM_LOONGARCH relocation 0x%x.", mInImageName, (unsigned) ELF64_R_TYPE(Rel->r_info));
+ }
} else {
Error (NULL, 0, 3000, "Invalid", "Not a supported machine type");
}
@@ -1850,6 +2028,113 @@ WriteRelocations64 (
default:
Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R_TYPE(Rel->r_info));
}
+ } else if (mEhdr->e_machine == EM_LOONGARCH) {
+ switch (ELF_R_TYPE(Rel->r_info)) {
+ case R_LARCH_MARK_LA:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA);
+ break;
+ case R_LARCH_64:
+ CoffAddFixup(
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]
+ + (Rel->r_offset - SecShdr->sh_addr)),
+ EFI_IMAGE_REL_BASED_DIR64);
+ break;
+ case R_LARCH_NONE:
+ case R_LARCH_32:
+ case R_LARCH_RELATIVE:
+ case R_LARCH_COPY:
+ case R_LARCH_JUMP_SLOT:
+ case R_LARCH_TLS_DTPMOD32:
+ case R_LARCH_TLS_DTPMOD64:
+ case R_LARCH_TLS_DTPREL32:
+ case R_LARCH_TLS_DTPREL64:
+ case R_LARCH_TLS_TPREL32:
+ case R_LARCH_TLS_TPREL64:
+ case R_LARCH_IRELATIVE:
+ case R_LARCH_MARK_PCREL:
+ case R_LARCH_SOP_PUSH_PCREL:
+ case R_LARCH_SOP_PUSH_ABSOLUTE:
+ case R_LARCH_SOP_PUSH_DUP:
+ case R_LARCH_SOP_PUSH_GPREL:
+ case R_LARCH_SOP_PUSH_TLS_TPREL:
+ case R_LARCH_SOP_PUSH_TLS_GOT:
+ case R_LARCH_SOP_PUSH_TLS_GD:
+ case R_LARCH_SOP_PUSH_PLT_PCREL:
+ case R_LARCH_SOP_ASSERT:
+ case R_LARCH_SOP_NOT:
+ case R_LARCH_SOP_SUB:
+ case R_LARCH_SOP_SL:
+ case R_LARCH_SOP_SR:
+ case R_LARCH_SOP_ADD:
+ case R_LARCH_SOP_AND:
+ case R_LARCH_SOP_IF_ELSE:
+ case R_LARCH_SOP_POP_32_S_10_5:
+ case R_LARCH_SOP_POP_32_U_10_12:
+ case R_LARCH_SOP_POP_32_S_10_12:
+ case R_LARCH_SOP_POP_32_S_10_16:
+ case R_LARCH_SOP_POP_32_S_10_16_S2:
+ case R_LARCH_SOP_POP_32_S_5_20:
+ case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:
+ case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:
+ case R_LARCH_SOP_POP_32_U:
+ case R_LARCH_ADD8:
+ case R_LARCH_ADD16:
+ case R_LARCH_ADD24:
+ case R_LARCH_ADD32:
+ case R_LARCH_ADD64:
+ case R_LARCH_SUB8:
+ case R_LARCH_SUB16:
+ case R_LARCH_SUB24:
+ case R_LARCH_SUB32:
+ case R_LARCH_SUB64:
+ case R_LARCH_GNU_VTINHERIT:
+ case R_LARCH_GNU_VTENTRY:
+ case R_LARCH_B16:
+ case R_LARCH_B21:
+ case R_LARCH_B26:
+ case R_LARCH_ABS_HI20:
+ case R_LARCH_ABS_LO12:
+ case R_LARCH_ABS64_LO20:
+ case R_LARCH_ABS64_HI12:
+ case R_LARCH_PCALA_HI20:
+ case R_LARCH_PCALA_LO12:
+ case R_LARCH_PCALA64_LO20:
+ case R_LARCH_PCALA64_HI12:
+ case R_LARCH_GOT_PC_HI20:
+ case R_LARCH_GOT_PC_LO12:
+ case R_LARCH_GOT64_PC_LO20:
+ case R_LARCH_GOT64_PC_HI12:
+ case R_LARCH_GOT64_HI20:
+ case R_LARCH_GOT64_LO12:
+ case R_LARCH_GOT64_LO20:
+ case R_LARCH_GOT64_HI12:
+ case R_LARCH_TLS_LE_HI20:
+ case R_LARCH_TLS_LE_LO12:
+ case R_LARCH_TLS_LE64_LO20:
+ case R_LARCH_TLS_LE64_HI12:
+ case R_LARCH_TLS_IE_PC_HI20:
+ case R_LARCH_TLS_IE_PC_LO12:
+ case R_LARCH_TLS_IE64_PC_LO20:
+ case R_LARCH_TLS_IE64_PC_HI12:
+ case R_LARCH_TLS_IE64_HI20:
+ case R_LARCH_TLS_IE64_LO12:
+ case R_LARCH_TLS_IE64_LO20:
+ case R_LARCH_TLS_IE64_HI12:
+ case R_LARCH_TLS_LD_PC_HI20:
+ case R_LARCH_TLS_LD64_HI20:
+ case R_LARCH_TLS_GD_PC_HI20:
+ case R_LARCH_TLS_GD64_HI20:
+ case R_LARCH_RELAX:
+ //
+ // These types are not used or do not require fixup in PE format files.
+ //
+ break;
+ default:
+ Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s unsupported ELF EM_LOONGARCH relocation 0x%x.", mInImageName, (unsigned) ELF64_R_TYPE(Rel->r_info));
+ }
} else {
Error (NULL, 0, 3000, "Not Supported", "This tool does not support relocations for ELF with e_machine %u (processor type).", (unsigned) mEhdr->e_machine);
}
diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/GenFw/elf_common.h
index b67f59e7a0..7b7fdeb329 100644
--- a/BaseTools/Source/C/GenFw/elf_common.h
+++ b/BaseTools/Source/C/GenFw/elf_common.h
@@ -4,6 +4,7 @@ Ported ELF include files from FreeBSD
Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Portion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -181,6 +182,7 @@ typedef struct {
#define EM_AARCH64 183 /* ARM 64bit Architecture */
#define EM_RISCV64 243 /* 64bit RISC-V Architecture */
#define EM_RISCV 244 /* 32bit RISC-V Architecture */
+#define EM_LOONGARCH 258 /* LoongArch Architecture */
/* Non-standard or deprecated. */
#define EM_486 6 /* Intel i486. */
@@ -1042,4 +1044,96 @@ typedef struct {
#define R_RISCV_SET8 54
#define R_RISCV_SET16 55
#define R_RISCV_SET32 56
+
+/*
+ * LoongArch relocation types
+ */
+#define R_LARCH_NONE 0
+#define R_LARCH_32 1
+#define R_LARCH_64 2
+#define R_LARCH_RELATIVE 3
+#define R_LARCH_COPY 4
+#define R_LARCH_JUMP_SLOT 5
+#define R_LARCH_TLS_DTPMOD32 6
+#define R_LARCH_TLS_DTPMOD64 7
+#define R_LARCH_TLS_DTPREL32 8
+#define R_LARCH_TLS_DTPREL64 9
+#define R_LARCH_TLS_TPREL32 10
+#define R_LARCH_TLS_TPREL64 11
+#define R_LARCH_IRELATIVE 12
+#define R_LARCH_MARK_LA 20
+#define R_LARCH_MARK_PCREL 21
+#define R_LARCH_SOP_PUSH_PCREL 22
+#define R_LARCH_SOP_PUSH_ABSOLUTE 23
+#define R_LARCH_SOP_PUSH_DUP 24
+#define R_LARCH_SOP_PUSH_GPREL 25
+#define R_LARCH_SOP_PUSH_TLS_TPREL 26
+#define R_LARCH_SOP_PUSH_TLS_GOT 27
+#define R_LARCH_SOP_PUSH_TLS_GD 28
+#define R_LARCH_SOP_PUSH_PLT_PCREL 29
+#define R_LARCH_SOP_ASSERT 30
+#define R_LARCH_SOP_NOT 31
+#define R_LARCH_SOP_SUB 32
+#define R_LARCH_SOP_SL 33
+#define R_LARCH_SOP_SR 34
+#define R_LARCH_SOP_ADD 35
+#define R_LARCH_SOP_AND 36
+#define R_LARCH_SOP_IF_ELSE 37
+#define R_LARCH_SOP_POP_32_S_10_5 38
+#define R_LARCH_SOP_POP_32_U_10_12 39
+#define R_LARCH_SOP_POP_32_S_10_12 40
+#define R_LARCH_SOP_POP_32_S_10_16 41
+#define R_LARCH_SOP_POP_32_S_10_16_S2 42
+#define R_LARCH_SOP_POP_32_S_5_20 43
+#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44
+#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45
+#define R_LARCH_SOP_POP_32_U 46
+#define R_LARCH_ADD8 47
+#define R_LARCH_ADD16 48
+#define R_LARCH_ADD24 49
+#define R_LARCH_ADD32 50
+#define R_LARCH_ADD64 51
+#define R_LARCH_SUB8 52
+#define R_LARCH_SUB16 53
+#define R_LARCH_SUB24 54
+#define R_LARCH_SUB32 55
+#define R_LARCH_SUB64 56
+#define R_LARCH_GNU_VTINHERIT 57
+#define R_LARCH_GNU_VTENTRY 58
+#define R_LARCH_B16 64
+#define R_LARCH_B21 65
+#define R_LARCH_B26 66
+#define R_LARCH_ABS_HI20 67
+#define R_LARCH_ABS_LO12 68
+#define R_LARCH_ABS64_LO20 69
+#define R_LARCH_ABS64_HI12 70
+#define R_LARCH_PCALA_HI20 71
+#define R_LARCH_PCALA_LO12 72
+#define R_LARCH_PCALA64_LO20 73
+#define R_LARCH_PCALA64_HI12 74
+#define R_LARCH_GOT_PC_HI20 75
+#define R_LARCH_GOT_PC_LO12 76
+#define R_LARCH_GOT64_PC_LO20 77
+#define R_LARCH_GOT64_PC_HI12 78
+#define R_LARCH_GOT64_HI20 79
+#define R_LARCH_GOT64_LO12 80
+#define R_LARCH_GOT64_LO20 81
+#define R_LARCH_GOT64_HI12 82
+#define R_LARCH_TLS_LE_HI20 83
+#define R_LARCH_TLS_LE_LO12 84
+#define R_LARCH_TLS_LE64_LO20 85
+#define R_LARCH_TLS_LE64_HI12 86
+#define R_LARCH_TLS_IE_PC_HI20 87
+#define R_LARCH_TLS_IE_PC_LO12 88
+#define R_LARCH_TLS_IE64_PC_LO20 89
+#define R_LARCH_TLS_IE64_PC_HI12 90
+#define R_LARCH_TLS_IE64_HI20 91
+#define R_LARCH_TLS_IE64_LO12 92
+#define R_LARCH_TLS_IE64_LO20 93
+#define R_LARCH_TLS_IE64_HI12 94
+#define R_LARCH_TLS_LD_PC_HI20 95
+#define R_LARCH_TLS_LD64_HI20 96
+#define R_LARCH_TLS_GD_PC_HI20 97
+#define R_LARCH_TLS_GD64_HI20 98
+#define R_LARCH_RELAX 99
#endif /* !_SYS_ELF_COMMON_H_ */
diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
index 21c968e650..77ded3f611 100644
--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
@@ -7,6 +7,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -36,23 +37,25 @@
//
// PE32+ Machine type for EFI images
//
-#define IMAGE_FILE_MACHINE_I386 0x014c
-#define IMAGE_FILE_MACHINE_EBC 0x0EBC
-#define IMAGE_FILE_MACHINE_X64 0x8664
-#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
-#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/Thumb 2 Little Endian
-#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Little Endian
-#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
+#define IMAGE_FILE_MACHINE_I386 0x014c
+#define IMAGE_FILE_MACHINE_EBC 0x0EBC
+#define IMAGE_FILE_MACHINE_X64 0x8664
+#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only
+#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/Thumb 2 Little Endian
+#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Little Endian
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA
+#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 // 64bit LoongArch Architecture
//
// Support old names for backward compatible
//
-#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386
-#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
-#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
-#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
-#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
-#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
+#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386
+#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC
+#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64
+#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT
+#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64
+#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64
+#define EFI_IMAGE_MACHINE_LOONGARCH64 IMAGE_FILE_MACHINE_LOONGARCH64
#define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ
#define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE
@@ -500,19 +503,21 @@ typedef struct {
//
// Based relocation types.
//
-#define EFI_IMAGE_REL_BASED_ABSOLUTE 0
-#define EFI_IMAGE_REL_BASED_HIGH 1
-#define EFI_IMAGE_REL_BASED_LOW 2
-#define EFI_IMAGE_REL_BASED_HIGHLOW 3
-#define EFI_IMAGE_REL_BASED_HIGHADJ 4
-#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
-#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
-#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
-#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
-#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
-#define EFI_IMAGE_REL_BASED_DIR64 10
+#define EFI_IMAGE_REL_BASED_ABSOLUTE 0
+#define EFI_IMAGE_REL_BASED_HIGH 1
+#define EFI_IMAGE_REL_BASED_LOW 2
+#define EFI_IMAGE_REL_BASED_HIGHLOW 3
+#define EFI_IMAGE_REL_BASED_HIGHADJ 4
+#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5
+#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5
+#define EFI_IMAGE_REL_BASED_RISCV_HI20 5
+#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
+#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8
+#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8
+#define EFI_IMAGE_REL_BASED_IA64_IMM64 9
+#define EFI_IMAGE_REL_BASED_DIR64 10
///
--git a/BaseTools/Source/C/Makefiles/header.makefile b/BaseTools/Source/C/Makefiles/header.makefile
index 0df728f327..4e88a4fbd8 100644
--- a/BaseTools/Source/C/Makefiles/header.makefile
+++ b/BaseTools/Source/C/Makefiles/header.makefile
@@ -31,6 +31,9 @@ ifndef HOST_ARCH
ifneq (,$(findstring riscv64,$(uname_m)))
HOST_ARCH=RISCV64
endif
+ ifneq (,$(findstring loongarch64,$(uname_m)))
+ HOST_ARCH=LOONGARCH64
+ endif
ifndef HOST_ARCH
$(info Could not detected HOST_ARCH from uname results)
$(error HOST_ARCH is not defined!)
@@ -70,6 +73,9 @@ ARCH_INCLUDE = -I $(MAKEROOT)/Include/AArch64/
else ifeq ($(HOST_ARCH), RISCV64)
ARCH_INCLUDE = -I $(MAKEROOT)/Include/RiscV64/
+else ifeq ($(HOST_ARCH), LOONGARCH64)
+ARCH_INCLUDE = -I $(MAKEROOT)/Include/LoongArch64/
+
else
$(error Bad HOST_ARCH)
endif
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 16/34] BaseTools: Updated for GCC5 tool chain for LoongArch platfrom.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (14 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 15/34] BaseTools: Update GenFw/GenFv to support LoongArch platform Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 17/34] BaseTools: Updated build tools to support new LoongArch Chao Li
` (17 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Bob Feng, Liming Gao, Yuwei Chen, Dongyan Qian, Baoqi Zhang
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
BaseTools define template files changes for building EDK2 LoongArch
platform.
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Dongyan Qian <qiandongyan@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
BaseTools/Conf/tools_def.template | 54 +++++++++++++++++++++++++++----
1 file changed, 48 insertions(+), 6 deletions(-)
diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.template
index 5ed19810b7..9ceadeaa59 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -4,6 +4,7 @@
# Portions copyright (c) 2011 - 2019, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>
# (C) Copyright 2020, Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# Copyright (c) Microsoft Corporation
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -267,7 +268,7 @@ DEFINE DTC_BIN = ENV(DTC_PREFIX)dtc
# Intel(r) ACPI Compiler from
# https://acpica.org/downloads
# GCC5 -Linux,Windows- Requires:
-# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabi or riscv64-linux-gnu
+# GCC 5 with LTO support, targeting x86_64-linux-gnu, aarch64-linux-gnu, arm-linux-gnueabi, riscv64-linux-gnu or loongarch64-linux-gnu
# Optional:
# Required to build platforms or ACPI tables:
# Intel(r) ACPI Compiler from
@@ -1852,6 +1853,7 @@ DEFINE GCC_ALL_CC_FLAGS = -g -Os -fshort-wchar -fno-builtin -fno-stri
DEFINE GCC_IA32_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -m32 -malign-double -freorder-blocks -freorder-blocks-and-partition -O2 -mno-stack-arg-probe
DEFINE GCC_X64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mno-red-zone -Wno-address -mno-stack-arg-probe
DEFINE GCC_ARM_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -mabi=aapcs -fno-short-enums -funsigned-char -ffunction-sections -fdata-sections -fomit-frame-pointer -Wno-address -mthumb -mfloat-abi=soft -fno-pic -fno-pie
+DEFINE GCC_LOONGARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mabi=lp64d -fno-asynchronous-unwind-tables -fno-plt -Wno-address -fno-short-enums -fsigned-char -ffunction-sections -fdata-sections
DEFINE GCC_ARM_CC_XIPFLAGS = -mno-unaligned-access
DEFINE GCC_AARCH64_CC_FLAGS = DEF(GCC_ALL_CC_FLAGS) -mlittle-endian -fno-short-enums -fverbose-asm -funsigned-char -ffunction-sections -fdata-sections -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables -fno-pic -fno-pie -ffixed-x18
DEFINE GCC_AARCH64_CC_XIPFLAGS = -mstrict-align -mgeneral-regs-only
@@ -1859,12 +1861,15 @@ DEFINE GCC_DLINK_FLAGS_COMMON = -nostdlib --pie
DEFINE GCC_DLINK2_FLAGS_COMMON = -Wl,--script=$(EDK_TOOLS_PATH)/Scripts/GccBase.lds
DEFINE GCC_IA32_X64_DLINK_COMMON = DEF(GCC_DLINK_FLAGS_COMMON) --gc-sections
DEFINE GCC_ARM_AARCH64_DLINK_COMMON= -Wl,--emit-relocs -nostdlib -Wl,--gc-sections -u $(IMAGE_ENTRY_POINT) -Wl,-e,$(IMAGE_ENTRY_POINT),-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map
+DEFINE GCC_LOONGARCH64_DLINK_COMMON= -Wl,--emit-relocs -nostdlib -Wl,--gc-sections -u $(IMAGE_ENTRY_POINT) -Wl,-e,$(IMAGE_ENTRY_POINT),-Map,$(DEST_DIR_DEBUG)/$(BASE_NAME).map
DEFINE GCC_ARM_DLINK_FLAGS = DEF(GCC_ARM_AARCH64_DLINK_COMMON) -z common-page-size=0x20 -Wl,--pic-veneer
DEFINE GCC_AARCH64_DLINK_FLAGS = DEF(GCC_ARM_AARCH64_DLINK_COMMON) -z common-page-size=0x20
+DEFINE GCC_LOONGARCH64_DLINK_FLAGS = DEF(GCC_LOONGARCH64_DLINK_COMMON) -z common-page-size=0x20
DEFINE GCC_ARM_AARCH64_ASLDLINK_FLAGS = -Wl,--defsym=PECOFF_HEADER_SIZE=0 DEF(GCC_DLINK2_FLAGS_COMMON) -z common-page-size=0x20
DEFINE GCC_IA32_X64_ASLDLINK_FLAGS = DEF(GCC_IA32_X64_DLINK_COMMON) --entry _ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT)
DEFINE GCC_ARM_ASLDLINK_FLAGS = DEF(GCC_ARM_DLINK_FLAGS) -Wl,--entry,ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT) DEF(GCC_ARM_AARCH64_ASLDLINK_FLAGS)
DEFINE GCC_AARCH64_ASLDLINK_FLAGS = DEF(GCC_AARCH64_DLINK_FLAGS) -Wl,--entry,ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT) DEF(GCC_ARM_AARCH64_ASLDLINK_FLAGS)
+DEFINE GCC_LOONGARCH64_ASLDLINK_FLAGS = DEF(GCC_LOONGARCH64_DLINK_FLAGS) --entry ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT)
DEFINE GCC_IA32_X64_DLINK_FLAGS = DEF(GCC_IA32_X64_DLINK_COMMON) --entry _$(IMAGE_ENTRY_POINT) --file-alignment 0x20 --section-alignment 0x20 -Map $(DEST_DIR_DEBUG)/$(BASE_NAME).map
DEFINE GCC_ASM_FLAGS = -c -x assembler -imacros AutoGen.h
DEFINE GCC_PP_FLAGS = -E -x assembler-with-cpp -include AutoGen.h
@@ -1873,11 +1878,12 @@ DEFINE GCC_ASLPP_FLAGS = -x c -E -include AutoGen.h
DEFINE GCC_ASLCC_FLAGS = -x c
DEFINE GCC_WINDRES_FLAGS = -J rc -O coff
DEFINE GCC_DTCPP_FLAGS = -E -x assembler-with-cpp -imacros AutoGen.h -nostdinc -undef
-DEFINE GCC_IA32_RC_FLAGS = -I binary -O elf32-i386 -B i386 --rename-section .data=.hii
-DEFINE GCC_X64_RC_FLAGS = -I binary -O elf64-x86-64 -B i386 --rename-section .data=.hii
-DEFINE GCC_ARM_RC_FLAGS = -I binary -O elf32-littlearm -B arm --rename-section .data=.hii
-DEFINE GCC_AARCH64_RC_FLAGS = -I binary -O elf64-littleaarch64 -B aarch64 --rename-section .data=.hii
-DEFINE GCC_RISCV64_RC_FLAGS = -I binary -O elf64-littleriscv -B riscv --rename-section .data=.hii
+DEFINE GCC_IA32_RC_FLAGS = -I binary -O elf32-i386 -B i386 --rename-section .data=.hii
+DEFINE GCC_X64_RC_FLAGS = -I binary -O elf64-x86-64 -B i386 --rename-section .data=.hii
+DEFINE GCC_ARM_RC_FLAGS = -I binary -O elf32-littlearm -B arm --rename-section .data=.hii
+DEFINE GCC_AARCH64_RC_FLAGS = -I binary -O elf64-littleaarch64 -B aarch64 --rename-section .data=.hii
+DEFINE GCC_RISCV64_RC_FLAGS = -I binary -O elf64-littleriscv -B riscv --rename-section .data=.hii
+DEFINE GCC_LOONGARCH64_RC_FLAGS = -I binary -O elf64-loongarch -B loongarch64 --rename-section .data=.hii
# GCC Build Flag for included header file list generation
DEFINE GCC_DEPS_FLAGS = -MMD -MF $@.deps
@@ -1967,6 +1973,14 @@ DEFINE GCC5_RISCV64_CC_FLAGS = DEF(GCC5_RISCV_ALL_CC_FLAGS) DEF(GC
DEFINE GCC5_RISCV64_DLINK_FLAGS = DEF(GCC5_RISCV_ALL_DLINK_FLAGS) -Wl,-melf64lriscv,--oformat=elf64-littleriscv,--no-relax
DEFINE GCC5_RISCV64_DLINK2_FLAGS = DEF(GCC5_RISCV_ALL_DLINK2_FLAGS)
DEFINE GCC5_RISCV64_ASM_FLAGS = DEF(GCC5_RISCV_ALL_ASM_FLAGS) -march=DEF(GCC5_RISCV64_ARCH) -mcmodel=medany -mabi=lp64
+
+DEFINE GCC5_LOONGARCH64_CC_FLAGS = DEF(GCC_LOONGARCH64_CC_FLAGS) -march=loongarch64 -mno-memcpy -Werror -Wno-maybe-uninitialized -Wno-stringop-overflow -Wno-pointer-to-int-cast -no-pie -fno-stack-protector -mno-explicit-relocs
+DEFINE GCC5_LOONGARCH64_DLINK_FLAGS = DEF(GCC_LOONGARCH64_DLINK_FLAGS)
+DEFINE GCC5_LOONGARCH64_DLINK2_FLAGS = DEF(GCC_DLINK2_FLAGS_COMMON) -Wl,--defsym=PECOFF_HEADER_SIZE=0x228
+DEFINE GCC5_LOONGARCH64_ASLDLINK_FLAGS = DEF(GCC_LOONGARCH64_ASLDLINK_FLAGS)
+DEFINE GCC5_LOONGARCH64_ASM_FLAGS = -x assembler-with-cpp -mabi=lp64d -march=loongarch64 -fno-builtin -c -Wall -mno-explicit-relocs
+DEFINE GCC5_LOONGARCH64_PP_FLAGS = -mabi=lp64d -march=loongarch64 DEF(GCC_PP_FLAGS)
+
DEFINE GCC_PP_FLAGS = -E -x assembler-with-cpp -include AutoGen.h DEF(GCC5_RISCV_OPENSBI_TYPES)
####################################################################################
@@ -2445,6 +2459,34 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS = -z common-page-size=0x20
*_GCC5_RISCV64_OBJCOPY_FLAGS =
*_GCC5_RISCV64_DTCPP_FLAGS = DEF(GCC_DTCPP_FLAGS)
+##################
+# GCC5 LOONGARCH64 definitions
+##################
+*_GCC5_LOONGARCH64_OBJCOPY_PATH = ENV(GCC5_LOONGARCH64_PREFIX)objcopy
+*_GCC5_LOONGARCH64_CC_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
+*_GCC5_LOONGARCH64_SLINK_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc-ar
+*_GCC5_LOONGARCH64_DLINK_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
+*_GCC5_LOONGARCH64_ASLDLINK_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
+*_GCC5_LOONGARCH64_ASM_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
+*_GCC5_LOONGARCH64_PP_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
+*_GCC5_LOONGARCH64_VFRPP_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
+*_GCC5_LOONGARCH64_ASLCC_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
+*_GCC5_LOONGARCH64_ASLPP_PATH = ENV(GCC5_LOONGARCH64_PREFIX)gcc
+*_GCC5_LOONGARCH64_RC_PATH = ENV(GCC5_LOONGARCH64_PREFIX)objcopy
+
+*_GCC5_LOONGARCH64_ASLCC_FLAGS = DEF(GCC_ASLCC_FLAGS)
+*_GCC5_LOONGARCH64_ASLDLINK_FLAGS = DEF(GCC5_LOONGARCH64_ASLDLINK_FLAGS)
+*_GCC5_LOONGARCH64_ASM_FLAGS = DEF(GCC5_LOONGARCH64_ASM_FLAGS)
+*_GCC5_LOONGARCH64_DLINK_FLAGS = DEF(GCC5_LOONGARCH64_DLINK_FLAGS)
+*_GCC5_LOONGARCH64_DLINK2_FLAGS = DEF(GCC5_LOONGARCH64_DLINK2_FLAGS)
+*_GCC5_LOONGARCH64_RC_FLAGS = DEF(GCC_LOONGARCH64_RC_FLAGS)
+*_GCC5_LOONGARCH64_OBJCOPY_FLAGS =
+*_GCC5_LOONGARCH64_NASM_FLAGS = -f elf32
+*_GCC5_LOONGARCH64_PP_FLAGS = DEF(GCC5_LOONGARCH64_PP_FLAGS)
+
+DEBUG_GCC5_LOONGARCH64_CC_FLAGS = DEF(GCC5_LOONGARCH64_CC_FLAGS)
+RELEASE_GCC5_LOONGARCH64_CC_FLAGS = DEF(GCC5_LOONGARCH64_CC_FLAGS) -Wno-unused-but-set-variable -Wno-unused-variable
+
####################################################################################
#
# CLANG35 - This configuration is used to compile under Linux to produce
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 17/34] BaseTools: Updated build tools to support new LoongArch.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (15 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 16/34] BaseTools: Updated for GCC5 tool chain for LoongArch platfrom Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 18/34] BaseTools: Add LoongArch64 binding Chao Li
` (16 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Bob Feng, Liming Gao, Yuwei Chen, Baoqi Zhang
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Python code changes for building EDK2 LoongArch platform.
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
BaseTools/Source/Python/Common/DataType.py | 21 ++++++++++++++--
.../Source/Python/UPT/Library/DataType.py | 24 ++++++++++++++++++-
BaseTools/Source/Python/build/buildoptions.py | 3 ++-
3 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/Python/Common/DataType.py
index dc49623333..48dbf16495 100644
--- a/BaseTools/Source/Python/Common/DataType.py
+++ b/BaseTools/Source/Python/Common/DataType.py
@@ -4,6 +4,7 @@
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -52,10 +53,10 @@ TAB_ARCH_X64 = 'X64'
TAB_ARCH_ARM = 'ARM'
TAB_ARCH_EBC = 'EBC'
TAB_ARCH_AARCH64 = 'AARCH64'
-
TAB_ARCH_RISCV64 = 'RISCV64'
+TAB_ARCH_LOONGARCH64 = 'LOONGARCH64'
-ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_COMMON}
+ARCH_SET_FULL = {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_LOONGARCH64, TAB_ARCH_COMMON}
SUP_MODULE_BASE = 'BASE'
SUP_MODULE_SEC = 'SEC'
@@ -138,6 +139,7 @@ TAB_SOURCES_X64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_X64
TAB_SOURCES_ARM = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_ARM
TAB_SOURCES_EBC = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_EBC
TAB_SOURCES_AARCH64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_SOURCES_LOONGARCH64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_BINARIES = 'Binaries'
TAB_BINARIES_COMMON = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_COMMON
@@ -146,6 +148,7 @@ TAB_BINARIES_X64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_X64
TAB_BINARIES_ARM = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_ARM
TAB_BINARIES_EBC = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_EBC
TAB_BINARIES_AARCH64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_BINARIES_LOONGARCH64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_INCLUDES = 'Includes'
TAB_INCLUDES_COMMON = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_COMMON
@@ -154,6 +157,7 @@ TAB_INCLUDES_X64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_X64
TAB_INCLUDES_ARM = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_ARM
TAB_INCLUDES_EBC = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_EBC
TAB_INCLUDES_AARCH64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_INCLUDES_LOONGARCH64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_GUIDS = 'Guids'
TAB_GUIDS_COMMON = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_COMMON
@@ -162,6 +166,7 @@ TAB_GUIDS_X64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_X64
TAB_GUIDS_ARM = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_ARM
TAB_GUIDS_EBC = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_EBC
TAB_GUIDS_AARCH64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_GUIDS_LOONGARCH64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PROTOCOLS = 'Protocols'
TAB_PROTOCOLS_COMMON = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_COMMON
@@ -170,6 +175,7 @@ TAB_PROTOCOLS_X64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_X64
TAB_PROTOCOLS_ARM = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_ARM
TAB_PROTOCOLS_EBC = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_EBC
TAB_PROTOCOLS_AARCH64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_PROTOCOLS_LOONGARCH64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PPIS = 'Ppis'
TAB_PPIS_COMMON = TAB_PPIS + TAB_SPLIT + TAB_ARCH_COMMON
@@ -178,6 +184,7 @@ TAB_PPIS_X64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_X64
TAB_PPIS_ARM = TAB_PPIS + TAB_SPLIT + TAB_ARCH_ARM
TAB_PPIS_EBC = TAB_PPIS + TAB_SPLIT + TAB_ARCH_EBC
TAB_PPIS_AARCH64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_PPIS_LOONGARCH64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_LIBRARY_CLASSES = 'LibraryClasses'
TAB_LIBRARY_CLASSES_COMMON = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_COMMON
@@ -186,6 +193,7 @@ TAB_LIBRARY_CLASSES_X64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_X64
TAB_LIBRARY_CLASSES_ARM = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_ARM
TAB_LIBRARY_CLASSES_EBC = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_EBC
TAB_LIBRARY_CLASSES_AARCH64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_LIBRARY_CLASSES_LOONGARCH64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PACKAGES = 'Packages'
TAB_PACKAGES_COMMON = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_COMMON
@@ -194,6 +202,7 @@ TAB_PACKAGES_X64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_X64
TAB_PACKAGES_ARM = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_ARM
TAB_PACKAGES_EBC = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_EBC
TAB_PACKAGES_AARCH64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_PACKAGES_LOONGARCH64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PCDS = 'Pcds'
TAB_PCDS_FIXED_AT_BUILD = 'FixedAtBuild'
@@ -221,6 +230,7 @@ TAB_PCDS_FIXED_AT_BUILD_X64 = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + T
TAB_PCDS_FIXED_AT_BUILD_ARM = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_FIXED_AT_BUILD_EBC = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_EBC
TAB_PCDS_FIXED_AT_BUILD_AARCH64 = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_PCDS_FIXED_AT_BUILD_LOONGARCH64 = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PCDS_PATCHABLE_IN_MODULE_NULL = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE
TAB_PCDS_PATCHABLE_IN_MODULE_COMMON = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_COMMON
@@ -229,6 +239,7 @@ TAB_PCDS_PATCHABLE_IN_MODULE_X64 = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB
TAB_PCDS_PATCHABLE_IN_MODULE_ARM = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_PATCHABLE_IN_MODULE_EBC = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_EBC
TAB_PCDS_PATCHABLE_IN_MODULE_AARCH64 = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_PCDS_PATCHABLE_IN_MODULE_LOONGARCH64 = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PCDS_FEATURE_FLAG_NULL = TAB_PCDS + TAB_PCDS_FEATURE_FLAG
TAB_PCDS_FEATURE_FLAG_COMMON = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_COMMON
@@ -237,6 +248,7 @@ TAB_PCDS_FEATURE_FLAG_X64 = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_A
TAB_PCDS_FEATURE_FLAG_ARM = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_FEATURE_FLAG_EBC = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_EBC
TAB_PCDS_FEATURE_FLAG_AARCH64 = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_PCDS_FEATURE_FLAG_LOONGARCH64 = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PCDS_DYNAMIC_EX_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC_EX
TAB_PCDS_DYNAMIC_EX_DEFAULT_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC_EX_DEFAULT
@@ -248,6 +260,7 @@ TAB_PCDS_DYNAMIC_EX_X64 = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_
TAB_PCDS_DYNAMIC_EX_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_DYNAMIC_EX_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_EBC
TAB_PCDS_DYNAMIC_EX_AARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_PCDS_DYNAMIC_EX_LOONGARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PCDS_DYNAMIC_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC
TAB_PCDS_DYNAMIC_DEFAULT_NULL = TAB_PCDS + TAB_PCDS_DYNAMIC_DEFAULT
@@ -259,6 +272,7 @@ TAB_PCDS_DYNAMIC_X64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_X64
TAB_PCDS_DYNAMIC_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_ARM
TAB_PCDS_DYNAMIC_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_EBC
TAB_PCDS_DYNAMIC_AARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_PCDS_DYNAMIC_LOONGARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE = 'PcdLoadFixAddressPeiCodePageNumber'
TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE_DATA_TYPE = 'UINT32'
@@ -285,6 +299,7 @@ TAB_DEPEX_X64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_X64
TAB_DEPEX_ARM = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_ARM
TAB_DEPEX_EBC = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_EBC
TAB_DEPEX_AARCH64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_DEPEX_LOONGARCH64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_SKUIDS = 'SkuIds'
TAB_DEFAULT_STORES = 'DefaultStores'
@@ -297,6 +312,7 @@ TAB_LIBRARIES_X64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_X64
TAB_LIBRARIES_ARM = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_ARM
TAB_LIBRARIES_EBC = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_EBC
TAB_LIBRARIES_AARCH64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_LIBRARIES_LOONGARCH64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_COMPONENTS = 'Components'
TAB_COMPONENTS_COMMON = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_COMMON
@@ -305,6 +321,7 @@ TAB_COMPONENTS_X64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_X64
TAB_COMPONENTS_ARM = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_ARM
TAB_COMPONENTS_EBC = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_EBC
TAB_COMPONENTS_AARCH64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_AARCH64
+TAB_COMPONENTS_LOONGARCH64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_BUILD_OPTIONS = 'BuildOptions'
diff --git a/BaseTools/Source/Python/UPT/Library/DataType.py b/BaseTools/Source/Python/UPT/Library/DataType.py
index 2033149aa6..0e47f35670 100644
--- a/BaseTools/Source/Python/UPT/Library/DataType.py
+++ b/BaseTools/Source/Python/UPT/Library/DataType.py
@@ -2,6 +2,7 @@
# This file is used to define class for data type structure
#
# Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
+# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -367,10 +368,11 @@ TAB_ARCH_IA32 = 'IA32'
TAB_ARCH_X64 = 'X64'
TAB_ARCH_IPF = 'IPF'
TAB_ARCH_ARM = 'ARM'
+TAB_ARCH_LOONGARCH64 = 'LOONGARCH64'
TAB_ARCH_EBC = 'EBC'
ARCH_LIST = \
-[TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_IPF, TAB_ARCH_ARM, TAB_ARCH_EBC]
+[TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_IPF, TAB_ARCH_ARM, TAB_ARCH_LOONGARCH64, TAB_ARCH_EBC]
SUP_MODULE_BASE = 'BASE'
SUP_MODULE_SEC = 'SEC'
@@ -454,6 +456,7 @@ TAB_SOURCES_IA32 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_IA32
TAB_SOURCES_X64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_X64
TAB_SOURCES_IPF = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_IPF
TAB_SOURCES_ARM = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_ARM
+TAB_SOURCES_LOONGARCH64 = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_SOURCES_EBC = TAB_SOURCES + TAB_SPLIT + TAB_ARCH_EBC
TAB_BINARIES = 'Binaries'
@@ -462,6 +465,7 @@ TAB_BINARIES_IA32 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_IA32
TAB_BINARIES_X64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_X64
TAB_BINARIES_IPF = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_IPF
TAB_BINARIES_ARM = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_ARM
+TAB_BINARIES_LOONGARCH64 = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_BINARIES_EBC = TAB_BINARIES + TAB_SPLIT + TAB_ARCH_EBC
TAB_INCLUDES = 'Includes'
@@ -470,6 +474,7 @@ TAB_INCLUDES_IA32 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_IA32
TAB_INCLUDES_X64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_X64
TAB_INCLUDES_IPF = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_IPF
TAB_INCLUDES_ARM = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_ARM
+TAB_INCLUDES_LOONGARCH64 = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_INCLUDES_EBC = TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_EBC
TAB_GUIDS = 'Guids'
@@ -478,6 +483,7 @@ TAB_GUIDS_IA32 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_IA32
TAB_GUIDS_X64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_X64
TAB_GUIDS_IPF = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_IPF
TAB_GUIDS_ARM = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_ARM
+TAB_GUIDS_LOONGARCH64 = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_GUIDS_EBC = TAB_GUIDS + TAB_SPLIT + TAB_ARCH_EBC
TAB_PROTOCOLS = 'Protocols'
@@ -486,6 +492,7 @@ TAB_PROTOCOLS_IA32 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_IA32
TAB_PROTOCOLS_X64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_X64
TAB_PROTOCOLS_IPF = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_IPF
TAB_PROTOCOLS_ARM = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_ARM
+TAB_PROTOCOLS_LOONGARCH64 = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PROTOCOLS_EBC = TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_EBC
TAB_PPIS = 'Ppis'
@@ -494,6 +501,7 @@ TAB_PPIS_IA32 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_IA32
TAB_PPIS_X64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_X64
TAB_PPIS_IPF = TAB_PPIS + TAB_SPLIT + TAB_ARCH_IPF
TAB_PPIS_ARM = TAB_PPIS + TAB_SPLIT + TAB_ARCH_ARM
+TAB_PPIS_LOONGARCH64 = TAB_PPIS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PPIS_EBC = TAB_PPIS + TAB_SPLIT + TAB_ARCH_EBC
TAB_LIBRARY_CLASSES = 'LibraryClasses'
@@ -502,6 +510,7 @@ TAB_LIBRARY_CLASSES_IA32 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_IA32
TAB_LIBRARY_CLASSES_X64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_X64
TAB_LIBRARY_CLASSES_IPF = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_IPF
TAB_LIBRARY_CLASSES_ARM = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_ARM
+TAB_LIBRARY_CLASSES_LOONGARCH64 = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_LIBRARY_CLASSES_EBC = TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_EBC
TAB_PACKAGES = 'Packages'
@@ -510,6 +519,7 @@ TAB_PACKAGES_IA32 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_IA32
TAB_PACKAGES_X64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_X64
TAB_PACKAGES_IPF = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_IPF
TAB_PACKAGES_ARM = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_ARM
+TAB_PACKAGES_LOONGARCH64 = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PACKAGES_EBC = TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_EBC
TAB_PCDS = 'Pcds'
@@ -548,6 +558,8 @@ TAB_PCDS_FIXED_AT_BUILD_IPF = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \
TAB_SPLIT + TAB_ARCH_IPF
TAB_PCDS_FIXED_AT_BUILD_ARM = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \
TAB_SPLIT + TAB_ARCH_ARM
+TAB_PCDS_FIXED_AT_BUILD_LOONGARCH64 = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \
+TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PCDS_FIXED_AT_BUILD_EBC = TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \
TAB_SPLIT + TAB_ARCH_EBC
@@ -562,6 +574,8 @@ TAB_PCDS_PATCHABLE_IN_MODULE_IPF = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + \
TAB_SPLIT + TAB_ARCH_IPF
TAB_PCDS_PATCHABLE_IN_MODULE_ARM = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + \
TAB_SPLIT + TAB_ARCH_ARM
+TAB_PCDS_PATCHABLE_IN_MODULE_LOONGARCH64 = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + \
+TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PCDS_PATCHABLE_IN_MODULE_EBC = TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODULE + \
TAB_SPLIT + TAB_ARCH_EBC
@@ -576,6 +590,8 @@ TAB_PCDS_FEATURE_FLAG_IPF = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + \
TAB_ARCH_IPF
TAB_PCDS_FEATURE_FLAG_ARM = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + \
TAB_ARCH_ARM
+TAB_PCDS_FEATURE_FLAG_LOONGARCH64 = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + \
+TAB_ARCH_LOONGARCH64
TAB_PCDS_FEATURE_FLAG_EBC = TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT + \
TAB_ARCH_EBC
@@ -593,6 +609,8 @@ TAB_PCDS_DYNAMIC_EX_IPF = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \
TAB_ARCH_IPF
TAB_PCDS_DYNAMIC_EX_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \
TAB_ARCH_ARM
+TAB_PCDS_DYNAMIC_EX_LOONGARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \
+TAB_ARCH_LOONGARCH64
TAB_PCDS_DYNAMIC_EX_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \
TAB_ARCH_EBC
@@ -606,6 +624,7 @@ TAB_PCDS_DYNAMIC_IA32 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_IA32
TAB_PCDS_DYNAMIC_X64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_X64
TAB_PCDS_DYNAMIC_IPF = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_IPF
TAB_PCDS_DYNAMIC_ARM = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_ARM
+TAB_PCDS_DYNAMIC_LOONGARCH64 = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_PCDS_DYNAMIC_EBC = TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARCH_EBC
TAB_PCD_DYNAMIC_TYPE_LIST = [TAB_PCDS_DYNAMIC_DEFAULT_NULL, \
@@ -646,6 +665,7 @@ TAB_DEPEX_IA32 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_IA32
TAB_DEPEX_X64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_X64
TAB_DEPEX_IPF = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_IPF
TAB_DEPEX_ARM = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_ARM
+TAB_DEPEX_LOONGARCH64 = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_DEPEX_EBC = TAB_DEPEX + TAB_SPLIT + TAB_ARCH_EBC
TAB_SKUIDS = 'SkuIds'
@@ -656,6 +676,7 @@ TAB_LIBRARIES_IA32 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_IA32
TAB_LIBRARIES_X64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_X64
TAB_LIBRARIES_IPF = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_IPF
TAB_LIBRARIES_ARM = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_ARM
+TAB_LIBRARIES_LOONGARCH64 = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_LIBRARIES_EBC = TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_EBC
TAB_COMPONENTS = 'Components'
@@ -664,6 +685,7 @@ TAB_COMPONENTS_IA32 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_IA32
TAB_COMPONENTS_X64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_X64
TAB_COMPONENTS_IPF = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_IPF
TAB_COMPONENTS_ARM = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_ARM
+TAB_COMPONENTS_LOONGARCH64 = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_LOONGARCH64
TAB_COMPONENTS_EBC = TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_EBC
TAB_BUILD_OPTIONS = 'BuildOptions'
diff --git a/BaseTools/Source/Python/build/buildoptions.py b/BaseTools/Source/Python/build/buildoptions.py
index 39d92cff20..8334604b46 100644
--- a/BaseTools/Source/Python/build/buildoptions.py
+++ b/BaseTools/Source/Python/build/buildoptions.py
@@ -4,6 +4,7 @@
# Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2018 - 2020, Hewlett Packard Enterprise Development, L.P.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -41,7 +42,7 @@ class MyOptionParser():
def GetOption(self):
Parser = OptionParser(description=__copyright__, version=__version__, prog="build.exe", usage="%prog [options] [all|fds|genc|genmake|clean|cleanall|cleanlib|modules|libraries|run]")
Parser.add_option("-a", "--arch", action="append", dest="TargetArch",
- help="ARCHS is one of list: IA32, X64, ARM, AARCH64, RISCV64 or EBC, which overrides target.txt's TARGET_ARCH definition. To specify more archs, please repeat this option.")
+ help="ARCHS is one of list: IA32, X64, ARM, AARCH64, RISCV64, LOONGARCH64 or EBC, which overrides target.txt's TARGET_ARCH definition. To specify more archs, please repeat this option.")
Parser.add_option("-p", "--platform", action="callback", type="string", dest="PlatformFile", callback=SingleCheckCallback,
help="Build the platform specified by the DSC file name argument, overriding target.txt's ACTIVE_PLATFORM definition.")
Parser.add_option("-m", "--module", action="callback", type="string", dest="ModuleFile", callback=SingleCheckCallback,
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 18/34] BaseTools: Add LoongArch64 binding.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (16 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 17/34] BaseTools: Updated build tools to support new LoongArch Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 19/34] BaseTools: Enable LoongArch64 architecture for LoongArch64 EDK2 CI Chao Li
` (15 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Bob Feng, Liming Gao, Yuwei Chen, Baoqi Zhang
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch64 ProcessorBin.h and add LoongArch to Makefiles.
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
BaseTools/Source/C/GNUmakefile | 3 +
.../C/Include/LoongArch64/ProcessorBind.h | 80 +++++++++++++++++++
2 files changed, 83 insertions(+)
create mode 100644 BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h
diff --git a/BaseTools/Source/C/GNUmakefile b/BaseTools/Source/C/GNUmakefile
index 8c191e0c38..5275f657ef 100644
--- a/BaseTools/Source/C/GNUmakefile
+++ b/BaseTools/Source/C/GNUmakefile
@@ -29,6 +29,9 @@ ifndef HOST_ARCH
ifneq (,$(findstring riscv64,$(uname_m)))
HOST_ARCH=RISCV64
endif
+ ifneq (,$(findstring loongarch64,$(uname_m)))
+ HOST_ARCH=LOONGARCH64
+ endif
ifndef HOST_ARCH
$(info Could not detected HOST_ARCH from uname results)
$(error HOST_ARCH is not defined!)
diff --git a/BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h b/BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h
new file mode 100644
index 0000000000..0267859dee
--- /dev/null
+++ b/BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h
@@ -0,0 +1,80 @@
+/** @file
+ Processor or Compiler specific defines and types for LoongArch
+
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#ifndef PROCESSOR_BIND_H_
+#define PROCESSOR_BIND_H_
+
+//
+// Define the processor type so other code can make processor based choices
+//
+#define MDE_CPU_LOONGARCH64
+
+#define EFIAPI
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#ifndef __GNUC__
+#pragma pack()
+#endif
+
+//
+// Use ANSI C 2000 stdint.h integer width declarations
+//
+#include <stdint.h>
+typedef uint8_t BOOLEAN;
+typedef int8_t INT8;
+typedef uint8_t UINT8;
+typedef int16_t INT16;
+typedef uint16_t UINT16;
+typedef int32_t INT32;
+typedef uint32_t UINT32;
+typedef int64_t INT64;
+typedef uint64_t UINT64;
+typedef char CHAR8;
+typedef uint16_t CHAR16;
+
+//
+// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
+// 8 bytes on supported 64-bit processor instructions)
+//
+typedef UINT64 UINTN;
+
+//
+// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+// 8 bytes on supported 64-bit processor instructions)
+//
+typedef INT64 INTN;
+
+//
+// Processor specific defines
+//
+
+//
+// A value of native width with the highest bit set.
+//
+#define MAX_BIT 0x8000000000000000ULL
+//
+// A value of native width with the two highest bits set.
+//
+#define MAX_2_BITS 0xC000000000000000ULL
+
+#if defined (__GNUC__)
+//
+// For GNU assembly code, .global or .globl can declare global symbols.
+// Define this macro to unify the usage.
+//
+#define ASM_GLOBAL .globl
+#endif
+
+//
+// The stack alignment required for LoongArch
+//
+#define CPU_STACK_ALIGNMENT 16
+
+#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 19/34] BaseTools: Enable LoongArch64 architecture for LoongArch64 EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (17 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 18/34] BaseTools: Add LoongArch64 binding Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 20/34] .azurepipelines: Add LoongArch64 architecture on " Chao Li
` (14 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Bob Feng, Liming Gao, Yuwei Chen, Michael D Kinney
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
EDK CI for LoongArch64 architecture
Enable LoongArch64 architecture for LoongArch64 EDK2 CI testing.
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
...gcc_loongarch64_unknown_linux_ext_dep.yaml | 22 +++++++++++++
.../LinuxGcc5ToolChain/LinuxGcc5ToolChain.py | 31 +++++++++++++++++++
2 files changed, 53 insertions(+)
create mode 100644 BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml
diff --git a/BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml b/BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml
new file mode 100644
index 0000000000..ac18438080
--- /dev/null
+++ b/BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml
@@ -0,0 +1,22 @@
+## @file
+# Download GCC LoongArch64 compiler from LoongArch GitHub release site
+# Set shell variable GCC5_LOONGARCH64_INSTALL to this folder
+#
+# This is only downloaded when a build activates scope gcc_loongarch64_unknown_linux
+#
+# Copyright (c) Microsoft Corporation.
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+{
+ "scope": "gcc_loongarch64_unknown_linux",
+ "type": "web",
+ "name": "gcc_loongarch64_unknown_linux",
+ "source":"https://github.com/loongson/build-tools/releases/download/2022.09.06/loongarch64-clfs-6.3-cross-tools-gcc-full.tar.xz",
+ "version": "13.0.0",
+ "sha256":"27a43c5bb127794f091d0e75da0003c4d0eec28a958d8f2cc7cd290a6e6133ab",
+ "compression_type": "tar",
+ "internal_path": "/cross-tools/",
+ "flags": ["set_shell_var", ],
+ "var_name": "GCC5_LOONGARCH64_INSTALL"
+}
diff --git a/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py b/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py
index f0685d8040..dab7a87997 100644
--- a/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py
+++ b/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py
@@ -5,6 +5,7 @@
#
# Copyright (c) Microsoft Corporation
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
import os
@@ -43,6 +44,12 @@ class LinuxGcc5ToolChain(IUefiBuildPlugin):
self.Logger.critical("Failed in check riscv64")
return ret
+ # Check LoongArch64 compiler
+ ret = self._check_loongarch64()
+ if ret != 0:
+ self.Logger.critical("Failed in check loongarch64")
+ return ret
+
return 0
def _check_arm(self):
@@ -121,3 +128,27 @@ class LinuxGcc5ToolChain(IUefiBuildPlugin):
shell_environment.GetEnvironment().set_shell_var("LD_LIBRARY_PATH", prefix)
return 0
+
+ def _check_loongarch64(self):
+ # check to see if full path already configured
+ if shell_environment.GetEnvironment().get_shell_var("GCC5_LOONGARCH64_PREFIX") is not None:
+ self.Logger.info("GCC5_LOONGARCH64_PREFIX is already set.")
+
+ else:
+ # now check for install dir. If set then set the Prefix
+ install_path = shell_environment.GetEnvironment(
+ ).get_shell_var("GCC5_LOONGARCH64_INSTALL")
+ if install_path is None:
+ return 0
+
+ # make GCC5_LOONGARCH64_PREFIX to align with tools_def.txt
+ prefix = os.path.join(install_path, "bin", "loongarch64-unknown-linux-gnu-")
+ shell_environment.GetEnvironment().set_shell_var("GCC5_LOONGARCH64_PREFIX", prefix)
+
+ # now confirm it exists
+ if not os.path.exists(shell_environment.GetEnvironment().get_shell_var("GCC5_LOONGARCH64_PREFIX") + "gcc"):
+ self.Logger.error(
+ "Path for GCC5_LOONGARCH64_PREFIX toolchain is invalid")
+ return -2
+
+ return 0
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 20/34] .azurepipelines: Add LoongArch64 architecture on LoongArch64 EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (18 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 19/34] BaseTools: Enable LoongArch64 architecture for LoongArch64 EDK2 CI Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 21/34] .pytool: " Chao Li
` (13 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch64 architecture on LoongArch64 EDK2 CI.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
.azurepipelines/Ubuntu-GCC5.yml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/.azurepipelines/Ubuntu-GCC5.yml b/.azurepipelines/Ubuntu-GCC5.yml
index 3760c6efe1..1acd8d2a46 100644
--- a/.azurepipelines/Ubuntu-GCC5.yml
+++ b/.azurepipelines/Ubuntu-GCC5.yml
@@ -3,6 +3,7 @@
#
# Copyright (c) Microsoft Corporation.
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
trigger:
@@ -17,5 +18,5 @@ jobs:
parameters:
tool_chain_tag: 'GCC5'
vm_image: 'ubuntu-latest'
- arch_list: "IA32,X64,ARM,AARCH64,RISCV64"
+ arch_list: "IA32,X64,ARM,AARCH64,RISCV64,LOONGARCH64"
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 21/34] .pytool: Add LoongArch64 architecture on LoongArch64 EDK2 CI.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (19 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 20/34] .azurepipelines: Add LoongArch64 architecture on " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 22/34] MdePkg: Add LoongArch LOONGARCH64 binding Chao Li
` (12 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch64 architecture on LoongArch64 EDK2 CI testing.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
.pytool/CISettings.py | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/.pytool/CISettings.py b/.pytool/CISettings.py
index cf9e0d77b1..7ebec0ba0a 100644
--- a/.pytool/CISettings.py
+++ b/.pytool/CISettings.py
@@ -79,7 +79,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
"X64",
"ARM",
"AARCH64",
- "RISCV64")
+ "RISCV64",
+ "LOONGARCH64")
def GetTargetsSupported(self):
''' return iterable of edk2 target tags supported by this build '''
@@ -170,6 +171,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsManager, SetupSettingsManag
scopes += ("gcc_arm_linux",)
if "RISCV64" in self.ActualArchitectures:
scopes += ("gcc_riscv64_unknown",)
+ if "LOONGARCH64" in self.ActualArchitectures:
+ scopes += ("gcc_loongarch64_unknown_linux",)
self.ActualScopes = scopes
return self.ActualScopes
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 22/34] MdePkg: Add LoongArch LOONGARCH64 binding
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (20 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 21/34] .pytool: " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 23/34] MdePkg/Include: LoongArch definitions Chao Li
` (11 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Baoqi Zhang,
Dongyan Qian
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LOONGARCH64 sections in MdePkg.dec and LOONGARCH64 ProcessorBind.h
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Co-authored-by: Dongyan Qian <qiandongyan@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/Include/LoongArch64/ProcessorBind.h | 120 +++++++++++++++++++++
MdePkg/MdePkg.dec | 4 +
MdePkg/MdePkg.dsc | 3 +-
3 files changed, 126 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Include/LoongArch64/ProcessorBind.h
diff --git a/MdePkg/Include/LoongArch64/ProcessorBind.h b/MdePkg/Include/LoongArch64/ProcessorBind.h
new file mode 100644
index 0000000000..502d479099
--- /dev/null
+++ b/MdePkg/Include/LoongArch64/ProcessorBind.h
@@ -0,0 +1,120 @@
+/** @file
+ Processor or Compiler specific defines and types for LoongArch
+
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef PROCESSOR_BIND_H_
+#define PROCESSOR_BIND_H_
+
+//
+// Define the processor type so other code can make processor based choices
+//
+#define MDE_CPU_LOONGARCH64
+
+#define EFIAPI
+
+//
+// Make sure we are using the correct packing rules per EFI specification
+//
+#ifndef __GNUC__
+ #pragma pack()
+#endif
+
+//
+// Assume standard LoongArch 64-bit alignment.
+// Need to check portability of long long
+//
+typedef unsigned long UINT64;
+typedef long INT64;
+typedef unsigned int UINT32;
+typedef int INT32;
+typedef unsigned short UINT16;
+typedef unsigned short CHAR16;
+typedef short INT16;
+typedef unsigned char BOOLEAN;
+typedef unsigned char UINT8;
+typedef char CHAR8;
+typedef char INT8;
+
+//
+// Unsigned value of native width. (4 bytes on supported 32-bit processor instructions,
+// 8 bytes on supported 64-bit processor instructions)
+//
+
+typedef UINT64 UINTN;
+
+//
+// Signed value of native width. (4 bytes on supported 32-bit processor instructions,
+// 8 bytes on supported 64-bit processor instructions)
+//
+typedef INT64 INTN;
+
+//
+// Processor specific defines
+//
+
+//
+// A value of native width with the highest bit set.
+//
+#define MAX_BIT 0x8000000000000000ULL
+//
+// A value of native width with the two highest bits set.
+//
+#define MAX_2_BITS 0xC000000000000000ULL
+
+//
+// Maximum legal LoongArch 64-bit address
+//
+#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL
+
+//
+// Maximum usable address at boot time (48 bits using 4KB pages)
+//
+#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL
+
+//
+// Maximum legal LoongArch 64-bit INTN and UINTN values.
+//
+#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)
+#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)
+
+//
+// Page allocation granularity for LoongArch
+//
+#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)
+#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000)
+
+#if defined (__GNUC__)
+//
+// For GNU assembly code, .global or .globl can declare global symbols.
+// Define this macro to unify the usage.
+//
+#define ASM_GLOBAL .globl
+#endif
+
+//
+// The stack alignment required for LoongArch
+//
+#define CPU_STACK_ALIGNMENT 16
+
+/**
+ Return the pointer to the first instruction of a function given a function pointer.
+ On LOONGARCH CPU architectures, these two pointer values are the same,
+ so the implementation of this macro is very simple.
+
+ @param FunctionPointer A pointer to a function.
+
+ @return The pointer to the first instruction of a function given a function pointer.
+
+**/
+#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPointer)
+
+#ifndef __USER_LABEL_PREFIX__
+#define __USER_LABEL_PREFIX__
+#endif
+
+#endif
diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec
index f1ebf9e251..4c81cbd75a 100644
--- a/MdePkg/MdePkg.dec
+++ b/MdePkg/MdePkg.dec
@@ -7,6 +7,7 @@
# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -43,6 +44,9 @@
[Includes.RISCV64]
Include/RiscV64
+[Includes.LOONGARCH64]
+ Include/LoongArch64
+
[LibraryClasses]
## @libraryclass Provides most usb APIs to support the Hid requests defined in Usb Hid 1.1 spec
# and the standard requests defined in Usb 1.1 spec.
diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc
index cc1ac196a9..493a13ec91 100644
--- a/MdePkg/MdePkg.dsc
+++ b/MdePkg/MdePkg.dsc
@@ -4,6 +4,7 @@
# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -15,7 +16,7 @@
PLATFORM_VERSION = 1.08
DSC_SPECIFICATION = 0x00010005
OUTPUT_DIRECTORY = Build/Mde
- SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64
+ SUPPORTED_ARCHITECTURES = IA32|X64|EBC|ARM|AARCH64|RISCV64|LOONGARCH64
BUILD_TARGETS = DEBUG|RELEASE|NOOPT
SKUID_IDENTIFIER = DEFAULT
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 23/34] MdePkg/Include: LoongArch definitions.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (21 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 22/34] MdePkg: Add LoongArch LOONGARCH64 binding Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 24/34] MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture Chao Li
` (10 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch processor related definitions.
For the Http boot and PXE boot types seeing this URL section "Processor
Architecture Type" for the LOONGARCH values:
https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml
For definitions of PE/COFF and LOONGARCH relocation types, see the
"Machine Types" and "Basic Relocation Types" sections of this URL for
LOONGARCH values:
https://docs.microsoft.com/en-us/windows/win32/debug/pe-format
For the register definitions of exceptions context, see the UEFI V2.10
18.2.2, 18.2.4 and 18.2.5 sections of this URL for LOONGARCH
definitions:
https://uefi.org/specs/UEFI/2.10/18_Protocols_Debugger_Support.html
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdePkg/Include/IndustryStandard/PeImage.h | 9 ++
MdePkg/Include/Protocol/DebugSupport.h | 107 ++++++++++++++++++++--
MdePkg/Include/Protocol/PxeBaseCode.h | 3 +
MdePkg/Include/Uefi/UefiBaseType.h | 14 +++
MdePkg/Include/Uefi/UefiSpec.h | 16 ++--
5 files changed, 136 insertions(+), 13 deletions(-)
diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/IndustryStandard/PeImage.h
index 3109dc20f8..dd4cc25483 100644
--- a/MdePkg/Include/IndustryStandard/PeImage.h
+++ b/MdePkg/Include/IndustryStandard/PeImage.h
@@ -10,6 +10,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -38,6 +39,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define IMAGE_FILE_MACHINE_RISCV32 0x5032
#define IMAGE_FILE_MACHINE_RISCV64 0x5064
#define IMAGE_FILE_MACHINE_RISCV128 0x5128
+#define IMAGE_FILE_MACHINE_LOONGARCH32 0x6232
+#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264
//
// EXE file formats
@@ -503,6 +506,12 @@ typedef struct {
#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7
#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8
+//
+// Relocation types of LoongArch processor.
+//
+#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8
+#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8
+
///
/// Line number format.
///
diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protocol/DebugSupport.h
index ec5b92a5c5..2b0ae2d157 100644
--- a/MdePkg/Include/Protocol/DebugSupport.h
+++ b/MdePkg/Include/Protocol/DebugSupport.h
@@ -654,17 +654,110 @@ typedef struct {
UINT64 X31;
} EFI_SYSTEM_CONTEXT_RISCV64;
+//
+// LoongArch processor exception types.
+//
+#define EXCEPT_LOONGARCH_INT 0
+#define EXCEPT_LOONGARCH_PIL 1
+#define EXCEPT_LOONGARCH_PIS 2
+#define EXCEPT_LOONGARCH_PIF 3
+#define EXCEPT_LOONGARCH_PME 4
+#define EXCEPT_LOONGARCH_PNR 5
+#define EXCEPT_LOONGARCH_PNX 6
+#define EXCEPT_LOONGARCH_PPI 7
+#define EXCEPT_LOONGARCH_ADE 8
+#define EXCEPT_LOONGARCH_ALE 9
+#define EXCEPT_LOONGARCH_BCE 10
+#define EXCEPT_LOONGARCH_SYS 11
+#define EXCEPT_LOONGARCH_BRK 12
+#define EXCEPT_LOONGARCH_INE 13
+#define EXCEPT_LOONGARCH_IPE 14
+#define EXCEPT_LOONGARCH_FPD 15
+#define EXCEPT_LOONGARCH_SXD 16
+#define EXCEPT_LOONGARCH_ASXD 17
+#define EXCEPT_LOONGARCH_FPE 18
+#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type in the ISA spec, the TLB refill is defined for an independent exception.
+
+//
+// LoongArch processor Interrupt types.
+//
+#define EXCEPT_LOONGARCH_INT_SIP0 0
+#define EXCEPT_LOONGARCH_INT_SIP1 1
+#define EXCEPT_LOONGARCH_INT_IP0 2
+#define EXCEPT_LOONGARCH_INT_IP1 3
+#define EXCEPT_LOONGARCH_INT_IP2 4
+#define EXCEPT_LOONGARCH_INT_IP3 5
+#define EXCEPT_LOONGARCH_INT_IP4 6
+#define EXCEPT_LOONGARCH_INT_IP5 7
+#define EXCEPT_LOONGARCH_INT_IP6 8
+#define EXCEPT_LOONGARCH_INT_IP7 9
+#define EXCEPT_LOONGARCH_INT_PMC 10
+#define EXCEPT_LOONGARCH_INT_TIMER 11
+#define EXCEPT_LOONGARCH_INT_IPI 12
+
+//
+// For coding convenience, define the maximum valid
+// LoongArch interrupt.
+//
+#define MAX_LOONGARCH_INTERRUPT 14
+
+typedef struct {
+ UINT64 R0;
+ UINT64 R1;
+ UINT64 R2;
+ UINT64 R3;
+ UINT64 R4;
+ UINT64 R5;
+ UINT64 R6;
+ UINT64 R7;
+ UINT64 R8;
+ UINT64 R9;
+ UINT64 R10;
+ UINT64 R11;
+ UINT64 R12;
+ UINT64 R13;
+ UINT64 R14;
+ UINT64 R15;
+ UINT64 R16;
+ UINT64 R17;
+ UINT64 R18;
+ UINT64 R19;
+ UINT64 R20;
+ UINT64 R21;
+ UINT64 R22;
+ UINT64 R23;
+ UINT64 R24;
+ UINT64 R25;
+ UINT64 R26;
+ UINT64 R27;
+ UINT64 R28;
+ UINT64 R29;
+ UINT64 R30;
+ UINT64 R31;
+
+ UINT64 CRMD; // CuRrent MoDe information
+ UINT64 PRMD; // PRe-exception MoDe information
+ UINT64 EUEN; // Extended component Unit ENable
+ UINT64 MISC; // MISCellaneous controller
+ UINT64 ECFG; // Exception ConFiGuration
+ UINT64 ESTAT; // Exception STATus
+ UINT64 ERA; // Exception Return Address
+ UINT64 BADV; // BAD Virtual address
+ UINT64 BADI; // BAD Instruction
+} EFI_SYSTEM_CONTEXT_LOONGARCH64;
+
///
/// Universal EFI_SYSTEM_CONTEXT definition.
///
typedef union {
- EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
- EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
- EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
- EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
- EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
- EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
- EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
+ EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;
+ EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;
+ EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;
+ EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;
+ EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;
+ EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;
+ EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;
+ EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLoongArch64;
} EFI_SYSTEM_CONTEXT;
//
diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protocol/PxeBaseCode.h
index 11872d602d..6787941a5d 100644
--- a/MdePkg/Include/Protocol/PxeBaseCode.h
+++ b/MdePkg/Include/Protocol/PxeBaseCode.h
@@ -4,6 +4,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -158,6 +159,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT;
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B
#elif defined (MDE_CPU_RISCV64)
#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B
+#elif defined (MDE_CPU_LOONGARCH64)
+#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0027
#endif
///
diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiBaseType.h
index 4a34ce8e25..83975a08eb 100644
--- a/MdePkg/Include/Uefi/UefiBaseType.h
+++ b/MdePkg/Include/Uefi/UefiBaseType.h
@@ -4,6 +4,7 @@
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -246,6 +247,12 @@ typedef union {
#define EFI_IMAGE_MACHINE_RISCV64 0x5064
#define EFI_IMAGE_MACHINE_RISCV128 0x5128
+///
+/// PE32+ Machine type for LoongArch 32/64 images.
+///
+#define EFI_IMAGE_MACHINE_LOONGARCH32 0x6232
+#define EFI_IMAGE_MACHINE_LOONGARCH64 0x6264
+
#if !defined (EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined (EFI_IMAGE_MACHINE_CROSS_TYPE_VALUE)
#if defined (MDE_CPU_IA32)
@@ -278,6 +285,13 @@ typedef union {
#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
((Machine) == EFI_IMAGE_MACHINE_RISCV64)
+#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
+
+ #elif defined (MDE_CPU_LOONGARCH64)
+
+#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \
+ ((Machine) == EFI_IMAGE_MACHINE_LOONGARCH64)
+
#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)
#elif defined (MDE_CPU_EBC)
diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h
index 2b38b100f6..3abebbb8d9 100644
--- a/MdePkg/Include/Uefi/UefiSpec.h
+++ b/MdePkg/Include/Uefi/UefiSpec.h
@@ -7,6 +7,7 @@
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -2195,12 +2196,13 @@ typedef struct {
//
// EFI File location to boot from on removable media devices
//
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
-#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.EFI"
+#define EFI_REMOVABLE_MEDIA_FILE_NAME_LOONGARCH64 L"\\EFI\\BOOT\\BOOTLOONGARCH64.EFI"
#if !defined (EFI_REMOVABLE_MEDIA_FILE_NAME)
#if defined (MDE_CPU_IA32)
@@ -2214,6 +2216,8 @@ typedef struct {
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64
#elif defined (MDE_CPU_RISCV64)
#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64
+ #elif defined (MDE_CPU_LOONGARCH64)
+#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_LOONGARCH64
#else
#error Unknown Processor Type
#endif
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 24/34] MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (22 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 23/34] MdePkg/Include: LoongArch definitions Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 25/34] MdePkg/BaseCacheMaintenanceLib: LoongArch cache maintenance implementation Chao Li
` (9 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Baoqi Zhang
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch LOONGARCH64 BaseLib functions.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/Include/Library/BaseLib.h | 24 ++++++++
MdePkg/Library/BaseLib/BaseLib.inf | 16 ++++-
MdePkg/Library/BaseLib/LoongArch64/Barrier.S | 28 +++++++++
.../BaseLib/LoongArch64/CpuBreakpoint.S | 24 ++++++++
MdePkg/Library/BaseLib/LoongArch64/CpuPause.S | 31 ++++++++++
.../BaseLib/LoongArch64/DisableInterrupts.S | 21 +++++++
.../BaseLib/LoongArch64/EnableInterrupts.S | 21 +++++++
.../BaseLib/LoongArch64/GetInterruptState.S | 35 +++++++++++
.../BaseLib/LoongArch64/InternalSwitchStack.c | 58 +++++++++++++++++++
.../Library/BaseLib/LoongArch64/MemoryFence.S | 18 ++++++
.../BaseLib/LoongArch64/SetJumpLongJump.S | 49 ++++++++++++++++
.../Library/BaseLib/LoongArch64/SwitchStack.S | 39 +++++++++++++
12 files changed, 363 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Barrier.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuPause.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S
diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index a6f9a194ef..f3f59f21c2 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -6,6 +6,7 @@ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -152,6 +153,29 @@ typedef struct {
#endif // defined (MDE_CPU_RISCV64)
+#if defined (MDE_CPU_LOONGARCH64)
+///
+/// The LoongArch architecture context buffer used by SetJump() and LongJump()
+///
+typedef struct {
+ UINT64 S0;
+ UINT64 S1;
+ UINT64 S2;
+ UINT64 S3;
+ UINT64 S4;
+ UINT64 S5;
+ UINT64 S6;
+ UINT64 S7;
+ UINT64 S8;
+ UINT64 SP;
+ UINT64 FP;
+ UINT64 RA;
+} BASE_LIBRARY_JUMP_BUFFER;
+
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
+
+#endif // defined (MDE_CPU_LOONGARCH64)
+
//
// String Services
//
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 6be5be9428..9ed46a584a 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -21,7 +21,7 @@
LIBRARY_CLASS = BaseLib
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
@@ -402,6 +402,20 @@
RiscV64/RiscVInterrupt.S | GCC
RiscV64/FlushCache.S | GCC
+[Sources.LOONGARCH64]
+ Math64.c
+ Unaligned.c
+ LoongArch64/InternalSwitchStack.c
+ LoongArch64/GetInterruptState.S | GCC
+ LoongArch64/EnableInterrupts.S | GCC
+ LoongArch64/DisableInterrupts.S | GCC
+ LoongArch64/Barrier.S | GCC
+ LoongArch64/MemoryFence.S | GCC
+ LoongArch64/CpuBreakpoint.S | GCC
+ LoongArch64/CpuPause.S | GCC
+ LoongArch64/SetJumpLongJump.S | GCC
+ LoongArch64/SwitchStack.S | GCC
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseLib/LoongArch64/Barrier.S b/MdePkg/Library/BaseLib/LoongArch64/Barrier.S
new file mode 100644
index 0000000000..58f21ad725
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/Barrier.S
@@ -0,0 +1,28 @@
+#------------------------------------------------------------------------------
+#
+# LoongArch Barrier Operations
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(AsmDataBarrierLoongArch)
+ASM_GLOBAL ASM_PFX(AsmInstructionBarrierLoongArch)
+
+#
+# Data barrier operation for LoongArch.
+#
+ASM_PFX(AsmDataBarrierLoongArch):
+ dbar 0
+ jirl $zero, $ra, 0
+
+#
+# Instruction barrier operation for LoongArch.
+#
+ASM_PFX(AsmInstructionBarrierLoongArch):
+ ibar 0
+ jirl $zero, $ra, 0
+
+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S b/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S
new file mode 100644
index 0000000000..4e022e9bb5
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S
@@ -0,0 +1,24 @@
+#------------------------------------------------------------------------------
+#
+# CpuBreakpoint for LoongArch
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(CpuBreakpoint)
+
+#/**
+# Generates a breakpoint on the CPU.
+#
+# Generates a breakpoint on the CPU. The breakpoint must be implemented such
+# that code can resume normal execution after the breakpoint.
+#
+#**/
+
+ASM_PFX(CpuBreakpoint):
+ break 3
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S b/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S
new file mode 100644
index 0000000000..e9140e8742
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S
@@ -0,0 +1,31 @@
+#------------------------------------------------------------------------------
+#
+# CpuPause for LoongArch
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(CpuPause)
+
+#/**
+# Requests CPU to pause for a short period of time.
+#
+# Requests CPU to pause for a short period of time. Typically used in MP
+# systems to prevent memory starvation while waiting for a spin lock.
+#
+#**/
+
+ASM_PFX(CpuPause):
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
new file mode 100644
index 0000000000..0f228339af
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
@@ -0,0 +1,21 @@
+#------------------------------------------------------------------------------
+#
+# LoongArch interrupt disable
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(DisableInterrupts)
+
+#/**
+# Disables CPU interrupts.
+#**/
+
+ASM_PFX(DisableInterrupts):
+ li.w $t0, 0x4
+ csrxchg $zero, $t0, 0x0
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
new file mode 100644
index 0000000000..3c34fb2cdd
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
@@ -0,0 +1,21 @@
+#------------------------------------------------------------------------------
+#
+# LoongArch interrupt enable
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(EnableInterrupts)
+
+#/**
+# Enables CPU interrupts.
+#**/
+
+ASM_PFX(EnableInterrupts):
+ li.w $t0, 0x4
+ csrxchg $t0, $t0, 0x0
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S b/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S
new file mode 100644
index 0000000000..bfd1f2d5f7
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S
@@ -0,0 +1,35 @@
+#------------------------------------------------------------------------------
+#
+# Get LoongArch interrupt status
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(GetInterruptState)
+
+#/**
+# Retrieves the current CPU interrupt state.
+#
+# Returns TRUE means interrupts are currently enabled. Otherwise,
+# returns FALSE.
+#
+# @retval TRUE CPU interrupts are enabled.
+# @retval FALSE CPU interrupts are disabled.
+#
+#**/
+
+ASM_PFX(GetInterruptState):
+ li.w $t1, 0x4
+ csrrd $t0, 0x0
+ and $t0, $t0, $t1
+ beqz $t0, 1f
+ li.w $a0, 0x1
+ b 2f
+1:
+ li.w $a0, 0x0
+2:
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c b/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c
new file mode 100644
index 0000000000..859bc96329
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c
@@ -0,0 +1,58 @@
+/** @file
+ SwitchStack() function for LoongArch.
+
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BaseLibInternals.h"
+
+UINTN
+EFIAPI
+InternalSwitchStackAsm (
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer
+ );
+
+/**
+ Transfers control to a function starting with a new stack.
+
+ Transfers control to the function specified by EntryPoint using the
+ new stack specified by NewStack and passing in the parameters specified
+ by Context1 and Context2. Context1 and Context2 are optional and may
+ be NULL. The function EntryPoint must never return.
+
+ If EntryPoint is NULL, then ASSERT().
+ If NewStack is NULL, then ASSERT().
+
+ @param[in] EntryPoint A pointer to function to call with the new stack.
+ @param[in] Context1 A pointer to the context to pass into the EntryPoint
+ function.
+ @param[in] Context2 A pointer to the context to pass into the EntryPoint
+ function.
+ @param[in] NewStack A pointer to the new stack to use for the EntryPoint
+ function.
+ @param[in] Marker VA_LIST marker for the variable argument list.
+
+**/
+VOID
+EFIAPI
+InternalSwitchStack (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1 OPTIONAL,
+ IN VOID *Context2 OPTIONAL,
+ IN VOID *NewStack,
+ IN VA_LIST Marker
+ )
+
+{
+ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
+
+ JumpBuffer.RA = (UINTN)EntryPoint;
+ JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);
+ JumpBuffer.SP -= sizeof (Context1) + sizeof (Context2);
+ ((VOID **)(UINTN)JumpBuffer.SP)[0] = Context1;
+ ((VOID **)(UINTN)JumpBuffer.SP)[1] = Context2;
+
+ InternalSwitchStackAsm (&JumpBuffer);
+}
diff --git a/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S b/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S
new file mode 100644
index 0000000000..2b3d34366f
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S
@@ -0,0 +1,18 @@
+#------------------------------------------------------------------------------
+#
+# MemoryFence() for LoongArch
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(MemoryFence)
+
+#
+# Memory fence for LoongArch
+#
+ASM_PFX(MemoryFence):
+ b AsmDataBarrierLoongArch
+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S b/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S
new file mode 100644
index 0000000000..1c6ee54b6f
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S
@@ -0,0 +1,49 @@
+#------------------------------------------------------------------------------
+#
+# Set/Long jump for LoongArch
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#define STORE st.d /* 64 bit mode regsave instruction */
+#define LOAD ld.d /* 64 bit mode regload instruction */
+#define RSIZE 8 /* 64 bit mode register size */
+
+ASM_GLOBAL ASM_PFX(SetJump)
+ASM_GLOBAL ASM_PFX(InternalLongJump)
+
+ASM_PFX(SetJump):
+ STORE $s0, $a0, RSIZE * 0
+ STORE $s1, $a0, RSIZE * 1
+ STORE $s2, $a0, RSIZE * 2
+ STORE $s3, $a0, RSIZE * 3
+ STORE $s4, $a0, RSIZE * 4
+ STORE $s5, $a0, RSIZE * 5
+ STORE $s6, $a0, RSIZE * 6
+ STORE $s7, $a0, RSIZE * 7
+ STORE $s8, $a0, RSIZE * 8
+ STORE $sp, $a0, RSIZE * 9
+ STORE $fp, $a0, RSIZE * 10
+ STORE $ra, $a0, RSIZE * 11
+ li.w $a0, 0 # Setjmp return
+ jirl $zero, $ra, 0
+
+ASM_PFX(InternalLongJump):
+ LOAD $ra, $a0, RSIZE * 11
+ LOAD $s0, $a0, RSIZE * 0
+ LOAD $s1, $a0, RSIZE * 1
+ LOAD $s2, $a0, RSIZE * 2
+ LOAD $s3, $a0, RSIZE * 3
+ LOAD $s4, $a0, RSIZE * 4
+ LOAD $s5, $a0, RSIZE * 5
+ LOAD $s6, $a0, RSIZE * 6
+ LOAD $s7, $a0, RSIZE * 7
+ LOAD $s8, $a0, RSIZE * 8
+ LOAD $sp, $a0, RSIZE * 9
+ LOAD $fp, $a0, RSIZE * 10
+ move $a0, $a1
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S b/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S
new file mode 100644
index 0000000000..ad9aa8b343
--- /dev/null
+++ b/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------
+#
+# InternalSwitchStackAsm for LoongArch
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+#define STORE st.d /* 64 bit mode regsave instruction */
+#define LOAD ld.d /* 64 bit mode regload instruction */
+#define RSIZE 8 /* 64 bit mode register size */
+
+ASM_GLOBAL ASM_PFX(InternalSwitchStackAsm)
+
+/**
+ This allows the caller to switch the stack and goes to the new entry point
+
+ @param JumpBuffer A pointer to CPU context buffer.
+**/
+
+ASM_PFX(InternalSwitchStackAsm):
+ LOAD $ra, $a0, RSIZE * 11
+ LOAD $s0, $a0, RSIZE * 0
+ LOAD $s1, $a0, RSIZE * 1
+ LOAD $s2, $a0, RSIZE * 2
+ LOAD $s3, $a0, RSIZE * 3
+ LOAD $s4, $a0, RSIZE * 4
+ LOAD $s5, $a0, RSIZE * 5
+ LOAD $s6, $a0, RSIZE * 6
+ LOAD $s7, $a0, RSIZE * 7
+ LOAD $s8, $a0, RSIZE * 8
+ LOAD $sp, $a0, RSIZE * 9
+ LOAD $fp, $a0, RSIZE * 10
+ LOAD $a0, $sp, 0
+ LOAD $a1, $sp, 8
+ jirl $zero, $ra, 0
+ .end
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 25/34] MdePkg/BaseCacheMaintenanceLib: LoongArch cache maintenance implementation.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (23 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 24/34] MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 26/34] MdePkg/BaseIoLibIntrinsic: IoLibNoIo for LoongArch architecture Chao Li
` (8 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Implement LoongArch cache maintenance functions in
BaseCacheMaintenanceLib.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
.../BaseCacheMaintenanceLib.inf | 6 +-
.../BaseCacheMaintenanceLib/LoongArchCache.c | 254 ++++++++++++++++++
2 files changed, 259 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
index 33114243d5..6fd9cbe5f6 100644
--- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
@@ -7,6 +7,7 @@
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -24,7 +25,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources.IA32]
@@ -45,6 +46,9 @@
[Sources.RISCV64]
RiscVCache.c
+[Sources.LOONGARCH64]
+ LoongArchCache.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c b/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c
new file mode 100644
index 0000000000..4c8773278c
--- /dev/null
+++ b/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c
@@ -0,0 +1,254 @@
+/** @file
+ Cache Maintenance Functions for LoongArch.
+ LoongArch cache maintenance functions has not yet been completed, and will added in later.
+ Functions are null functions now.
+
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+//
+// Include common header file for this module.
+//
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+
+/**
+ LoongArch data barrier operation.
+**/
+VOID
+EFIAPI
+AsmDataBarrierLoongArch (
+ VOID
+ );
+
+/**
+ LoongArch instruction barrier operation.
+**/
+VOID
+EFIAPI
+AsmInstructionBarrierLoongArch (
+ VOID
+ );
+
+/**
+ Invalidates the entire instruction cache in cache coherency domain of the
+ calling CPU.
+
+**/
+VOID
+EFIAPI
+InvalidateInstructionCache (
+ VOID
+ )
+{
+ AsmInstructionBarrierLoongArch ();
+}
+
+/**
+ Invalidates a range of instruction cache lines in the cache coherency domain
+ of the calling CPU.
+
+ Invalidates the instruction cache lines specified by Address and Length. If
+ Address is not aligned on a cache line boundary, then entire instruction
+ cache line containing Address is invalidated. If Address + Length is not
+ aligned on a cache line boundary, then the entire instruction cache line
+ containing Address + Length -1 is invalidated. This function may choose to
+ invalidate the entire instruction cache if that is more efficient than
+ invalidating the specified range. If Length is 0, the no instruction cache
+ lines are invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param[in] Address The base address of the instruction cache lines to
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+
+ @param[in] Length The number of bytes to invalidate from the instruction cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ AsmInstructionBarrierLoongArch ();
+ return Address;
+}
+
+/**
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU.
+
+ Writes Back and Invalidates the entire data cache in cache coherency domain
+ of the calling CPU. This function guarantees that all dirty cache lines are
+ written back to system memory, and also invalidates all the data cache lines
+ in the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));
+}
+
+/**
+ Writes Back and Invalidates a range of data cache lines in the cache
+ coherency domain of the calling CPU.
+
+ Writes Back and Invalidate the data cache lines specified by Address and
+ Length. If Address is not aligned on a cache line boundary, then entire data
+ cache line containing Address is written back and invalidated. If Address +
+ Length is not aligned on a cache line boundary, then the entire data cache
+ line containing Address + Length -1 is written back and invalidated. This
+ function may choose to write back and invalidate the entire data cache if
+ that is more efficient than writing back and invalidating the specified
+ range. If Length is 0, the no data cache lines are written back and
+ invalidated. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param[in] Address The base address of the data cache lines to write back and
+ invalidate. If the CPU is in a physical addressing mode, then
+ Address is a physical address. If the CPU is in a virtual
+ addressing mode, then Address is a virtual address.
+ @param[in] Length The number of bytes to write back and invalidate from the
+ data cache.
+
+ @return Address of cache invalidation.
+
+**/
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Writes Back the entire data cache in cache coherency domain of the calling
+ CPU. This function guarantees that all dirty cache lines are written back to
+ system memory. This function may also invalidate all the data cache lines in
+ the cache coherency domain of the calling CPU.
+
+**/
+VOID
+EFIAPI
+WriteBackDataCache (
+ VOID
+ )
+{
+ WriteBackInvalidateDataCache ();
+}
+
+/**
+ Writes Back a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Writes Back the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is written back. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is written back. This function may choose to write back the entire
+ data cache if that is more efficient than writing back the specified range.
+ If Length is 0, the no data cache lines are written back. This function may
+ also invalidate all the data cache lines in the specified range of the cache
+ coherency domain of the calling CPU. Address is returned.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param[in] Address The base address of the data cache lines to write back. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing
+ mode, then Address is a virtual address.
+ @param[in] Length The number of bytes to write back from the data cache.
+
+ @return Address of cache written in main memory.
+
+**/
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __FUNCTION__));
+ return Address;
+}
+
+/**
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU.
+
+ Invalidates the entire data cache in cache coherency domain of the calling
+ CPU. This function must be used with care because dirty cache lines are not
+ written back to system memory. It is typically used for cache diagnostics. If
+ the CPU does not support invalidation of the entire data cache, then a write
+ back and invalidate operation should be performed on the entire data cache.
+
+**/
+VOID
+EFIAPI
+InvalidateDataCache (
+ VOID
+ )
+{
+ AsmDataBarrierLoongArch ();
+}
+
+/**
+ Invalidates a range of data cache lines in the cache coherency domain of the
+ calling CPU.
+
+ Invalidates the data cache lines specified by Address and Length. If Address
+ is not aligned on a cache line boundary, then entire data cache line
+ containing Address is invalidated. If Address + Length is not aligned on a
+ cache line boundary, then the entire data cache line containing Address +
+ Length -1 is invalidated. This function must never invalidate any cache lines
+ outside the specified range. If Length is 0, the no data cache lines are
+ invalidated. Address is returned. This function must be used with care
+ because dirty cache lines are not written back to system memory. It is
+ typically used for cache diagnostics. If the CPU does not support
+ invalidation of a data cache range, then a write back and invalidate
+ operation should be performed on the data cache range.
+
+ If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().
+
+ @param[in] Address The base address of the data cache lines to invalidate. If
+ the CPU is in a physical addressing mode, then Address is a
+ physical address. If the CPU is in a virtual addressing mode,
+ then Address is a virtual address.
+ @param[in] Length The number of bytes to invalidate from the data cache.
+
+ @return Address.
+
+**/
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+ IN VOID *Address,
+ IN UINTN Length
+ )
+{
+ AsmDataBarrierLoongArch ();
+ return Address;
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 26/34] MdePkg/BaseIoLibIntrinsic: IoLibNoIo for LoongArch architecture.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (24 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 25/34] MdePkg/BaseCacheMaintenanceLib: LoongArch cache maintenance implementation Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 27/34] MdePkg/BasePeCoff: Add LoongArch PE/Coff related code Chao Li
` (7 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
LoongArch MMIO library instance, use the IoLibNoIo.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
.../Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 10 +++++++---
MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c | 3 ++-
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
index 27b15d9ae2..aeb072ee95 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
@@ -4,13 +4,14 @@
# I/O Library that uses compiler intrinsics to perform IN and OUT instructions
# for IA-32 and x64. On IPF, I/O port requests are translated into MMIO requests.
# MMIO requests are forwarded directly to memory. For EBC, I/O port requests
-# ASSERT(). For ARM, AARCH64 and RISCV64, this I/O library only provides non I/O
-# read and write.
+# ASSERT(). For ARM, AARCH64, RISCV64 and LoongArch, this I/O library only provides
+# non I/O read and write.
#
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -27,7 +28,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
@@ -62,6 +63,9 @@
[Sources.RISCV64]
IoLibNoIo.c
+[Sources.LOONGARCH64]
+ IoLibNoIo.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
index c71f45b22e..c51e5da39b 100644
--- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
+++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c
@@ -1,11 +1,12 @@
/** @file
I/O library for non I/O read and write access (memory map I/O read and
- write only) architecture, such as ARM and RISC-V processor.
+ write only) architecture, such as ARM, RISC-V and LoongArch processor.
Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 27/34] MdePkg/BasePeCoff: Add LoongArch PE/Coff related code.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (25 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 26/34] MdePkg/BaseIoLibIntrinsic: IoLibNoIo for LoongArch architecture Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 28/34] MdePkg/BaseCpuLib: LoongArch Base CPU library implementation Chao Li
` (6 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Baoqi Zhang
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch image relocation.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
.../Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
.../Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
.../BasePeCoffLib/LoongArch/PeCoffLoaderEx.c | 137 ++++++++++++++++++
4 files changed, 146 insertions(+), 1 deletion(-)
create mode 100644 MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
index 6d8d9faeb8..97a8aaf8c7 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c
@@ -1,6 +1,6 @@
/** @file
Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but
- only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.
+ only supports relocating IA32, x64, IPF, ARM, RISC-V, LoongArch and EBC images.
Caution: This file requires additional review when modified.
This library will have external input - PE/COFF image.
@@ -18,6 +18,7 @@
Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
index 110b6d5a09..3b8b8eb191 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
@@ -4,6 +4,7 @@
# The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
# The X64 version library support loading IA32, X64 and EBC PE/COFF images.
# The RISC-V version library support loading RISC-V images.
+# The LoongArch version library support loading LoongArch images.
#
# Caution: This module requires additional review when modified.
# This library will have external input - PE/COFF image.
@@ -13,6 +14,7 @@
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -46,6 +48,9 @@
[Sources.RISCV64]
RiscV/PeCoffLoaderEx.c
+[Sources.LOONGARCH64]
+ LoongArch/PeCoffLoaderEx.c
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
index 55417029f2..1f731344e1 100644
--- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
+++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni
@@ -5,6 +5,7 @@
// The IA32 version library support loading IA32, X64 and EBC PE/COFF images.
// The X64 version library support loading IA32, X64 and EBC PE/COFF images.
// The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COFF images.
+// The LoongArch version library support loading LoongArch32 and LoongArch64 PE/COFF images.
//
// Caution: This module requires additional review when modified.
// This library will have external input - PE/COFF image.
@@ -14,6 +15,7 @@
// Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
// Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
diff --git a/MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c b/MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c
new file mode 100644
index 0000000000..417096f334
--- /dev/null
+++ b/MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c
@@ -0,0 +1,137 @@
+/** @file
+ PE/Coff loader for LoongArch PE image
+
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "BasePeCoffLibInternals.h"
+#include <Library/BaseLib.h>
+
+/**
+ Performs an LoongArch specific relocation fixup and is a no-op on other
+ instruction sets.
+
+ @param[in] Reloc Pointer to the relocation record.
+ @param[in, out] Fixup Pointer to the address to fix up.
+ @param[in, out] FixupData Pointer to a buffer to log the fixups.
+ @param[in] Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeCoffLoaderRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ UINT8 RelocType;
+ UINT64 Value;
+ UINT64 Tmp1;
+ UINT64 Tmp2;
+
+ RelocType = (*Reloc) >> 12;
+ Value = 0;
+ Tmp1 = 0;
+ Tmp2 = 0;
+
+ switch (RelocType) {
+ case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA:
+ // The next four instructions are used to load a 64 bit address, relocate all of them
+ Value = (*(UINT32 *)Fixup & 0x1ffffe0) << 7 | // lu12i.w 20bits from bit5
+ (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori 12bits from bit10
+ Tmp1 = *((UINT32 *)Fixup + 2) & 0x1ffffe0; // lu32i.d 20bits from bit5
+ Tmp2 = *((UINT32 *)Fixup + 3) & 0x3ffc00; // lu52i.d 12bits from bit10
+ Value = Value | (Tmp1 << 27) | (Tmp2 << 42);
+ Value += Adjust;
+
+ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 12) & 0xfffff) << 5);
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
+ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
+ *FixupData = *FixupData + sizeof (UINT32);
+ }
+
+ Fixup += sizeof (UINT32);
+ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x3ffc00) | ((Value & 0xfff) << 10);
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
+ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
+ *FixupData = *FixupData + sizeof (UINT32);
+ }
+
+ Fixup += sizeof (UINT32);
+ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 32) & 0xfffff) << 5);
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
+ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
+ *FixupData = *FixupData + sizeof (UINT32);
+ }
+
+ Fixup += sizeof (UINT32);
+ *(UINT32 *)Fixup = (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value >> 52) & 0xfff) << 10);
+ if (*FixupData != NULL) {
+ *FixupData = ALIGN_POINTER (*FixupData, sizeof (UINT32));
+ *(UINT32 *)(*FixupData) = *(UINT32 *)Fixup;
+ *FixupData = *FixupData + sizeof (UINT32);
+ }
+
+ break;
+ default:
+ return RETURN_UNSUPPORTED;
+ }
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Returns TRUE if the machine type of PE/COFF image is supported. Supported
+ does not mean the image can be executed it means the PE/COFF loader supports
+ loading and relocating of the image type. It's up to the caller to support
+ the entry point.
+
+ @param[in] Machine Machine type from the PE Header.
+
+ @return TRUE if this PE/COFF loader can load the image
+
+**/
+BOOLEAN
+PeCoffLoaderImageFormatSupported (
+ IN UINT16 Machine
+ )
+{
+ if (Machine == IMAGE_FILE_MACHINE_LOONGARCH64) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Performs an LOONGARCH-based specific re-relocation fixup and is a no-op on other
+ instruction sets. This is used to re-relocated the image into the EFI virtual
+ space for runtime calls.
+
+ @param[in] Reloc The pointer to the relocation record.
+ @param[in, out] Fixup The pointer to the address to fix up.
+ @param[in, out] FixupData The pointer to a buffer to log the fixups.
+ @param[in] Adjust The offset to adjust the fixup.
+
+ @return Status code.
+
+**/
+RETURN_STATUS
+PeHotRelocateImageEx (
+ IN UINT16 *Reloc,
+ IN OUT CHAR8 *Fixup,
+ IN OUT CHAR8 **FixupData,
+ IN UINT64 Adjust
+ )
+{
+ // To check
+ return PeCoffLoaderRelocateImageEx (Reloc, Fixup, FixupData, Adjust);
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 28/34] MdePkg/BaseCpuLib: LoongArch Base CPU library implementation.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (26 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 27/34] MdePkg/BasePeCoff: Add LoongArch PE/Coff related code Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code Chao Li
` (5 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Implement LoongArch CPU related functions in BaseCpuLib.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 7 ++++++-
MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++--
MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S | 15 +++++++++++++++
MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S | 15 +++++++++++++++
4 files changed, 39 insertions(+), 3 deletions(-)
create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S
create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
index c4cd29a783..6b230f6e6d 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
@@ -8,6 +8,7 @@
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -25,7 +26,7 @@
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources.IA32]
@@ -61,6 +62,10 @@
[Sources.RISCV64]
RiscV/Cpu.S
+[Sources.LOONGARCH64]
+ LoongArch/CpuFlushTlb.S | GCC
+ LoongArch/CpuSleep.S | GCC
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
index 80dc495786..7c5c8dfb37 100644
--- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
+++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni
@@ -1,13 +1,14 @@
// /** @file
// Instance of CPU Library for various architecture.
//
-// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,
+// CPU Library implemented using ASM functions for IA-32, X64, RISCV64 and LoongArch64,
// PAL CALLs for IPF, and empty functions for EBC.
//
// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
// Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+// Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
//
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
@@ -16,5 +17,5 @@
#string STR_MODULE_ABSTRACT #language en-US "Instance of CPU Library for various architectures"
-#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, and empty functions for EBC."
+#string STR_MODULE_DESCRIPTION #language en-US "CPU Library implemented using ASM functions for IA-32, X64, RISCV64 and LoongArch64, PAL CALLs for IPF, and empty functions for EBC."
diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S b/MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S
new file mode 100644
index 0000000000..8b792f0a37
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S
@@ -0,0 +1,15 @@
+#------------------------------------------------------------------------------
+#
+# CpuFlushTlb() for LoongArch64
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(CpuFlushTlb)
+
+ASM_PFX(CpuFlushTlb):
+ tlbflush
+ jirl $zero, $ra, 0
+ .end
diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S b/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S
new file mode 100644
index 0000000000..eb31b10714
--- /dev/null
+++ b/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S
@@ -0,0 +1,15 @@
+#------------------------------------------------------------------------------
+#
+# CpuSleep() for LoongArch64
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+ASM_GLOBAL ASM_PFX(CpuSleep)
+
+ASM_PFX(CpuSleep):
+ idle 0
+ jirl $zero, $ra, 0
+ .end
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (27 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 28/34] MdePkg/BaseCpuLib: LoongArch Base CPU library implementation Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:27 ` Chao Li
2022-09-30 15:08 ` Michael D Kinney
2022-09-27 11:13 ` [PATCH v3 30/34] MdePkg/BaseSafeIntLib: Add LoongArch64 architecture for BaseSafeIntLib Chao Li
` (4 subsequent siblings)
33 siblings, 2 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu, Baoqi Zhang
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Support LoongArch cache related functions.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
---
.../BaseSynchronizationLib.inf | 6 +
.../LoongArch64/AsmSynchronization.S | 122 +++++++++
.../LoongArch64/Synchronization.c | 233 ++++++++++++++++++
3 files changed, 361 insertions(+)
create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
index 02ba12961a..dd66ec1d03 100755
--- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -4,6 +4,7 @@
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -82,6 +83,11 @@
Synchronization.c
RiscV64/Synchronization.S
+[Sources.LOONGARCH64]
+ Synchronization.c
+ LoongArch64/Synchronization.c | GCC
+ LoongArch64/AsmSynchronization.S | GCC
+
[Packages]
MdePkg/MdePkg.dec
diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
new file mode 100644
index 0000000000..3f1b06172d
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
@@ -0,0 +1,122 @@
+#------------------------------------------------------------------------------
+#
+# LoongArch synchronization ASM functions.
+#
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#------------------------------------------------------------------------------
+
+ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange16)
+ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange32)
+ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange64)
+ASM_GLOBAL ASM_PFX(AsmInternalSyncIncrement)
+ASM_GLOBAL ASM_PFX(AsmInternalSyncDecrement)
+
+/**
+UINT32
+EFIAPI
+AsmInternalSyncCompareExchange16 (
+ IN volatile UINT32 *Ptr32,
+ IN UINT64 Mask,
+ IN UINT64 LocalCompareValue,
+ IN UINT64 LocalExchangeValue
+ )
+**/
+ASM_PFX(AsmInternalSyncCompareExchange16):
+1:
+ ll.w $t0, $a0, 0x0
+ and $t1, $t0, $a1
+ bne $t1, $a2, 2f
+ andn $t1, $t0, $a1
+ or $t1, $t1, $a3
+ sc.w $t1, $a0, 0x0
+ beqz $t1, 1b
+ b 3f
+2:
+ dbar 0
+3:
+ move $a0, $t0
+ jirl $zero, $ra, 0
+
+/**
+UINT32
+EFIAPI
+AsmInternalSyncCompareExchange32 (
+ IN volatile UINT32 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
+ )
+**/
+ASM_PFX(AsmInternalSyncCompareExchange32):
+1:
+ ll.w $t0, $a0, 0x0
+ bne $t0, $a1, 2f
+ move $t0, $a2
+ sc.w $t0, $a0, 0x0
+ beqz $t0, 1b
+ b 3f
+2:
+ dbar 0
+3:
+ move $a0, $t0
+ jirl $zero, $ra, 0
+
+/**
+UINT64
+EFIAPI
+AsmInternalSyncCompareExchange64 (
+ IN volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
+ )
+**/
+ASM_PFX(AsmInternalSyncCompareExchange64):
+1:
+ ll.d $t0, $a0, 0x0
+ bne $t0, $a1, 2f
+ move $t0, $a2
+ sc.d $t0, $a0, 0x0
+ beqz $t0, 1b
+ b 3f
+2:
+ dbar 0
+3:
+ move $a0, $t0
+ jirl $zero, $ra, 0
+
+/**
+UINT32
+EFIAPI
+AsmInternalSyncIncrement (
+ IN volatile UINT32 *Value
+ )
+**/
+ASM_PFX(AsmInternalSyncIncrement):
+ move $t0, $a0
+ dbar 0
+ ld.w $t1, $t0, 0x0
+ li.w $t2, 1
+ amadd.w $t1, $t2, $t0
+
+ ld.w $a0, $t0, 0x0
+ jirl $zero, $ra, 0
+
+/**
+UINT32
+EFIAPI
+AsmInternalSyncDecrement (
+ IN volatile UINT32 *Value
+ )
+**/
+ASM_PFX(AsmInternalSyncDecrement):
+ move $t0, $a0
+ dbar 0
+ ld.w $t1, $t0, 0x0
+ li.w $t2, -1
+ amadd.w $t1, $t2, $t0
+
+ ld.w $a0, $t0, 0x0
+ jirl $zero, $ra, 0
+.end
diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
new file mode 100644
index 0000000000..d696c8ce10
--- /dev/null
+++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
@@ -0,0 +1,233 @@
+/** @file
+ LoongArch synchronization functions.
+
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Library/DebugLib.h>
+
+UINT32
+EFIAPI
+AsmInternalSyncCompareExchange16 (
+ IN volatile UINT32 *,
+ IN UINT64,
+ IN UINT64,
+ IN UINT64
+ );
+
+UINT32
+EFIAPI
+AsmInternalSyncCompareExchange32 (
+ IN volatile UINT32 *,
+ IN UINT64,
+ IN UINT64
+ );
+
+UINT64
+EFIAPI
+AsmInternalSyncCompareExchange64 (
+ IN volatile UINT64 *,
+ IN UINT64,
+ IN UINT64
+ );
+
+UINT32
+EFIAPI
+AsmInternalSyncIncrement (
+ IN volatile UINT32 *
+ );
+
+UINT32
+EFIAPI
+AsmInternalSyncDecrement (
+ IN volatile UINT32 *
+ );
+
+/**
+ Performs an atomic compare exchange operation on a 16-bit
+ unsigned integer.
+
+ Performs an atomic compare exchange operation on the 16-bit
+ unsigned integer specified by Value. If Value is equal to
+ CompareValue, then Value is set to ExchangeValue and
+ CompareValue is returned. If Value is not equal to
+ CompareValue, then Value is returned. The compare exchange
+ operation must be performed using MP safe mechanisms.
+
+ @param[in] Value A pointer to the 16-bit value for the
+ compare exchange operation.
+ @param[in] CompareValue 16-bit value used in compare operation.
+ @param[in] ExchangeValue 16-bit value used in exchange operation.
+
+ @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InternalSyncCompareExchange16 (
+ IN volatile UINT16 *Value,
+ IN UINT16 CompareValue,
+ IN UINT16 ExchangeValue
+ )
+{
+ UINT32 RetValue;
+ UINT32 Shift;
+ UINT64 Mask;
+ UINT64 LocalCompareValue;
+ UINT64 LocalExchangeValue;
+ volatile UINT32 *Ptr32;
+
+ /* Check that ptr is naturally aligned */
+ ASSERT (!((UINT64)Value & (sizeof (Value) - 1)));
+
+ /* Mask inputs to the correct size. */
+ Mask = (((~0UL) - (1UL << (0)) + 1) & (~0UL >> (64 - 1 - ((sizeof (UINT16) * 8) - 1))));
+ LocalCompareValue = ((UINT64)CompareValue) & Mask;
+ LocalExchangeValue = ((UINT64)ExchangeValue) & Mask;
+
+ /*
+ * Calculate a shift & mask that correspond to the value we wish to
+ * compare & exchange within the naturally aligned 4 byte integer
+ * that includes it.
+ */
+ Shift = (UINT64)Value & 0x3;
+ Shift *= 8; /* BITS_PER_BYTE */
+ LocalCompareValue <<= Shift;
+ LocalExchangeValue <<= Shift;
+ Mask <<= Shift;
+
+ /*
+ * Calculate a pointer to the naturally aligned 4 byte integer that
+ * includes our byte of interest, and load its value.
+ */
+ Ptr32 = (UINT32 *)((UINT64)Value & ~0x3);
+
+ RetValue = AsmInternalSyncCompareExchange16 (
+ Ptr32,
+ Mask,
+ LocalCompareValue,
+ LocalExchangeValue
+ );
+
+ return (RetValue & Mask) >> Shift;
+}
+
+/**
+ Performs an atomic compare exchange operation on a 32-bit
+ unsigned integer.
+
+ Performs an atomic compare exchange operation on the 32-bit
+ unsigned integer specified by Value. If Value is equal to
+ CompareValue, then Value is set to ExchangeValue and
+ CompareValue is returned. If Value is not equal to
+ CompareValue, then Value is returned. The compare exchange
+ operation must be performed using MP safe mechanisms.
+
+ @param[in] Value A pointer to the 32-bit value for the
+ compare exchange operation.
+ @param[in] CompareValue 32-bit value used in compare operation.
+ @param[in] ExchangeValue 32-bit value used in exchange operation.
+
+ @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InternalSyncCompareExchange32 (
+ IN volatile UINT32 *Value,
+ IN UINT32 CompareValue,
+ IN UINT32 ExchangeValue
+ )
+{
+ UINT32 RetValue;
+
+ RetValue = AsmInternalSyncCompareExchange32 (
+ Value,
+ CompareValue,
+ ExchangeValue
+ );
+
+ return RetValue;
+}
+
+/**
+ Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+ Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+ by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
+ CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
+ The compare exchange operation must be performed using MP safe mechanisms.
+
+ @param[in] Value A pointer to the 64-bit value for the compare exchange
+ operation.
+ @param[in] CompareValue 64-bit value used in compare operation.
+ @param[in] ExchangeValue 64-bit value used in exchange operation.
+
+ @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InternalSyncCompareExchange64 (
+ IN volatile UINT64 *Value,
+ IN UINT64 CompareValue,
+ IN UINT64 ExchangeValue
+ )
+{
+ UINT64 RetValue;
+
+ RetValue = AsmInternalSyncCompareExchange64 (
+ Value,
+ CompareValue,
+ ExchangeValue
+ );
+
+ return RetValue;
+}
+
+/**
+ Performs an atomic increment of an 32-bit unsigned integer.
+
+ Performs an atomic increment of the 32-bit unsigned integer specified by
+ Value and returns the incremented value. The increment operation must be
+ performed using MP safe mechanisms. The state of the return value is not
+ guaranteed to be MP safe.
+
+ @param[in] Value A pointer to the 32-bit value to increment.
+
+ @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncIncrement (
+ IN volatile UINT32 *Value
+ )
+{
+ return AsmInternalSyncIncrement (Value);
+}
+
+/**
+ Performs an atomic decrement of an 32-bit unsigned integer.
+
+ Performs an atomic decrement of the 32-bit unsigned integer specified by
+ Value and returns the decrement value. The decrement operation must be
+ performed using MP safe mechanisms. The state of the return value is not
+ guaranteed to be MP safe.
+
+ @param[in] Value A pointer to the 32-bit value to decrement.
+
+ @return The decrement value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncDecrement (
+ IN volatile UINT32 *Value
+ )
+{
+ return AsmInternalSyncDecrement (Value);
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* Re: [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code.
2022-09-27 11:13 ` [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code Chao Li
@ 2022-09-27 11:27 ` Chao Li
2022-09-30 10:09 ` Chao Li
2022-09-30 15:08 ` Michael D Kinney
1 sibling, 1 reply; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:27 UTC (permalink / raw)
To: Michael D Kinney
Cc: Liming Gao, Zhiguang Liu, Baoqi Zhang, devel@edk2.groups.io
[-- Attachment #1: Type: text/plain, Size: 11729 bytes --]
Hi Mike,
I have converted the inline assembly code to ASM code, please review this patch again, thanks!
Thanks,
Chao
--------
On 9月 27 2022, at 7:13 晚上, Chao Li <lichao@loongson.cn> wrote:
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
>
> Support LoongArch cache related functions.
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
>
> Signed-off-by: Chao Li <lichao@loongson.cn>
> Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
> ---
> .../BaseSynchronizationLib.inf | 6 +
> .../LoongArch64/AsmSynchronization.S | 122 +++++++++
> .../LoongArch64/Synchronization.c | 233 ++++++++++++++++++
> 3 files changed, 361 insertions(+)
> create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
>
> diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> index 02ba12961a..dd66ec1d03 100755
> --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> @@ -4,6 +4,7 @@
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
> #
> # SPDX-License-Identifier: BSD-2-Clause-Patent
> #
> @@ -82,6 +83,11 @@
> Synchronization.c
>
> RiscV64/Synchronization.S
>
>
> +[Sources.LOONGARCH64]
> + Synchronization.c
> + LoongArch64/Synchronization.c | GCC
> + LoongArch64/AsmSynchronization.S | GCC
> +
> [Packages]
> MdePkg/MdePkg.dec
>
>
> diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> new file mode 100644
> index 0000000000..3f1b06172d
> --- /dev/null
> +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> @@ -0,0 +1,122 @@
> +#------------------------------------------------------------------------------
> +#
> +# LoongArch synchronization ASM functions.
> +#
> +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#------------------------------------------------------------------------------
> +
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange16)
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange32)
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange64)
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncIncrement)
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncDecrement)
> +
> +/**
> +UINT32
> +EFIAPI
> +AsmInternalSyncCompareExchange16 (
> + IN volatile UINT32 *Ptr32,
> + IN UINT64 Mask,
> + IN UINT64 LocalCompareValue,
> + IN UINT64 LocalExchangeValue
> + )
> +**/
> +ASM_PFX(AsmInternalSyncCompareExchange16):
> +1:
> + ll.w $t0, $a0, 0x0
> + and $t1, $t0, $a1
> + bne $t1, $a2, 2f
> + andn $t1, $t0, $a1
> + or $t1, $t1, $a3
> + sc.w $t1, $a0, 0x0
> + beqz $t1, 1b
> + b 3f
> +2:
> + dbar 0
> +3:
> + move $a0, $t0
> + jirl $zero, $ra, 0
> +
> +/**
> +UINT32
> +EFIAPI
> +AsmInternalSyncCompareExchange32 (
> + IN volatile UINT32 *Value,
> + IN UINT64 CompareValue,
> + IN UINT64 ExchangeValue
> + )
> +**/
> +ASM_PFX(AsmInternalSyncCompareExchange32):
> +1:
> + ll.w $t0, $a0, 0x0
> + bne $t0, $a1, 2f
> + move $t0, $a2
> + sc.w $t0, $a0, 0x0
> + beqz $t0, 1b
> + b 3f
> +2:
> + dbar 0
> +3:
> + move $a0, $t0
> + jirl $zero, $ra, 0
> +
> +/**
> +UINT64
> +EFIAPI
> +AsmInternalSyncCompareExchange64 (
> + IN volatile UINT64 *Value,
> + IN UINT64 CompareValue,
> + IN UINT64 ExchangeValue
> + )
> +**/
> +ASM_PFX(AsmInternalSyncCompareExchange64):
> +1:
> + ll.d $t0, $a0, 0x0
> + bne $t0, $a1, 2f
> + move $t0, $a2
> + sc.d $t0, $a0, 0x0
> + beqz $t0, 1b
> + b 3f
> +2:
> + dbar 0
> +3:
> + move $a0, $t0
> + jirl $zero, $ra, 0
> +
> +/**
> +UINT32
> +EFIAPI
> +AsmInternalSyncIncrement (
> + IN volatile UINT32 *Value
> + )
> +**/
> +ASM_PFX(AsmInternalSyncIncrement):
> + move $t0, $a0
> + dbar 0
> + ld.w $t1, $t0, 0x0
> + li.w $t2, 1
> + amadd.w $t1, $t2, $t0
> +
> + ld.w $a0, $t0, 0x0
> + jirl $zero, $ra, 0
> +
> +/**
> +UINT32
> +EFIAPI
> +AsmInternalSyncDecrement (
> + IN volatile UINT32 *Value
> + )
> +**/
> +ASM_PFX(AsmInternalSyncDecrement):
> + move $t0, $a0
> + dbar 0
> + ld.w $t1, $t0, 0x0
> + li.w $t2, -1
> + amadd.w $t1, $t2, $t0
> +
> + ld.w $a0, $t0, 0x0
> + jirl $zero, $ra, 0
> +.end
> diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
> new file mode 100644
> index 0000000000..d696c8ce10
> --- /dev/null
> +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
> @@ -0,0 +1,233 @@
> +/** @file
>
> + LoongArch synchronization functions.
> +
> + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
> +
> + SPDX-License-Identifier: BSD-2-Clause-Patent
> +
> +**/
> +
> +#include <Library/DebugLib.h>
> +
> +UINT32
> +EFIAPI
> +AsmInternalSyncCompareExchange16 (
> + IN volatile UINT32 *,
> + IN UINT64,
> + IN UINT64,
> + IN UINT64
> + );
> +
> +UINT32
> +EFIAPI
> +AsmInternalSyncCompareExchange32 (
> + IN volatile UINT32 *,
> + IN UINT64,
> + IN UINT64
> + );
> +
> +UINT64
> +EFIAPI
> +AsmInternalSyncCompareExchange64 (
> + IN volatile UINT64 *,
> + IN UINT64,
> + IN UINT64
> + );
> +
> +UINT32
> +EFIAPI
> +AsmInternalSyncIncrement (
> + IN volatile UINT32 *
> + );
> +
> +UINT32
> +EFIAPI
> +AsmInternalSyncDecrement (
> + IN volatile UINT32 *
> + );
> +
> +/**
> + Performs an atomic compare exchange operation on a 16-bit
> + unsigned integer.
> +
> + Performs an atomic compare exchange operation on the 16-bit
> + unsigned integer specified by Value. If Value is equal to
> + CompareValue, then Value is set to ExchangeValue and
> + CompareValue is returned. If Value is not equal to
> + CompareValue, then Value is returned. The compare exchange
> + operation must be performed using MP safe mechanisms.
> +
> + @param[in] Value A pointer to the 16-bit value for the
> + compare exchange operation.
> + @param[in] CompareValue 16-bit value used in compare operation.
> + @param[in] ExchangeValue 16-bit value used in exchange operation.
> +
> + @return The original *Value before exchange.
> +
> +**/
> +UINT16
> +EFIAPI
> +InternalSyncCompareExchange16 (
> + IN volatile UINT16 *Value,
> + IN UINT16 CompareValue,
> + IN UINT16 ExchangeValue
> + )
> +{
> + UINT32 RetValue;
> + UINT32 Shift;
> + UINT64 Mask;
> + UINT64 LocalCompareValue;
> + UINT64 LocalExchangeValue;
> + volatile UINT32 *Ptr32;
> +
> + /* Check that ptr is naturally aligned */
> + ASSERT (!((UINT64)Value & (sizeof (Value) - 1)));
> +
> + /* Mask inputs to the correct size. */
> + Mask = (((~0UL) - (1UL << (0)) + 1) & (~0UL >> (64 - 1 - ((sizeof (UINT16) * 8) - 1))));
> + LocalCompareValue = ((UINT64)CompareValue) & Mask;
> + LocalExchangeValue = ((UINT64)ExchangeValue) & Mask;
> +
> + /*
> + * Calculate a shift & mask that correspond to the value we wish to
> + * compare & exchange within the naturally aligned 4 byte integer
> + * that includes it.
> + */
> + Shift = (UINT64)Value & 0x3;
> + Shift *= 8; /* BITS_PER_BYTE */
> + LocalCompareValue <<= Shift;
> + LocalExchangeValue <<= Shift;
> + Mask <<= Shift;
> +
> + /*
> + * Calculate a pointer to the naturally aligned 4 byte integer that
> + * includes our byte of interest, and load its value.
> + */
> + Ptr32 = (UINT32 *)((UINT64)Value & ~0x3);
> +
> + RetValue = AsmInternalSyncCompareExchange16 (
> + Ptr32,
> + Mask,
> + LocalCompareValue,
> + LocalExchangeValue
> + );
> +
> + return (RetValue & Mask) >> Shift;
> +}
> +
> +/**
> + Performs an atomic compare exchange operation on a 32-bit
> + unsigned integer.
> +
> + Performs an atomic compare exchange operation on the 32-bit
> + unsigned integer specified by Value. If Value is equal to
> + CompareValue, then Value is set to ExchangeValue and
> + CompareValue is returned. If Value is not equal to
> + CompareValue, then Value is returned. The compare exchange
> + operation must be performed using MP safe mechanisms.
> +
> + @param[in] Value A pointer to the 32-bit value for the
> + compare exchange operation.
> + @param[in] CompareValue 32-bit value used in compare operation.
> + @param[in] ExchangeValue 32-bit value used in exchange operation.
> +
> + @return The original *Value before exchange.
> +
> +**/
> +UINT32
> +EFIAPI
> +InternalSyncCompareExchange32 (
> + IN volatile UINT32 *Value,
> + IN UINT32 CompareValue,
> + IN UINT32 ExchangeValue
> + )
> +{
> + UINT32 RetValue;
> +
> + RetValue = AsmInternalSyncCompareExchange32 (
> + Value,
> + CompareValue,
> + ExchangeValue
> + );
> +
> + return RetValue;
> +}
> +
> +/**
> + Performs an atomic compare exchange operation on a 64-bit unsigned integer.
> +
> + Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
> + by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
> + CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
> + The compare exchange operation must be performed using MP safe mechanisms.
> +
> + @param[in] Value A pointer to the 64-bit value for the compare exchange
> + operation.
> + @param[in] CompareValue 64-bit value used in compare operation.
> + @param[in] ExchangeValue 64-bit value used in exchange operation.
> +
> + @return The original *Value before exchange.
> +
> +**/
> +UINT64
> +EFIAPI
> +InternalSyncCompareExchange64 (
> + IN volatile UINT64 *Value,
> + IN UINT64 CompareValue,
> + IN UINT64 ExchangeValue
> + )
> +{
> + UINT64 RetValue;
> +
> + RetValue = AsmInternalSyncCompareExchange64 (
> + Value,
> + CompareValue,
> + ExchangeValue
> + );
> +
> + return RetValue;
> +}
> +
> +/**
> + Performs an atomic increment of an 32-bit unsigned integer.
> +
> + Performs an atomic increment of the 32-bit unsigned integer specified by
> + Value and returns the incremented value. The increment operation must be
> + performed using MP safe mechanisms. The state of the return value is not
> + guaranteed to be MP safe.
> +
> + @param[in] Value A pointer to the 32-bit value to increment.
> +
> + @return The incremented value.
> +
> +**/
> +UINT32
> +EFIAPI
> +InternalSyncIncrement (
> + IN volatile UINT32 *Value
> + )
> +{
> + return AsmInternalSyncIncrement (Value);
> +}
> +
> +/**
> + Performs an atomic decrement of an 32-bit unsigned integer.
> +
> + Performs an atomic decrement of the 32-bit unsigned integer specified by
> + Value and returns the decrement value. The decrement operation must be
> + performed using MP safe mechanisms. The state of the return value is not
> + guaranteed to be MP safe.
> +
> + @param[in] Value A pointer to the 32-bit value to decrement.
> +
> + @return The decrement value.
> +
> +**/
> +UINT32
> +EFIAPI
> +InternalSyncDecrement (
> + IN volatile UINT32 *Value
> + )
> +{
> + return AsmInternalSyncDecrement (Value);
> +}
> --
> 2.27.0
>
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^ permalink raw reply [flat|nested] 38+ messages in thread* Re: [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code.
2022-09-27 11:27 ` Chao Li
@ 2022-09-30 10:09 ` Chao Li
0 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-30 10:09 UTC (permalink / raw)
To: Michael D Kinney
Cc: Liming Gao, Zhiguang Liu, Baoqi Zhang,
" devel@edk2.groups.io "
[-- Attachment #1: Type: text/plain, Size: 12853 bytes --]
Hi Mike,
I'm guessing you're a little busy, or forgot about this issue. :)
I have converted the inline assembly code to ASM code, please review this patch again, thanks!
Thanks,
Chao
--------
On 9月 27 2022, at 7:27 晚上, chao li <lichao@loongson.cn> wrote:
> Hi Mike,
> I have converted the inline assembly code to ASM code, please review this patch again, thanks!
>
>
> Thanks,
> Chao
> --------
>
> On 9月 27 2022, at 7:13 晚上, Chao Li <lichao@loongson.cn> wrote:
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
> >
> > Support LoongArch cache related functions.
> > Cc: Michael D Kinney <michael.d.kinney@intel.com>
> > Cc: Liming Gao <gaoliming@byosoft.com.cn>
> > Cc: Zhiguang Liu <zhiguang.liu@intel.com>
> >
> > Signed-off-by: Chao Li <lichao@loongson.cn>
> > Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
> > ---
> > .../BaseSynchronizationLib.inf | 6 +
> > .../LoongArch64/AsmSynchronization.S | 122 +++++++++
> > .../LoongArch64/Synchronization.c | 233 ++++++++++++++++++
> > 3 files changed, 361 insertions(+)
> > create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> > create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
> >
> > diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> > index 02ba12961a..dd66ec1d03 100755
> > --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> > +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> > @@ -4,6 +4,7 @@
> > # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
> >
> > # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> > # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> > +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
> > #
> > # SPDX-License-Identifier: BSD-2-Clause-Patent
> > #
> > @@ -82,6 +83,11 @@
> > Synchronization.c
> >
> > RiscV64/Synchronization.S
> >
> >
> > +[Sources.LOONGARCH64]
> > + Synchronization.c
> > + LoongArch64/Synchronization.c | GCC
> > + LoongArch64/AsmSynchronization.S | GCC
> > +
> > [Packages]
> > MdePkg/MdePkg.dec
> >
> >
> > diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> > new file mode 100644
> > index 0000000000..3f1b06172d
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> > @@ -0,0 +1,122 @@
> > +#------------------------------------------------------------------------------
> > +#
> > +# LoongArch synchronization ASM functions.
> > +#
> > +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
> > +#
> > +# SPDX-License-Identifier: BSD-2-Clause-Patent
> > +#
> > +#------------------------------------------------------------------------------
> > +
> > +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange16)
> > +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange32)
> > +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange64)
> > +ASM_GLOBAL ASM_PFX(AsmInternalSyncIncrement)
> > +ASM_GLOBAL ASM_PFX(AsmInternalSyncDecrement)
> > +
> > +/**
> > +UINT32
> > +EFIAPI
> > +AsmInternalSyncCompareExchange16 (
> > + IN volatile UINT32 *Ptr32,
> > + IN UINT64 Mask,
> > + IN UINT64 LocalCompareValue,
> > + IN UINT64 LocalExchangeValue
> > + )
> > +**/
> > +ASM_PFX(AsmInternalSyncCompareExchange16):
> > +1:
> > + ll.w $t0, $a0, 0x0
> > + and $t1, $t0, $a1
> > + bne $t1, $a2, 2f
> > + andn $t1, $t0, $a1
> > + or $t1, $t1, $a3
> > + sc.w $t1, $a0, 0x0
> > + beqz $t1, 1b
> > + b 3f
> > +2:
> > + dbar 0
> > +3:
> > + move $a0, $t0
> > + jirl $zero, $ra, 0
> > +
> > +/**
> > +UINT32
> > +EFIAPI
> > +AsmInternalSyncCompareExchange32 (
> > + IN volatile UINT32 *Value,
> > + IN UINT64 CompareValue,
> > + IN UINT64 ExchangeValue
> > + )
> > +**/
> > +ASM_PFX(AsmInternalSyncCompareExchange32):
> > +1:
> > + ll.w $t0, $a0, 0x0
> > + bne $t0, $a1, 2f
> > + move $t0, $a2
> > + sc.w $t0, $a0, 0x0
> > + beqz $t0, 1b
> > + b 3f
> > +2:
> > + dbar 0
> > +3:
> > + move $a0, $t0
> > + jirl $zero, $ra, 0
> > +
> > +/**
> > +UINT64
> > +EFIAPI
> > +AsmInternalSyncCompareExchange64 (
> > + IN volatile UINT64 *Value,
> > + IN UINT64 CompareValue,
> > + IN UINT64 ExchangeValue
> > + )
> > +**/
> > +ASM_PFX(AsmInternalSyncCompareExchange64):
> > +1:
> > + ll.d $t0, $a0, 0x0
> > + bne $t0, $a1, 2f
> > + move $t0, $a2
> > + sc.d $t0, $a0, 0x0
> > + beqz $t0, 1b
> > + b 3f
> > +2:
> > + dbar 0
> > +3:
> > + move $a0, $t0
> > + jirl $zero, $ra, 0
> > +
> > +/**
> > +UINT32
> > +EFIAPI
> > +AsmInternalSyncIncrement (
> > + IN volatile UINT32 *Value
> > + )
> > +**/
> > +ASM_PFX(AsmInternalSyncIncrement):
> > + move $t0, $a0
> > + dbar 0
> > + ld.w $t1, $t0, 0x0
> > + li.w $t2, 1
> > + amadd.w $t1, $t2, $t0
> > +
> > + ld.w $a0, $t0, 0x0
> > + jirl $zero, $ra, 0
> > +
> > +/**
> > +UINT32
> > +EFIAPI
> > +AsmInternalSyncDecrement (
> > + IN volatile UINT32 *Value
> > + )
> > +**/
> > +ASM_PFX(AsmInternalSyncDecrement):
> > + move $t0, $a0
> > + dbar 0
> > + ld.w $t1, $t0, 0x0
> > + li.w $t2, -1
> > + amadd.w $t1, $t2, $t0
> > +
> > + ld.w $a0, $t0, 0x0
> > + jirl $zero, $ra, 0
> > +.end
> > diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
> > new file mode 100644
> > index 0000000000..d696c8ce10
> > --- /dev/null
> > +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
> > @@ -0,0 +1,233 @@
> > +/** @file
> >
> > + LoongArch synchronization functions.
> > +
> > + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
> > +
> > + SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +
> > +#include <Library/DebugLib.h>
> > +
> > +UINT32
> > +EFIAPI
> > +AsmInternalSyncCompareExchange16 (
> > + IN volatile UINT32 *,
> > + IN UINT64,
> > + IN UINT64,
> > + IN UINT64
> > + );
> > +
> > +UINT32
> > +EFIAPI
> > +AsmInternalSyncCompareExchange32 (
> > + IN volatile UINT32 *,
> > + IN UINT64,
> > + IN UINT64
> > + );
> > +
> > +UINT64
> > +EFIAPI
> > +AsmInternalSyncCompareExchange64 (
> > + IN volatile UINT64 *,
> > + IN UINT64,
> > + IN UINT64
> > + );
> > +
> > +UINT32
> > +EFIAPI
> > +AsmInternalSyncIncrement (
> > + IN volatile UINT32 *
> > + );
> > +
> > +UINT32
> > +EFIAPI
> > +AsmInternalSyncDecrement (
> > + IN volatile UINT32 *
> > + );
> > +
> > +/**
> > + Performs an atomic compare exchange operation on a 16-bit
> > + unsigned integer.
> > +
> > + Performs an atomic compare exchange operation on the 16-bit
> > + unsigned integer specified by Value. If Value is equal to
> > + CompareValue, then Value is set to ExchangeValue and
> > + CompareValue is returned. If Value is not equal to
> > + CompareValue, then Value is returned. The compare exchange
> > + operation must be performed using MP safe mechanisms.
> > +
> > + @param[in] Value A pointer to the 16-bit value for the
> > + compare exchange operation.
> > + @param[in] CompareValue 16-bit value used in compare operation.
> > + @param[in] ExchangeValue 16-bit value used in exchange operation.
> > +
> > + @return The original *Value before exchange.
> > +
> > +**/
> > +UINT16
> > +EFIAPI
> > +InternalSyncCompareExchange16 (
> > + IN volatile UINT16 *Value,
> > + IN UINT16 CompareValue,
> > + IN UINT16 ExchangeValue
> > + )
> > +{
> > + UINT32 RetValue;
> > + UINT32 Shift;
> > + UINT64 Mask;
> > + UINT64 LocalCompareValue;
> > + UINT64 LocalExchangeValue;
> > + volatile UINT32 *Ptr32;
> > +
> > + /* Check that ptr is naturally aligned */
> > + ASSERT (!((UINT64)Value & (sizeof (Value) - 1)));
> > +
> > + /* Mask inputs to the correct size. */
> > + Mask = (((~0UL) - (1UL << (0)) + 1) & (~0UL >> (64 - 1 - ((sizeof (UINT16) * 8) - 1))));
> > + LocalCompareValue = ((UINT64)CompareValue) & Mask;
> > + LocalExchangeValue = ((UINT64)ExchangeValue) & Mask;
> > +
> > + /*
> > + * Calculate a shift & mask that correspond to the value we wish to
> > + * compare & exchange within the naturally aligned 4 byte integer
> > + * that includes it.
> > + */
> > + Shift = (UINT64)Value & 0x3;
> > + Shift *= 8; /* BITS_PER_BYTE */
> > + LocalCompareValue <<= Shift;
> > + LocalExchangeValue <<= Shift;
> > + Mask <<= Shift;
> > +
> > + /*
> > + * Calculate a pointer to the naturally aligned 4 byte integer that
> > + * includes our byte of interest, and load its value.
> > + */
> > + Ptr32 = (UINT32 *)((UINT64)Value & ~0x3);
> > +
> > + RetValue = AsmInternalSyncCompareExchange16 (
> > + Ptr32,
> > + Mask,
> > + LocalCompareValue,
> > + LocalExchangeValue
> > + );
> > +
> > + return (RetValue & Mask) >> Shift;
> > +}
> > +
> > +/**
> > + Performs an atomic compare exchange operation on a 32-bit
> > + unsigned integer.
> > +
> > + Performs an atomic compare exchange operation on the 32-bit
> > + unsigned integer specified by Value. If Value is equal to
> > + CompareValue, then Value is set to ExchangeValue and
> > + CompareValue is returned. If Value is not equal to
> > + CompareValue, then Value is returned. The compare exchange
> > + operation must be performed using MP safe mechanisms.
> > +
> > + @param[in] Value A pointer to the 32-bit value for the
> > + compare exchange operation.
> > + @param[in] CompareValue 32-bit value used in compare operation.
> > + @param[in] ExchangeValue 32-bit value used in exchange operation.
> > +
> > + @return The original *Value before exchange.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +InternalSyncCompareExchange32 (
> > + IN volatile UINT32 *Value,
> > + IN UINT32 CompareValue,
> > + IN UINT32 ExchangeValue
> > + )
> > +{
> > + UINT32 RetValue;
> > +
> > + RetValue = AsmInternalSyncCompareExchange32 (
> > + Value,
> > + CompareValue,
> > + ExchangeValue
> > + );
> > +
> > + return RetValue;
> > +}
> > +
> > +/**
> > + Performs an atomic compare exchange operation on a 64-bit unsigned integer.
> > +
> > + Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
> > + by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
> > + CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
> > + The compare exchange operation must be performed using MP safe mechanisms.
> > +
> > + @param[in] Value A pointer to the 64-bit value for the compare exchange
> > + operation.
> > + @param[in] CompareValue 64-bit value used in compare operation.
> > + @param[in] ExchangeValue 64-bit value used in exchange operation.
> > +
> > + @return The original *Value before exchange.
> > +
> > +**/
> > +UINT64
> > +EFIAPI
> > +InternalSyncCompareExchange64 (
> > + IN volatile UINT64 *Value,
> > + IN UINT64 CompareValue,
> > + IN UINT64 ExchangeValue
> > + )
> > +{
> > + UINT64 RetValue;
> > +
> > + RetValue = AsmInternalSyncCompareExchange64 (
> > + Value,
> > + CompareValue,
> > + ExchangeValue
> > + );
> > +
> > + return RetValue;
> > +}
> > +
> > +/**
> > + Performs an atomic increment of an 32-bit unsigned integer.
> > +
> > + Performs an atomic increment of the 32-bit unsigned integer specified by
> > + Value and returns the incremented value. The increment operation must be
> > + performed using MP safe mechanisms. The state of the return value is not
> > + guaranteed to be MP safe.
> > +
> > + @param[in] Value A pointer to the 32-bit value to increment.
> > +
> > + @return The incremented value.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +InternalSyncIncrement (
> > + IN volatile UINT32 *Value
> > + )
> > +{
> > + return AsmInternalSyncIncrement (Value);
> > +}
> > +
> > +/**
> > + Performs an atomic decrement of an 32-bit unsigned integer.
> > +
> > + Performs an atomic decrement of the 32-bit unsigned integer specified by
> > + Value and returns the decrement value. The decrement operation must be
> > + performed using MP safe mechanisms. The state of the return value is not
> > + guaranteed to be MP safe.
> > +
> > + @param[in] Value A pointer to the 32-bit value to decrement.
> > +
> > + @return The decrement value.
> > +
> > +**/
> > +UINT32
> > +EFIAPI
> > +InternalSyncDecrement (
> > + IN volatile UINT32 *Value
> > + )
> > +{
> > + return AsmInternalSyncDecrement (Value);
> > +}
> > --
> > 2.27.0
> >
>
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^ permalink raw reply [flat|nested] 38+ messages in thread
* Re: [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code.
2022-09-27 11:13 ` [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code Chao Li
2022-09-27 11:27 ` Chao Li
@ 2022-09-30 15:08 ` Michael D Kinney
1 sibling, 0 replies; 38+ messages in thread
From: Michael D Kinney @ 2022-09-30 15:08 UTC (permalink / raw)
To: Chao Li, devel@edk2.groups.io, Kinney, Michael D
Cc: Gao, Liming, Liu, Zhiguang, Baoqi Zhang
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
> -----Original Message-----
> From: Chao Li <lichao@loongson.cn>
> Sent: Tuesday, September 27, 2022 4:14 AM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D <michael.d.kinney@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>; Liu, Zhiguang
> <zhiguang.liu@intel.com>; Baoqi Zhang <zhangbaoqi@loongson.cn>
> Subject: [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code.
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
>
> Support LoongArch cache related functions.
>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Zhiguang Liu <zhiguang.liu@intel.com>
>
> Signed-off-by: Chao Li <lichao@loongson.cn>
> Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
> ---
> .../BaseSynchronizationLib.inf | 6 +
> .../LoongArch64/AsmSynchronization.S | 122 +++++++++
> .../LoongArch64/Synchronization.c | 233 ++++++++++++++++++
> 3 files changed, 361 insertions(+)
> create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
>
> diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> index 02ba12961a..dd66ec1d03 100755
> --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
> @@ -4,6 +4,7 @@
> # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
>
> # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
>
> # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>
> +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
>
> #
>
> # SPDX-License-Identifier: BSD-2-Clause-Patent
>
> #
>
> @@ -82,6 +83,11 @@
> Synchronization.c
>
> RiscV64/Synchronization.S
>
>
>
> +[Sources.LOONGARCH64]
>
> + Synchronization.c
>
> + LoongArch64/Synchronization.c | GCC
>
> + LoongArch64/AsmSynchronization.S | GCC
>
> +
>
> [Packages]
>
> MdePkg/MdePkg.dec
>
>
>
> diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> new file mode 100644
> index 0000000000..3f1b06172d
> --- /dev/null
> +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S
> @@ -0,0 +1,122 @@
> +#------------------------------------------------------------------------------
> +#
> +# LoongArch synchronization ASM functions.
> +#
> +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
> +#
> +# SPDX-License-Identifier: BSD-2-Clause-Patent
> +#
> +#------------------------------------------------------------------------------
> +
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange16)
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange32)
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange64)
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncIncrement)
> +ASM_GLOBAL ASM_PFX(AsmInternalSyncDecrement)
> +
> +/**
> +UINT32
> +EFIAPI
> +AsmInternalSyncCompareExchange16 (
> + IN volatile UINT32 *Ptr32,
> + IN UINT64 Mask,
> + IN UINT64 LocalCompareValue,
> + IN UINT64 LocalExchangeValue
> + )
> +**/
> +ASM_PFX(AsmInternalSyncCompareExchange16):
> +1:
> + ll.w $t0, $a0, 0x0
> + and $t1, $t0, $a1
> + bne $t1, $a2, 2f
> + andn $t1, $t0, $a1
> + or $t1, $t1, $a3
> + sc.w $t1, $a0, 0x0
> + beqz $t1, 1b
> + b 3f
> +2:
> + dbar 0
> +3:
> + move $a0, $t0
> + jirl $zero, $ra, 0
> +
> +/**
> +UINT32
> +EFIAPI
> +AsmInternalSyncCompareExchange32 (
> + IN volatile UINT32 *Value,
> + IN UINT64 CompareValue,
> + IN UINT64 ExchangeValue
> + )
> +**/
> +ASM_PFX(AsmInternalSyncCompareExchange32):
> +1:
> + ll.w $t0, $a0, 0x0
> + bne $t0, $a1, 2f
> + move $t0, $a2
> + sc.w $t0, $a0, 0x0
> + beqz $t0, 1b
> + b 3f
> +2:
> + dbar 0
> +3:
> + move $a0, $t0
> + jirl $zero, $ra, 0
> +
> +/**
> +UINT64
> +EFIAPI
> +AsmInternalSyncCompareExchange64 (
> + IN volatile UINT64 *Value,
> + IN UINT64 CompareValue,
> + IN UINT64 ExchangeValue
> + )
> +**/
> +ASM_PFX(AsmInternalSyncCompareExchange64):
> +1:
> + ll.d $t0, $a0, 0x0
> + bne $t0, $a1, 2f
> + move $t0, $a2
> + sc.d $t0, $a0, 0x0
> + beqz $t0, 1b
> + b 3f
> +2:
> + dbar 0
> +3:
> + move $a0, $t0
> + jirl $zero, $ra, 0
> +
> +/**
> +UINT32
> +EFIAPI
> +AsmInternalSyncIncrement (
> + IN volatile UINT32 *Value
> + )
> +**/
> +ASM_PFX(AsmInternalSyncIncrement):
> + move $t0, $a0
> + dbar 0
> + ld.w $t1, $t0, 0x0
> + li.w $t2, 1
> + amadd.w $t1, $t2, $t0
> +
> + ld.w $a0, $t0, 0x0
> + jirl $zero, $ra, 0
> +
> +/**
> +UINT32
> +EFIAPI
> +AsmInternalSyncDecrement (
> + IN volatile UINT32 *Value
> + )
> +**/
> +ASM_PFX(AsmInternalSyncDecrement):
> + move $t0, $a0
> + dbar 0
> + ld.w $t1, $t0, 0x0
> + li.w $t2, -1
> + amadd.w $t1, $t2, $t0
> +
> + ld.w $a0, $t0, 0x0
> + jirl $zero, $ra, 0
> +.end
> diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
> b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
> new file mode 100644
> index 0000000000..d696c8ce10
> --- /dev/null
> +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c
> @@ -0,0 +1,233 @@
> +/** @file
>
> + LoongArch synchronization functions.
>
> +
>
> + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
>
> +
>
> + SPDX-License-Identifier: BSD-2-Clause-Patent
>
> +
>
> +**/
>
> +
>
> +#include <Library/DebugLib.h>
>
> +
>
> +UINT32
>
> +EFIAPI
>
> +AsmInternalSyncCompareExchange16 (
>
> + IN volatile UINT32 *,
>
> + IN UINT64,
>
> + IN UINT64,
>
> + IN UINT64
>
> + );
>
> +
>
> +UINT32
>
> +EFIAPI
>
> +AsmInternalSyncCompareExchange32 (
>
> + IN volatile UINT32 *,
>
> + IN UINT64,
>
> + IN UINT64
>
> + );
>
> +
>
> +UINT64
>
> +EFIAPI
>
> +AsmInternalSyncCompareExchange64 (
>
> + IN volatile UINT64 *,
>
> + IN UINT64,
>
> + IN UINT64
>
> + );
>
> +
>
> +UINT32
>
> +EFIAPI
>
> +AsmInternalSyncIncrement (
>
> + IN volatile UINT32 *
>
> + );
>
> +
>
> +UINT32
>
> +EFIAPI
>
> +AsmInternalSyncDecrement (
>
> + IN volatile UINT32 *
>
> + );
>
> +
>
> +/**
>
> + Performs an atomic compare exchange operation on a 16-bit
>
> + unsigned integer.
>
> +
>
> + Performs an atomic compare exchange operation on the 16-bit
>
> + unsigned integer specified by Value. If Value is equal to
>
> + CompareValue, then Value is set to ExchangeValue and
>
> + CompareValue is returned. If Value is not equal to
>
> + CompareValue, then Value is returned. The compare exchange
>
> + operation must be performed using MP safe mechanisms.
>
> +
>
> + @param[in] Value A pointer to the 16-bit value for the
>
> + compare exchange operation.
>
> + @param[in] CompareValue 16-bit value used in compare operation.
>
> + @param[in] ExchangeValue 16-bit value used in exchange operation.
>
> +
>
> + @return The original *Value before exchange.
>
> +
>
> +**/
>
> +UINT16
>
> +EFIAPI
>
> +InternalSyncCompareExchange16 (
>
> + IN volatile UINT16 *Value,
>
> + IN UINT16 CompareValue,
>
> + IN UINT16 ExchangeValue
>
> + )
>
> +{
>
> + UINT32 RetValue;
>
> + UINT32 Shift;
>
> + UINT64 Mask;
>
> + UINT64 LocalCompareValue;
>
> + UINT64 LocalExchangeValue;
>
> + volatile UINT32 *Ptr32;
>
> +
>
> + /* Check that ptr is naturally aligned */
>
> + ASSERT (!((UINT64)Value & (sizeof (Value) - 1)));
>
> +
>
> + /* Mask inputs to the correct size. */
>
> + Mask = (((~0UL) - (1UL << (0)) + 1) & (~0UL >> (64 - 1 - ((sizeof (UINT16) * 8) - 1))));
>
> + LocalCompareValue = ((UINT64)CompareValue) & Mask;
>
> + LocalExchangeValue = ((UINT64)ExchangeValue) & Mask;
>
> +
>
> + /*
>
> + * Calculate a shift & mask that correspond to the value we wish to
>
> + * compare & exchange within the naturally aligned 4 byte integer
>
> + * that includes it.
>
> + */
>
> + Shift = (UINT64)Value & 0x3;
>
> + Shift *= 8; /* BITS_PER_BYTE */
>
> + LocalCompareValue <<= Shift;
>
> + LocalExchangeValue <<= Shift;
>
> + Mask <<= Shift;
>
> +
>
> + /*
>
> + * Calculate a pointer to the naturally aligned 4 byte integer that
>
> + * includes our byte of interest, and load its value.
>
> + */
>
> + Ptr32 = (UINT32 *)((UINT64)Value & ~0x3);
>
> +
>
> + RetValue = AsmInternalSyncCompareExchange16 (
>
> + Ptr32,
>
> + Mask,
>
> + LocalCompareValue,
>
> + LocalExchangeValue
>
> + );
>
> +
>
> + return (RetValue & Mask) >> Shift;
>
> +}
>
> +
>
> +/**
>
> + Performs an atomic compare exchange operation on a 32-bit
>
> + unsigned integer.
>
> +
>
> + Performs an atomic compare exchange operation on the 32-bit
>
> + unsigned integer specified by Value. If Value is equal to
>
> + CompareValue, then Value is set to ExchangeValue and
>
> + CompareValue is returned. If Value is not equal to
>
> + CompareValue, then Value is returned. The compare exchange
>
> + operation must be performed using MP safe mechanisms.
>
> +
>
> + @param[in] Value A pointer to the 32-bit value for the
>
> + compare exchange operation.
>
> + @param[in] CompareValue 32-bit value used in compare operation.
>
> + @param[in] ExchangeValue 32-bit value used in exchange operation.
>
> +
>
> + @return The original *Value before exchange.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +InternalSyncCompareExchange32 (
>
> + IN volatile UINT32 *Value,
>
> + IN UINT32 CompareValue,
>
> + IN UINT32 ExchangeValue
>
> + )
>
> +{
>
> + UINT32 RetValue;
>
> +
>
> + RetValue = AsmInternalSyncCompareExchange32 (
>
> + Value,
>
> + CompareValue,
>
> + ExchangeValue
>
> + );
>
> +
>
> + return RetValue;
>
> +}
>
> +
>
> +/**
>
> + Performs an atomic compare exchange operation on a 64-bit unsigned integer.
>
> +
>
> + Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
>
> + by Value. If Value is equal to CompareValue, then Value is set to ExchangeValue and
>
> + CompareValue is returned. If Value is not equal to CompareValue, then Value is returned.
>
> + The compare exchange operation must be performed using MP safe mechanisms.
>
> +
>
> + @param[in] Value A pointer to the 64-bit value for the compare exchange
>
> + operation.
>
> + @param[in] CompareValue 64-bit value used in compare operation.
>
> + @param[in] ExchangeValue 64-bit value used in exchange operation.
>
> +
>
> + @return The original *Value before exchange.
>
> +
>
> +**/
>
> +UINT64
>
> +EFIAPI
>
> +InternalSyncCompareExchange64 (
>
> + IN volatile UINT64 *Value,
>
> + IN UINT64 CompareValue,
>
> + IN UINT64 ExchangeValue
>
> + )
>
> +{
>
> + UINT64 RetValue;
>
> +
>
> + RetValue = AsmInternalSyncCompareExchange64 (
>
> + Value,
>
> + CompareValue,
>
> + ExchangeValue
>
> + );
>
> +
>
> + return RetValue;
>
> +}
>
> +
>
> +/**
>
> + Performs an atomic increment of an 32-bit unsigned integer.
>
> +
>
> + Performs an atomic increment of the 32-bit unsigned integer specified by
>
> + Value and returns the incremented value. The increment operation must be
>
> + performed using MP safe mechanisms. The state of the return value is not
>
> + guaranteed to be MP safe.
>
> +
>
> + @param[in] Value A pointer to the 32-bit value to increment.
>
> +
>
> + @return The incremented value.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +InternalSyncIncrement (
>
> + IN volatile UINT32 *Value
>
> + )
>
> +{
>
> + return AsmInternalSyncIncrement (Value);
>
> +}
>
> +
>
> +/**
>
> + Performs an atomic decrement of an 32-bit unsigned integer.
>
> +
>
> + Performs an atomic decrement of the 32-bit unsigned integer specified by
>
> + Value and returns the decrement value. The decrement operation must be
>
> + performed using MP safe mechanisms. The state of the return value is not
>
> + guaranteed to be MP safe.
>
> +
>
> + @param[in] Value A pointer to the 32-bit value to decrement.
>
> +
>
> + @return The decrement value.
>
> +
>
> +**/
>
> +UINT32
>
> +EFIAPI
>
> +InternalSyncDecrement (
>
> + IN volatile UINT32 *Value
>
> + )
>
> +{
>
> + return AsmInternalSyncDecrement (Value);
>
> +}
>
> --
> 2.27.0
^ permalink raw reply [flat|nested] 38+ messages in thread
* [PATCH v3 30/34] MdePkg/BaseSafeIntLib: Add LoongArch64 architecture for BaseSafeIntLib.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (28 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 31/34] MdeModulePkg/Logo: Add LoongArch64 architecture Chao Li
` (3 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Michael D Kinney, Liming Gao, Zhiguang Liu
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch64 architecture for BaseSafeIntLib library.
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
index 40017ec88b..9d039f2e5b 100644
--- a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
+++ b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf
@@ -4,9 +4,10 @@
# This library provides helper functions to prevent integer overflow during
# type conversion, addition, subtraction, and multiplication.
#
-# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017, Microsoft Corporation
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# All rights reserved.
@@ -25,7 +26,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
@@ -34,7 +35,7 @@
[Sources.Ia32, Sources.ARM]
SafeIntLib32.c
-[Sources.X64, Sources.AARCH64, Sources.RISCV64]
+[Sources.X64, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]
SafeIntLib64.c
[Sources.EBC]
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 31/34] MdeModulePkg/Logo: Add LoongArch64 architecture.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (29 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 30/34] MdePkg/BaseSafeIntLib: Add LoongArch64 architecture for BaseSafeIntLib Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 32/34] MdeModulePkg/CapsuleRuntimeDxe: " Chao Li
` (2 subsequent siblings)
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Zhichao Gao, Ray Ni, Michael D Kinney
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch64 architecture to the Logo.
Cc: Zhichao Gao <zhichao.gao@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
---
MdeModulePkg/Logo/Logo.inf | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf
index 70a66cae98..294482ccdc 100644
--- a/MdeModulePkg/Logo/Logo.inf
+++ b/MdeModulePkg/Logo/Logo.inf
@@ -3,6 +3,7 @@
#
# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -21,7 +22,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
#
[Binaries]
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 32/34] MdeModulePkg/CapsuleRuntimeDxe: Add LoongArch64 architecture.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (30 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 31/34] MdeModulePkg/Logo: Add LoongArch64 architecture Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 33/34] MdeModulePkg/DxeIplPeim : LoongArch DxeIPL implementation Chao Li
2022-09-27 11:13 ` [PATCH v3 34/34] NetworkPkg: Add LoongArch64 architecture Chao Li
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Liming Gao, Guomin Jiang, Michael D Kinney
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch in INF for building CapsuleRuntimeDxe LoongArch64 image.
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Sigend-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
.../Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
index 8bf5035a69..601eada170 100644
--- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
@@ -6,6 +6,7 @@
#
# Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
##
@@ -22,20 +23,20 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64 LOONGARCH64
#
[Sources]
CapsuleService.c
CapsuleService.h
-[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
+[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]
SaveLongModeContext.c
-[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64]
+[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]
CapsuleCache.c
-[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]
+[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64, Sources.LOONGARCH64]
CapsuleReset.c
[Sources.ARM, Sources.AARCH64]
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 33/34] MdeModulePkg/DxeIplPeim : LoongArch DxeIPL implementation.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (31 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 32/34] MdeModulePkg/CapsuleRuntimeDxe: " Chao Li
@ 2022-09-27 11:13 ` Chao Li
2022-09-27 11:13 ` [PATCH v3 34/34] NetworkPkg: Add LoongArch64 architecture Chao Li
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Liming Gao, Guomin Jiang, Baoqi Zhang
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Implement LoongArch DxeIPL instance.
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Guomin Jiang <guomin.jiang@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Co-authored-by: Baoqi Zhang <zhangbaoqi@loongson.cn>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
---
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 6 +-
.../Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c | 63 +++++++++++++++++++
2 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c
diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
index 19b8a4c8ae..052ea0ec1a 100644
--- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
@@ -8,6 +8,7 @@
# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -26,7 +27,7 @@
#
# The following information is for reference only and not required by the build tools.
#
-# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64
+# VALID_ARCHITECTURES = IA32 X64 EBC (EBC is for build only) AARCH64 RISCV64 LOONGARCH64
#
[Sources]
@@ -53,6 +54,9 @@
[Sources.RISCV64]
RiscV64/DxeLoadFunc.c
+[Sources.LOONGARCH64]
+ LoongArch64/DxeLoadFunc.c
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
diff --git a/MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c b/MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c
new file mode 100644
index 0000000000..95d3af19ea
--- /dev/null
+++ b/MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c
@@ -0,0 +1,63 @@
+/** @file
+ LoongArch specifc functionality for DxeLoad.
+
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "DxeIpl.h"
+
+/**
+ Transfers control to DxeCore.
+
+ This function performs a CPU architecture specific operations to execute
+ the entry point of DxeCore with the parameters of HobList.
+ It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.
+
+ @param[in] DxeCoreEntryPoint The entry point of DxeCore.
+ @param[in] HobList The start of HobList passed to DxeCore.
+
+**/
+VOID
+HandOffToDxeCore (
+ IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,
+ IN EFI_PEI_HOB_POINTERS HobList
+ )
+{
+ VOID *BaseOfStack;
+ VOID *TopOfStack;
+ EFI_STATUS Status;
+
+ //
+ // Allocate 128KB for the Stack
+ //
+ BaseOfStack = AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));
+ ASSERT (BaseOfStack != NULL);
+
+ //
+ // Compute the top of the stack we were allocated. Pre-allocate a UINTN
+ // for safety.
+ //
+ TopOfStack = (VOID *)((UINTN)BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);
+ TopOfStack = ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);
+
+ //
+ // End of PEI phase signal
+ //
+ Status = PeiServicesInstallPpi (&gEndOfPeiSignalPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update the contents of BSP stack HOB to reflect the real stack info passed to DxeCore.
+ //
+ UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack, STACK_SIZE);
+
+ SwitchStack (
+ (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,
+ HobList.Raw,
+ NULL,
+ TopOfStack
+ );
+}
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread* [PATCH v3 34/34] NetworkPkg: Add LoongArch64 architecture.
2022-09-27 11:13 [PATCH v3 00/34] Add a new architecture called LoongArch in EDK II Chao Li
` (32 preceding siblings ...)
2022-09-27 11:13 ` [PATCH v3 33/34] MdeModulePkg/DxeIplPeim : LoongArch DxeIPL implementation Chao Li
@ 2022-09-27 11:13 ` Chao Li
33 siblings, 0 replies; 38+ messages in thread
From: Chao Li @ 2022-09-27 11:13 UTC (permalink / raw)
To: devel; +Cc: Maciej Rabeda, Jiaxin Wu, Siyuan Fu, Michael D Kinney
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053
Add LoongArch64 architecture in to NetworkPkg.
Cc: Maciej Rabeda <maciej.rabeda@linux.intel.com>
Cc: Jiaxin Wu <jiaxin.wu@intel.com>
Cc: Siyuan Fu <siyuan.fu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
---
NetworkPkg/Network.dsc.inc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/NetworkPkg/Network.dsc.inc b/NetworkPkg/Network.dsc.inc
index 99fad885bf..04b515a0bb 100644
--- a/NetworkPkg/Network.dsc.inc
+++ b/NetworkPkg/Network.dsc.inc
@@ -9,6 +9,7 @@
#
# Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -38,7 +39,7 @@
!include NetworkPkg/NetworkComponents.dsc.inc
!else
-[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Components.RISCV64]
+[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Components.RISCV64, Components.LOONGARCH64]
!include NetworkPkg/NetworkComponents.dsc.inc
!endif
--
2.27.0
^ permalink raw reply related [flat|nested] 38+ messages in thread