From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from loongson.cn (loongson.cn [114.242.206.163]) by mx.groups.io with SMTP id smtpd.web08.9460.1664277256490546054 for ; Tue, 27 Sep 2022 04:14:17 -0700 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: loongson.cn, ip: 114.242.206.163, mailfrom: lichao@loongson.cn) Received: from code-server.gen (unknown [10.2.9.245]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Cxrmv02jJjirsiAA--.49762S10; Tue, 27 Sep 2022 19:14:15 +0800 (CST) From: "Chao Li" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [PATCH v3 08/34] MdePkg/Include: Add LOONGARCH related definitions EDK2 CI. Date: Tue, 27 Sep 2022 19:13:28 +0800 Message-Id: <20220927111354.4107719-9-lichao@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220927111354.4107719-1-lichao@loongson.cn> References: <20220927111354.4107719-1-lichao@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Cxrmv02jJjirsiAA--.49762S10 X-Coremail-Antispam: 1UD129KBjvJXoWxAF1fXF1UZFy5AF1xur13XFb_yoWrZFyDpr 18AFy5X397KF13uF97Ka1UC34xWr4rt3s5Xry2q3yUCF1jy3y8Kw1DWFW5KryDXr48XryF gFn3A3W0gFnxArJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: xolfxt3r6o00pqjv00gofq/1tbiAQACCGMxll4dbgALsp Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053 HTTP/PXE boot LOONGARCH64 related definitions for EDK2 CI. For the LOONGARCH values, please seeing following URL section "Processor Architecture Types": https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Chao Li Reviewed-by: Michael D Kinney --- MdePkg/Include/IndustryStandard/Dhcp.h | 45 ++++++++++++++------------ 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/Indust= ryStandard/Dhcp.h index f209f1b2eb..46ab4f8e75 100644 --- a/MdePkg/Include/IndustryStandard/Dhcp.h +++ b/MdePkg/Include/IndustryStandard/Dhcp.h @@ -4,6 +4,7 @@ =0D Copyright (c) 2016, Intel Corporation. All rights reserved.
=0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.
=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.
=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D =0D @@ -256,27 +257,31 @@ typedef enum { =0D ///=0D /// Processor Architecture Types=0D -/// These identifiers are defined by IETF:=0D -/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xm= l=0D +/// These identifiers are defined by IANA:=0D +/// https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.x= html=0D ///=0D -#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE=0D -#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE=0D -#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE=0D -#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE=0D -#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE=0D -#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE= =0D -#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE= =0D -#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for = PXE=0D -#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for = PXE=0D -#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for= PXE=0D +#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE= =0D +#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE=0D +#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE= =0D +#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE= =0D +#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE=0D +#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for P= XE=0D +#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for P= XE=0D +#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 fo= r PXE=0D +#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 fo= r PXE=0D +#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 f= or PXE=0D +#define PXE_CLIENT_ARCH_LOONGARCH32 0x0025 /// LoongArch uefi 32= for PXE=0D +#define PXE_CLIENT_ARCH_LOONGARCH64 0x0027 /// LoongArch uefi 64= for PXE=0D =0D -#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from = http=0D -#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from = http=0D -#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http= =0D -#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot fr= om http=0D -#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot fr= om http=0D -#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot= from http=0D -#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot= from http=0D -#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boo= t from http=0D +#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot fr= om http=0D +#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot fr= om http=0D +#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from ht= tp=0D +#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot= from http=0D +#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot= from http=0D +#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 b= oot from http=0D +#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 b= oot from http=0D +#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 = boot from http=0D +#define HTTP_CLIENT_ARCH_LOONGARCH32 0x0026 /// LoongArch uefi 3= 2 boot from http=0D +#define HTTP_CLIENT_ARCH_LOONGARCH64 0x0028 /// LoongArch uefi 6= 4 boot from http=0D =0D #endif=0D --=20 2.27.0