From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) by mx.groups.io with SMTP id smtpd.web08.10988.1664460448267482812 for ; Thu, 29 Sep 2022 07:07:28 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@redhat.com header.s=mimecast20190719 header.b=hcwAP1zH; spf=pass (domain: redhat.com, ip: 170.10.133.124, mailfrom: kraxel@redhat.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1664460447; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lWPRQ0DQ2//+h15jmXFth4note6UgzkFhmSUSUwcWoc=; b=hcwAP1zHp4CKu+AWbp+SsfpoE4OiIphgD0EYHXOp2jJEvzMz/4+lyhPTwntd/g+vLdjC9d m8kO7oovh14lLCwFUxUyWAdxqe7QA+5pRipoNQ2v5s6dDo8A/whhiBggxfDG88g2BEukWJ 9igXeBBdKJqLH1kFnv+gHijLmHhIaao= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-488-bAYdj8wtPZSHf-EmCk_NvQ-1; Thu, 29 Sep 2022 10:07:23 -0400 X-MC-Unique: bAYdj8wtPZSHf-EmCk_NvQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 0AF6C1C068D1; Thu, 29 Sep 2022 14:07:23 +0000 (UTC) Received: from sirius.home.kraxel.org (unknown [10.39.194.9]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 89071145B98C; Thu, 29 Sep 2022 14:07:22 +0000 (UTC) Received: by sirius.home.kraxel.org (Postfix, from userid 1000) id DFC0F18009B7; Thu, 29 Sep 2022 16:07:20 +0200 (CEST) From: "Gerd Hoffmann" To: devel@edk2.groups.io Cc: Gerd Hoffmann , Oliver Steffen , Ard Biesheuvel , Jiewen Yao , Pawel Polawski , Jordan Justen Subject: [PATCH 1/4] OvmfPkg/PlatformInitLib: qemu cpuid physbits detection Date: Thu, 29 Sep 2022 16:07:17 +0200 Message-Id: <20220929140720.1501464-2-kraxel@redhat.com> In-Reply-To: <20220929140720.1501464-1-kraxel@redhat.com> References: <20220929140720.1501464-1-kraxel@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="US-ASCII"; x-default=true Add some qemu specific quirks to PlatformAddressWidthFromCpuid() to figure whenever the PhysBits value returned by CPUID is something real we can work with or not. See the source code comment for details on the logic. Also apply some limits to the address space we are going to use: * Place a hard cap at 47 PhysBits (128 TB) to avoid using addresses which require 5-level paging support. * Cap at 40 PhysBits (1 TB) in case the CPU has no support for gigabyte pages, to avoid excessive amounts of pages being used for page tables. Signed-off-by: Gerd Hoffmann --- OvmfPkg/Library/PlatformInitLib/MemDetect.c | 102 ++++++++++++++++---- 1 file changed, 84 insertions(+), 18 deletions(-) diff --git a/OvmfPkg/Library/PlatformInitLib/MemDetect.c b/OvmfPkg/Library/PlatformInitLib/MemDetect.c index d1a4f4b20791..143a01ceb01e 100644 --- a/OvmfPkg/Library/PlatformInitLib/MemDetect.c +++ b/OvmfPkg/Library/PlatformInitLib/MemDetect.c @@ -503,39 +503,105 @@ PlatformGetFirstNonAddress ( } /* - * Use CPUID to figure physical address width. Does *not* work - * reliable on qemu. For historical reasons qemu returns phys-bits=40 - * even in case the host machine supports less than that. - * - * qemu has a cpu property (host-phys-bits={on,off}) to change that - * and make sure guest phys-bits are not larger than host phys-bits., - * but it is off by default. Exception: microvm machine type - * hard-wires that property to on. + * Use CPUID to figure physical address width. + * + * Does *not* work reliable on qemu. For historical reasons qemu + * returns phys-bits=40 by default even in case the host machine + * supports less than that. + * + * So we apply the following rules (which can be enabled/disabled + * using the QemuQuirk parameter) to figure whenever we can work with + * the returned physical address width or not: + * + * (1) If it is 41 or higher consider it valid. + * (2) If it is 40 or lower consider it valid in case it matches a + * known-good value for the CPU vendor, which is: + * -> 36 or 39 for Intel + * -> 40 for AMD + * (3) Otherwise consider it invalid. + * + * Recommendation: Run qemu with host-phys-bits=on. That will make + * sure guest phys-bits is not larger than host phys-bits. Some + * distro builds do that by default. */ VOID EFIAPI PlatformAddressWidthFromCpuid ( - IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob, + IN BOOLEAN QemuQuirk ) { - UINT32 RegEax; + UINT32 RegEax, RegEbx, RegEcx, RegEdx, Max; + UINT8 PhysBits; + CHAR8 Signature[13] = { 0 }; + BOOLEAN Valid = FALSE; + BOOLEAN Page1GSupport = FALSE; - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); - if (RegEax >= 0x80000008) { + AsmCpuid (0x80000000, &RegEax, &RegEbx, &RegEcx, &RegEdx); + *(UINT32 *)(Signature + 0) = RegEbx; + *(UINT32 *)(Signature + 4) = RegEdx; + *(UINT32 *)(Signature + 8) = RegEcx; + Max = RegEax; + + if (Max >= 0x80000001) { + AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx); + if ((RegEdx & BIT26) != 0) { + Page1GSupport = TRUE; + } + } + + if (Max >= 0x80000008) { AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - PlatformInfoHob->PhysMemAddressWidth = (UINT8)RegEax; + PhysBits = (UINT8)RegEax; } else { - PlatformInfoHob->PhysMemAddressWidth = 36; + PhysBits = 36; } - PlatformInfoHob->FirstNonAddress = LShiftU64 (1, PlatformInfoHob->PhysMemAddressWidth); + if (!QemuQuirk) { + Valid = TRUE; + } else if (PhysBits >= 41) { + Valid = TRUE; + } else if (AsciiStrCmp (Signature, "GenuineIntel") == 0) { + if ((PhysBits == 36) || (PhysBits == 39)) { + Valid = TRUE; + } + } else if (AsciiStrCmp (Signature, "AuthenticAMD") == 0) { + if (PhysBits == 40) { + Valid = TRUE; + } + } DEBUG (( DEBUG_INFO, - "%a: cpuid: phys-bits is %d\n", + "%a: Signature: '%a', PhysBits: %d, QemuQuirk: %a, Valid: %a\n", __FUNCTION__, - PlatformInfoHob->PhysMemAddressWidth + Signature, + PhysBits, + QemuQuirk ? "On" : "Off", + Valid ? "Yes" : "No" )); + + if (Valid) { + if (PhysBits > 47) { + /* + * Avoid 5-level paging altogether for now, which limits + * PhysBits to 48. Also avoid using address bit 48, due to sign + * extension we can't identity-map these addresses (and lots of + * places in edk2 assume we have everything identity-mapped). + * So the actual limit is 47. + */ + DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 47 (avoid 5-level paging)\n", __func__)); + PhysBits = 47; + } + + if (!Page1GSupport && (PhysBits > 40)) { + DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 40 (no 1G pages available)\n", __func__)); + PhysBits = 40; + } + + PlatformInfoHob->PhysMemAddressWidth = PhysBits; + PlatformInfoHob->FirstNonAddress = LShiftU64 (1, PlatformInfoHob->PhysMemAddressWidth); + } } /** @@ -672,7 +738,7 @@ PlatformAddressWidthInitialization ( EFI_STATUS Status; if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) { - PlatformAddressWidthFromCpuid (PlatformInfoHob); + PlatformAddressWidthFromCpuid (PlatformInfoHob, FALSE); return; } -- 2.37.3