From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f169.google.com (mail-pf1-f169.google.com [209.85.210.169]) by mx.groups.io with SMTP id smtpd.web10.4743.1665396780291515258 for ; Mon, 10 Oct 2022 03:13:02 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=UJtAj8Dq; spf=pass (domain: ventanamicro.com, ip: 209.85.210.169, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f169.google.com with SMTP id y8so10329021pfp.13 for ; Mon, 10 Oct 2022 03:13:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WcUQcrlsOuHVgj2JRl2uz0DW7Dlkd5aEGmo3h0WynhM=; b=UJtAj8DqXTALKuPGxpgcwES2vW+IIwAusrbpTINFzR6MQuaLmtT4UF5cyTGhTv97KH zUsdxI9JNyBCyKWSAh/R2oT2MpFfCTcYbYYpdqjwxfJg4xAHwcK7qxORM2V87IgU9LIU aVnBtwnNHXF2K9LhX9+ulBelQQFCjM7CAM7Ew5usWpnMLYh0c9j3ggTXzlu+3sGp8ZsF yrWAVM8dBUqOH5FHl+wkig/ssSSSIhITPwFWdbKzk3mZbSDHhKulV0dAth0yYsjXmjSf 3HH0D/559EYt/4wsfHagmETOS+PmWk4Q+fQVLpo0rR5uFdo833D6Bp3oCOGlEzuK2AHU +AqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WcUQcrlsOuHVgj2JRl2uz0DW7Dlkd5aEGmo3h0WynhM=; b=UOcjMwlwGEWs+XD1hOFb2k2SRs83RHKVl7jP+2U2TLxfmYsCLHD2dCGzqCdOHvIIl4 AQdOsu3ZVRoChrYuUNRBxJYdjX4/1r/ZmtZ18jRhCfAWqEDy2R+xC5TbqPdVcS0CZgyo ulst0McU9jLP39WPy6D4NeZLzqg4H29SDb6BRaWGbclRYaqjt7Da3cGt1n79RxGt/OHO hbfID1Z1R+4lgmipv899i2BNyC9kjQ9g/IvCHf+e4030CE7cMevAv1Cgr2zWIuObYXTZ WBW6ITe9pK0XrR0I0ZtJYmb55yjp6hdtQt4PX9+7SvLQD/carON9NTAsjMZ7QNdJZ0AT fpTQ== X-Gm-Message-State: ACrzQf1VnOAWedOiCj+vYqUv/096mCdIkQFqQaoVJ3gUDPle0BgBdb2w ndSbsyr78BOTgyIzElmz5cDblI3vxmqDRw== X-Google-Smtp-Source: AMsMyM74VOsxyLVTfO401EhJ52Oq4YZI/DkCmbjxQcfAVhjn/Gip2GNdilaoiv+H2stBQ+2dUTmjRg== X-Received: by 2002:a63:d551:0:b0:452:87e0:73d5 with SMTP id v17-20020a63d551000000b0045287e073d5mr15549077pgi.488.1665396782164; Mon, 10 Oct 2022 03:13:02 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id h17-20020a170902f55100b001788ccecbf5sm6302138plf.31.2022.10.10.03.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Oct 2022 03:13:01 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer Subject: [edk2-staging/RiscV64QemuVirt PATCH 19/29] UefiCpuPkg/CpuDxe: Add RISC-V Boot protocol support Date: Mon, 10 Oct 2022 15:41:52 +0530 Message-Id: <20221010101202.1146624-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221010101202.1146624-1-sunilvl@ventanamicro.com> References: <20221010101202.1146624-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add the support for this protocol which is defined in the spec: https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_UEFI_PROTOCOL-spec.pdf Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L --- UefiCpuPkg/UefiCpuPkg.dsc | 12 +++--- UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 66 ++++++++++++++++++++++++++++-- 2 files changed, 68 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index f694b3a77c2e..6ea90507e36f 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -122,9 +122,13 @@ [Components] UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf - -[Components.IA32, Components.X64] UefiCpuPkg/CpuDxe/CpuDxe.inf + UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +!if $(TOOL_CHAIN_TAG) != "XCODE5" + UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf +!endif + +[Components.IA32, Components.X64] UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf { NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -141,10 +145,6 @@ [Components.IA32, Components.X64] UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf - UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf -!if $(TOOL_CHAIN_TAG) != "XCODE5" - UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf -!endif UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c index 9f557b776a09..7551e0653603 100644 --- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -2,6 +2,7 @@ RISC-V CPU DXE driver. Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -12,8 +13,41 @@ // // Global Variables // -STATIC BOOLEAN mInterruptState = FALSE; -STATIC EFI_HANDLE mCpuHandle = NULL; +STATIC BOOLEAN mInterruptState = FALSE; +STATIC EFI_HANDLE mCpuHandle = NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +/** + Get the boot hartid + + @param This Protocol instance structure + @param BootHartId Pointer to the Boot Hart ID variable + + @retval EFI_SUCCESS If BootHartId is returned + @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is not + a valid RISCV_EFI_BOOT_PROTOCOL instance. + +**/ +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if ((This != &gRiscvBootProtocol) || (BootHartId == NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId = mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; EFI_CPU_ARCH_PROTOCOL gCpu = { CpuFlushCpuDataCache, @@ -284,15 +318,39 @@ InitializeCpu ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; - InitializeCpuExceptionHandlers(NULL); + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext != NULL); + if (FirmwareContext == NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_CONTEXT\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__, FirmwareContext)); + + mBootHartId = FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__, mBootHartId)); + + InitializeCpuExceptionHandlers (NULL); // // Make sure interrupts are disabled // DisableInterrupts (); + // + // Install Boot protocol + // + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + ASSERT_EFI_ERROR (Status); + // // Install CPU Architectural Protocol // -- 2.25.1