public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Sunil V L" <sunilvl@ventanamicro.com>
To: devel@edk2.groups.io
Cc: Eric Dong <eric.dong@intel.com>, Ray Ni <ray.ni@intel.com>,
	Rahul Kumar <rahul1.kumar@intel.com>,
	Daniel Schaefer <git@danielschaefer.me>
Subject: [edk2-staging/RiscV64QemuVirt PATCH V2 14/33] UefiCpuPkg/CpuTimerLib: Add support for RISC-V
Date: Wed, 12 Oct 2022 16:14:37 +0530	[thread overview]
Message-ID: <20221012104456.1393376-15-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20221012104456.1393376-1-sunilvl@ventanamicro.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

This is mostly copied from
edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
 .../Library/CpuTimerLib/BaseCpuTimerLib.inf   |   3 +
 .../Library/CpuTimerLib/RiscV64/CpuTimerLib.c | 199 ++++++++++++++++++
 2 files changed, 202 insertions(+)
 create mode 100644 UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c

diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
index a22457b44940..554ce9fe9db8 100644
--- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
+++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf
@@ -22,6 +22,9 @@ [Sources.IA32, Sources.X64]
   Ia32_X64/CpuTimerLib.c
   Ia32_X64/BaseCpuTimerLib.c
 
+[Sources.RISCV64]
+  RiscV64/CpuTimerLib.c
+
 [Packages]
   MdePkg/MdePkg.dec
   UefiCpuPkg/UefiCpuPkg.dec
diff --git a/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c
new file mode 100644
index 000000000000..9c8efc0f3530
--- /dev/null
+++ b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c
@@ -0,0 +1,199 @@
+/** @file
+  RISC-V instance of Timer Library.
+
+  Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Register/RiscV64/RiscVImpl.h>
+
+/**
+  Stalls the CPU for at least the given number of ticks.
+
+  Stalls the CPU for at least the given number of ticks. It's invoked by
+  MicroSecondDelay() and NanoSecondDelay().
+
+  @param  Delay     A period of time to delay in ticks.
+
+**/
+VOID
+InternalRiscVTimerDelay (
+  IN UINT32  Delay
+  )
+{
+  UINT32  Ticks;
+  UINT32  Times;
+
+  Times  = Delay >> (RISCV_TIMER_COMPARE_BITS - 2);
+  Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1);
+  do {
+    //
+    // The target timer count is calculated here
+    //
+    Ticks = RiscVReadTimer () + Delay;
+    Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2);
+    while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) {
+      CpuPause ();
+    }
+  } while (Times-- > 0);
+}
+
+/**
+  Stalls the CPU for at least the given number of microseconds.
+
+  Stalls the CPU for the number of microseconds specified by MicroSeconds.
+
+  @param  MicroSeconds  The minimum number of microseconds to delay.
+
+  @return MicroSeconds
+
+**/
+UINTN
+EFIAPI
+MicroSecondDelay (
+  IN UINTN  MicroSeconds
+  )
+{
+  InternalRiscVTimerDelay (
+    (UINT32)DivU64x32 (
+              MultU64x32 (
+                MicroSeconds,
+                PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+                ),
+              1000000u
+              )
+    );
+  return MicroSeconds;
+}
+
+/**
+  Stalls the CPU for at least the given number of nanoseconds.
+
+  Stalls the CPU for the number of nanoseconds specified by NanoSeconds.
+
+  @param  NanoSeconds The minimum number of nanoseconds to delay.
+
+  @return NanoSeconds
+
+**/
+UINTN
+EFIAPI
+NanoSecondDelay (
+  IN UINTN  NanoSeconds
+  )
+{
+  InternalRiscVTimerDelay (
+    (UINT32)DivU64x32 (
+              MultU64x32 (
+                NanoSeconds,
+                PcdGet64 (PcdCpuCoreCrystalClockFrequency)
+                ),
+              1000000000u
+              )
+    );
+  return NanoSeconds;
+}
+
+/**
+  Retrieves the current value of a 64-bit free running performance counter.
+
+  Retrieves the current value of a 64-bit free running performance counter. The
+  counter can either count up by 1 or count down by 1. If the physical
+  performance counter counts by a larger increment, then the counter values
+  must be translated. The properties of the counter can be retrieved from
+  GetPerformanceCounterProperties().
+
+  @return The current value of the free running performance counter.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounter (
+  VOID
+  )
+{
+  return (UINT64)RiscVReadTimer ();
+}
+
+/**return
+  Retrieves the 64-bit frequency in Hz and the range of performance counter
+  values.
+
+  If StartValue is not NULL, then the value that the performance counter starts
+  with immediately after is it rolls over is returned in StartValue. If
+  EndValue is not NULL, then the value that the performance counter end with
+  immediately before it rolls over is returned in EndValue. The 64-bit
+  frequency of the performance counter in Hz is always returned. If StartValue
+  is less than EndValue, then the performance counter counts up. If StartValue
+  is greater than EndValue, then the performance counter counts down. For
+  example, a 64-bit free running counter that counts up would have a StartValue
+  of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter
+  that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.
+
+  @param  StartValue  The value the performance counter starts with when it
+                      rolls over.
+  @param  EndValue    The value that the performance counter ends with before
+                      it rolls over.
+
+  @return The frequency in Hz.
+
+**/
+UINT64
+EFIAPI
+GetPerformanceCounterProperties (
+  OUT      UINT64 *StartValue, OPTIONAL
+  OUT      UINT64                    *EndValue     OPTIONAL
+  )
+{
+  if (StartValue != NULL) {
+    *StartValue = 0;
+  }
+
+  if (EndValue != NULL) {
+    *EndValue = 32 - 1;
+  }
+
+  return PcdGet64 (PcdCpuCoreCrystalClockFrequency);
+}
+
+/**
+  Converts elapsed ticks of performance counter to time in nanoseconds.
+
+  This function converts the elapsed ticks of running performance counter to
+  time value in unit of nanoseconds.
+
+  @param  Ticks     The number of elapsed ticks of running performance counter.
+
+  @return The elapsed time in nanoseconds.
+
+**/
+UINT64
+EFIAPI
+GetTimeInNanoSecond (
+  IN      UINT64  Ticks
+  )
+{
+  UINT64  NanoSeconds;
+  UINT32  Remainder;
+
+  //
+  //          Ticks
+  // Time = --------- x 1,000,000,000
+  //        Frequency
+  //
+  NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdCpuCoreCrystalClockFrequency), &Remainder), 1000000000u);
+
+  //
+  // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000)
+  // will not overflow 64-bit.
+  //
+  NanoSeconds += DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u), PcdGet64 (PcdCpuCoreCrystalClockFrequency));
+
+  return NanoSeconds;
+}
-- 
2.25.1


  parent reply	other threads:[~2022-10-12 10:45 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-12 10:44 [edk2-staging/RiscV64QemuVirt PATCH V2 00/33] Add support for RISC-V virt machine Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 01/33] MdePkg/Register: Add register definition header files for RISC-V Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 02/33] MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 03/33] MdePkg/BaseLib: RISC-V: Add few more helper functions Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 04/33] MdePkg: Add BaseRiscVSbiLib Library for RISC-V Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 05/33] OvmfPkg/PlatformInitLib: Refactor to allow other architectures Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 06/33] OvmfPkg/PlatformInitLib: Add support for RISC-V Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 07/33] OvmfPkg/ResetSystemLib: Refactor to allow other architectures Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 08/33] OvmfPkg/ResetSystemLib: Add support for RISC-V Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 09/33] OvmfPkg/Sec: Refactor to allow other architectures Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 10/33] OvmfPkg/Sec: Add RISC-V support Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 11/33] OvmfPkg/PlatformPei: Refactor to allow other architectures Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 12/33] OvmfPkg/PlatformPei: Add support for RISC-V Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 13/33] UefiCpuPkg/CpuTimerLib: Refactor to allow other architectures Sunil V L
2022-10-12 10:44 ` Sunil V L [this message]
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 15/33] UefiCpuPkg/CpuExceptionHandlerLib: " Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 16/33] UefiCpuPkg/CpuExceptionHandlerLib: Add support for RISC-V Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 17/33] UefiCpuPkg/CpuDxe: Refactor to allow other architectures Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 18/33] UefiCpuPkg/CpuDxe: Add support for RISC-V Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 19/33] UefiCpuPkg/CpuDxe: Add RISC-V Boot protocol support Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 20/33] UefiCpuPkg: Add CpuTimerDxe module Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 21/33] ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 22/33] ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 23/33] ArmVirtPkg/PlatformBootManagerLib: Move to OvmfPkg Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 24/33] ArmVirtPkg: Fix up the paths to PlatformBootManagerLib Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 25/33] ArmPlatformPkg/NorFlashPlatformLib.h:Move to MdePkg Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 26/33] EmbeddedPkg/NvVarStoreFormattedLib: Migrate to MdeModulePkg Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 27/33] OvmfPkg: Add NorFlashQemuLib library Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 28/33] OvmfPkg: Add Qemu NOR flash DXE driver Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 29/33] OvmfPkg/NorFlashDxe: Avoid switching to array mode during writes Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 30/33] OvmfPkg/NorFlashDxe: Avoid switching between modes in a tight loop Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 31/33] OvmfPkg: RiscVVirt: Add Qemu Virt platform support Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 32/33] Maintainers.txt: Add entry for OvmfPkg/RiscVVirt Sunil V L
2022-10-12 10:44 ` [edk2-staging/RiscV64QemuVirt PATCH V2 33/33] UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file Sunil V L

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20221012104456.1393376-15-sunilvl@ventanamicro.com \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox