From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f173.google.com (mail-pl1-f173.google.com [209.85.214.173]) by mx.groups.io with SMTP id smtpd.web09.18995.1665571509712688102 for ; Wed, 12 Oct 2022 03:45:09 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=I9n3s/ik; spf=pass (domain: ventanamicro.com, ip: 209.85.214.173, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pl1-f173.google.com with SMTP id h10so15885471plb.2 for ; Wed, 12 Oct 2022 03:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GGzPFyT2nPg858ze2vAmbQioiqDOOCniOoTIl4O3Ebc=; b=I9n3s/ik7jM2+Vc6cMbsSHbPDoj+9iFoNXQ/z3G5LL4fT2DMqrOUjl31Y17G6oVKRw fC3o87OshCI7vXbe8Peq56+A1SLrOHUYuQ4ooIoaEmA6ZhFJPoh5KfLlDz8p6kI2f0HZ fV9hi9R1imaqCe1Rx+A5X6BDBX99VTCO1PK5/6hV17oyWwx5HSIHU7jHNQQue0keHAFx nzi/Gd7SqhUMfAuwy0lcIOw15JeuhqeEaeY75B8dPN8w5hQwKCiwI3DaSmXJY64xQmps u9QrkafWdTPe6mcZLiEXrMxl89HlFeeBYM+Z3mapSka72YnNjPeYeK+n6Ro29nnjDwuG nQaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GGzPFyT2nPg858ze2vAmbQioiqDOOCniOoTIl4O3Ebc=; b=gsQEv7rkYrMEEPCFbd5J3n9Ju7k2ViJO6GFn3Z5+k26MNz90vr5ZoN9926Z5P9p8D9 +YCthhZt5Bpf7Gsuyh5wbScaauIn+2Gf693Pm+WMP32f8scglWbKpsaVAVFKBNgOPCos vd/iXBwvN4eA3YRPVByC5Mpaxuz5ei+1ApxVg8DtOIuQWhTGCzvAAp8znfOGJPbqthw6 6DPrKdhw7l+zaYmfUA7dwz8jIDwXXs8Ov3JqbYbWY4Vqnv9D8i+HglRDuCkAxIHooZvw wnJZUkzuazPnnxzhnHCz+TpM0v+xjjrYalFfepuPWhj4EoscyvWJHFY+Sf8CouyQqSwM T43A== X-Gm-Message-State: ACrzQf26+Z0/aB32RzZMp8EMs5ThZoh03AOdvd4f86XwWZkxd0SG54BZ 3vaoSLCNkMJefmLDKhWtXkpuxuF3cepM3g== X-Google-Smtp-Source: AMsMyM5HuCWZ6LJos0PFcKjrftgsg4v5rKAZE8B6ZGcNggnhVz31EMr6BuJm2tIcX6T+t6wFcYlwGQ== X-Received: by 2002:a17:902:9b82:b0:183:fffb:1bfe with SMTP id y2-20020a1709029b8200b00183fffb1bfemr6118475plp.173.1665571508923; Wed, 12 Oct 2022 03:45:08 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id z4-20020aa79e44000000b0054223a0185asm10812221pfq.161.2022.10.12.03.45.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Oct 2022 03:45:08 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [edk2-staging/RiscV64QemuVirt PATCH V2 01/33] MdePkg/Register: Add register definition header files for RISC-V Date: Wed, 12 Oct 2022 16:14:24 +0530 Message-Id: <20221012104456.1393376-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221012104456.1393376-1-sunilvl@ventanamicro.com> References: <20221012104456.1393376-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Sunil V L --- .../Include/Register/RiscV64/RiscVEncoding.h | 124 ++++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 24 ++++ 2 files changed, 148 insertions(+) create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h new file mode 100644 index 000000000000..c98c36ac4cde --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -0,0 +1,124 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. All rights reserved.
+ * Copyright (c) 2022 Ventana Micro Systems Inc. All rights reserved.
+ * + */ + +#ifndef __RISCV_ENCODING_H__ +#define __RISCV_ENCODING_H__ + +/* clang-format off */ +#define MSTATUS_SIE 0x00000002UL +#define MSTATUS_MIE 0x00000008UL +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) +#define MSTATUS_UBE 0x00000040UL +#define MSTATUS_MPIE 0x00000080UL +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) + +#define SSTATUS_SIE MSTATUS_SIE +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT +#define SSTATUS_SPIE MSTATUS_SPIE +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT +#define SSTATUS_SPP MSTATUS_SPP + +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define MIP_SSIP (1UL << IRQ_S_SOFT) +#define MIP_VSSIP (1UL << IRQ_VS_SOFT) +#define MIP_MSIP (1UL << IRQ_M_SOFT) +#define MIP_STIP (1UL << IRQ_S_TIMER) +#define MIP_VSTIP (1UL << IRQ_VS_TIMER) +#define MIP_MTIP (1UL << IRQ_M_TIMER) +#define MIP_SEIP (1UL << IRQ_S_EXT) +#define MIP_VSEIP (1UL << IRQ_VS_EXT) +#define MIP_MEIP (1UL << IRQ_M_EXT) +#define MIP_SGEIP (1UL << IRQ_S_GEXT) +#define MIP_LCOFIP (1UL << IRQ_PMU_OVF) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0UL +#define PRV_S 1UL +#define PRV_M 3UL + +#define SATP64_MODE 0xF000000000000000ULL +#define SATP64_ASID 0x0FFFF00000000000ULL +#define SATP64_PPN 0x00000FFFFFFFFFFFULL + +#define SATP_MODE_OFF 0UL +#define SATP_MODE_SV32 1UL +#define SATP_MODE_SV39 8UL +#define SATP_MODE_SV48 9UL +#define SATP_MODE_SV57 10UL +#define SATP_MODE_SV64 11UL + +#define SATP_MODE SATP64_MODE + +/* ===== User-level CSRs ===== */ + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 + +/* ===== Supervisor-level CSRs ===== */ + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* ===== Trap/Exception Causes ===== */ + +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INST_FAULT 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h new file mode 100644 index 000000000000..7dc100ecf510 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -0,0 +1,24 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include + +#ifndef __RISCV_IMPL_H_ +#define __RISCV_IMPL_H_ + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) +#define RISCV_TIMER_COMPARE_BITS 32 + +#endif -- 2.25.1