From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f181.google.com (mail-pl1-f181.google.com [209.85.214.181]) by mx.groups.io with SMTP id smtpd.web11.18730.1665571569518773081 for ; Wed, 12 Oct 2022 03:46:09 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=JYoc1/7U; spf=pass (domain: ventanamicro.com, ip: 209.85.214.181, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pl1-f181.google.com with SMTP id l4so15868909plb.8 for ; Wed, 12 Oct 2022 03:46:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WcUQcrlsOuHVgj2JRl2uz0DW7Dlkd5aEGmo3h0WynhM=; b=JYoc1/7UK+X3QOJpF2CQFc5gYiDam8DIoI9XJDWBw/xCDqYnaBkLYWIRQYqyjW4op6 6DmKVNZaV7l2vCiZ1YSIwuNQXfzwJkAsvh29fSa5YrHYooaFbp1zG3p9qojWiiJCOz2J cXv/QkIDx1btP+aMd2AG26UIsDGLKGVg1TphmYt0wDvwUWF+CDK+Xd+WOrcfQlCsvCio GeIcUE2hHCVYOwYEs2Gvclb+rqESdkb76A/hHFW4uFA8Dffv1WiJ1zL4E4g66er6FSeZ RKZFdl2h52nSSi0B/7pdbfmlyZklBX7/7IYj3OHABbeiXPvQVQVviV//3w6Cm1KxlYoo KTcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WcUQcrlsOuHVgj2JRl2uz0DW7Dlkd5aEGmo3h0WynhM=; b=Scx/GYojcXkdmZDBaEI12gQAWFtWKjgQqPKshiO0tGuW0mK6KDLLFbOiB260Ve7TzE Yak9fy4PBDLt3lO45EDcB00Enilhgun6KSzG+/Vj806C6mpRgRqMsr3MW5EZ+tpbX4di z66UBfHUvIBB2twxaXnHxAXdZaXU8VfD6ywgfVhjXzxsDxGtuuY1IixR7klUUaT5ymQ1 SBCpWG8494d4t3Se3MNb4phRg+XIrEtfdWZtA0CxmukcMb0eJBvat0aCgLpFEIt48pO1 XdurfXTO2/mBFtb8/6SPLkjFAEbfqq3cKKLDmZpH/glqD4KjlcoDNx9xfIaqEHAaqprA GTJQ== X-Gm-Message-State: ACrzQf1m2G2CBjUyqr5WcrVr+3qqC4sh2ABb534oR4NX3CgBAnIBwmfa I5udf/gzZig54ta+m5b3xnydoaTmcHqxFw== X-Google-Smtp-Source: AMsMyM7u8u3jFIGaEwqNVZ0d+rCTNEZ1tdI1TEm0ueXw0R/XCg/H8qI1a0RHSMu9JhChaR/v78d7Jg== X-Received: by 2002:a17:902:ea02:b0:181:f8d2:1c2b with SMTP id s2-20020a170902ea0200b00181f8d21c2bmr17499509plg.107.1665571568715; Wed, 12 Oct 2022 03:46:08 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id z4-20020aa79e44000000b0054223a0185asm10812221pfq.161.2022.10.12.03.46.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Oct 2022 03:46:08 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer Subject: [edk2-staging/RiscV64QemuVirt PATCH V2 19/33] UefiCpuPkg/CpuDxe: Add RISC-V Boot protocol support Date: Wed, 12 Oct 2022 16:14:42 +0530 Message-Id: <20221012104456.1393376-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221012104456.1393376-1-sunilvl@ventanamicro.com> References: <20221012104456.1393376-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add the support for this protocol which is defined in the spec: https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_UEFI_PROTOCOL-spec.pdf Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L --- UefiCpuPkg/UefiCpuPkg.dsc | 12 +++--- UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 66 ++++++++++++++++++++++++++++-- 2 files changed, 68 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index f694b3a77c2e..6ea90507e36f 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -122,9 +122,13 @@ [Components] UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf - -[Components.IA32, Components.X64] UefiCpuPkg/CpuDxe/CpuDxe.inf + UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +!if $(TOOL_CHAIN_TAG) != "XCODE5" + UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf +!endif + +[Components.IA32, Components.X64] UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf { NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -141,10 +145,6 @@ [Components.IA32, Components.X64] UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf - UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf -!if $(TOOL_CHAIN_TAG) != "XCODE5" - UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf -!endif UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c index 9f557b776a09..7551e0653603 100644 --- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -2,6 +2,7 @@ RISC-V CPU DXE driver. Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -12,8 +13,41 @@ // // Global Variables // -STATIC BOOLEAN mInterruptState = FALSE; -STATIC EFI_HANDLE mCpuHandle = NULL; +STATIC BOOLEAN mInterruptState = FALSE; +STATIC EFI_HANDLE mCpuHandle = NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +/** + Get the boot hartid + + @param This Protocol instance structure + @param BootHartId Pointer to the Boot Hart ID variable + + @retval EFI_SUCCESS If BootHartId is returned + @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is not + a valid RISCV_EFI_BOOT_PROTOCOL instance. + +**/ +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if ((This != &gRiscvBootProtocol) || (BootHartId == NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId = mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; EFI_CPU_ARCH_PROTOCOL gCpu = { CpuFlushCpuDataCache, @@ -284,15 +318,39 @@ InitializeCpu ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; - InitializeCpuExceptionHandlers(NULL); + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext != NULL); + if (FirmwareContext == NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_CONTEXT\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__, FirmwareContext)); + + mBootHartId = FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__, mBootHartId)); + + InitializeCpuExceptionHandlers (NULL); // // Make sure interrupts are disabled // DisableInterrupts (); + // + // Install Boot protocol + // + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + ASSERT_EFI_ERROR (Status); + // // Install CPU Architectural Protocol // -- 2.25.1