From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) by mx.groups.io with SMTP id smtpd.web11.5668.1665655159175675521 for ; Thu, 13 Oct 2022 02:59:19 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=iyuqtoAa; spf=pass (domain: ventanamicro.com, ip: 209.85.210.177, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pf1-f177.google.com with SMTP id y1so1510703pfr.3 for ; Thu, 13 Oct 2022 02:59:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eVGC+gpoKH0Z+QptuNZzlYFzPwB53yINKHidgk2vhLI=; b=iyuqtoAaOsQclYLi8K8uwulT2Ezk/Bzhj3QDwO/fEMxw56P/sov7ogNOzbPuaYKBbe QnKh1u7HFlMg5GFQAZCPa5B3fzU8XVyooBSa5xifjB+0K8No5M0WuYbAHpBSGKTZGVcd nokPNC4I4MxKFzuRPjCS6Cuji0q9gifcI6aLlKperYYlY372D8WAG5xB+xvztzNYIRFb lgj12ETMCJmo9+NH2gDjC0CAubJ+XILGdZcEEtztLop06ubu4dospvBAMo7VB+gpENtb uLgBLopI/r8MH/H96qq9rT93SXZn/34TKyhxFlw9T32spzr6N7KxaxJczheoTqUZGJlN nS6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eVGC+gpoKH0Z+QptuNZzlYFzPwB53yINKHidgk2vhLI=; b=Jf6WxTi9XRBRr83tr704MS92XpyvEmSdY2KAlMkglLa5szVyrLhDu0FCE7/LGN/8QD oHY/IOdexL7Mey2jXFMIMW0Fy4gU6q7rcDJL3TszIv+sbwO6Dh1uGdgahnenk9XmBNTP higrkKdwTC/fU07RtpT5RhQMcAuZ/ZGmQdVND9eBa2PGGiOd7BNjZuvLkdh9OBgCwdQp ddWcmD+lGjwGCzMYG70EQ+q0eV8x//Od1klmXxXJ/2lxJFrROUCRvHjC+KBkEMF/pa+e 4YS/QmR4pypj0fuZk4OgGS0xuDyJd4hhMomGZ/bTyLKn7IjNzybrUiBpQZIf1D8/IlXM +8cA== X-Gm-Message-State: ACrzQf2/cuZ5NOl9NYIp1fpPWLztPVZcKAsn4mTiT0hmGlFayrvg6MTe C5g+hNYcR0b7DbXY2RjnGZyceKMC3QCs4w== X-Google-Smtp-Source: AMsMyM6dXgunbVK+gLySqn3QGIkbhUWrAxruGq0uOp6YqHyqCudjGb7ba6XLDQgXN3iu6njEeJhpBg== X-Received: by 2002:a63:2bd5:0:b0:434:ea9a:ace2 with SMTP id r204-20020a632bd5000000b00434ea9aace2mr29767540pgr.323.1665655158171; Thu, 13 Oct 2022 02:59:18 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id w8-20020a17090abc0800b0020d43c5c9a0sm2931845pjr.18.2022.10.13.02.59.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Oct 2022 02:59:17 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer Subject: [edk2-staging/RiscV64QemuVirt PATCH V3 14/34] UefiCpuPkg/CpuTimerLib: Add support for RISC-V Date: Thu, 13 Oct 2022 15:28:09 +0530 Message-Id: <20221013095829.1454581-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221013095829.1454581-1-sunilvl@ventanamicro.com> References: <20221013095829.1454581-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L --- .../Library/CpuTimerLib/BaseCpuTimerLib.inf | 3 + .../Library/CpuTimerLib/RiscV64/CpuTimerLib.c | 199 ++++++++++++++++++ 2 files changed, 202 insertions(+) create mode 100644 UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf index a22457b44940..554ce9fe9db8 100644 --- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf +++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf @@ -22,6 +22,9 @@ [Sources.IA32, Sources.X64] Ia32_X64/CpuTimerLib.c Ia32_X64/BaseCpuTimerLib.c +[Sources.RISCV64] + RiscV64/CpuTimerLib.c + [Packages] MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec diff --git a/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c new file mode 100644 index 000000000000..9c8efc0f3530 --- /dev/null +++ b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c @@ -0,0 +1,199 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks = RiscVReadTimer () + Delay; + Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter. The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)RiscVReadTimer (); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter starts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end with + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartValue + is less than EndValue, then the performance counter counts up. If StartValue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a StartValue + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with before + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue != NULL) { + *StartValue = 0; + } + + if (EndValue != NULL) { + *EndValue = 32 - 1; + } + + return PcdGet64 (PcdCpuCoreCrystalClockFrequency); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance counter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time = --------- x 1,000,000,000 + // Frequency + // + NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdCpuCoreCrystalClockFrequency), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds += DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u), PcdGet64 (PcdCpuCoreCrystalClockFrequency)); + + return NanoSeconds; +} -- 2.25.1