From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) by mx.groups.io with SMTP id smtpd.web11.9783.1665766161659006876 for ; Fri, 14 Oct 2022 09:49:21 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=QGinN0AS; spf=pass (domain: ventanamicro.com, ip: 209.85.215.176, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pg1-f176.google.com with SMTP id q9so4768683pgq.8 for ; Fri, 14 Oct 2022 09:49:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P4MHiUp+ItOPy0j5E+49UGvfvsXU07BysANKBBoTKfs=; b=QGinN0ASqvrhlcRhleDm0tXyJE/WUj8zOhuy9n2WKvmkZeiWTE6wi8Lqxo/SJH+5N6 QPGLFK+2uBGZ+QeTV3F8+RdONyuP+C5IEbqJXpgHAebroSnzHywunJPy8AE26UzxkxNK C1E18EmYrewTNy1Mt1HZrBl4WAX2Y6LyTGeC0npH0VF25/RjizoJaXj/8+hJq+FZK2UQ f0XprHji3HGN8rOmLmovAXiukaXjUhrG/qER6DSNmYIEChfnkEfefuBox4VyrQ7pH65c QIaUn8kq1hsaUcq3TpiLwQ/W7thdfSWCI8kQz+yIn4lhZBsJWQ+2UwhdDyR00jp2uM+7 Z57A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P4MHiUp+ItOPy0j5E+49UGvfvsXU07BysANKBBoTKfs=; b=Xpe25IsoztWMWx8cpBBP1MfETarMc+6fRoF+skhs77Y0vw93v660tVGxZy6O622Y+z pXKMP7RvHnDYpWqk3LRszdty2gTDTHUq2Hlxt3lpbqPTQ0Z8wIpV/zofCK8zMahv+W9a utBx1iEGEB8dXwMDFuw//jB6TBzLY0Mr9OawszaQFj8iY4qkrij8aNlIHTssKNkKXmQp ys0QnPmOOVEqgA+ftLgKCR3+T9aJ3y65RyK32zATXJmPSgHas3Sw5IW6tHnY23zNWHWb +eH3Sdu6Y8ZfpE5GA/MNogL1BXlGdVWgsOrR8aK7vohjg+866rnIckWboBxrpio767++ JPfQ== X-Gm-Message-State: ACrzQf3tWR8lQkzOuWTufo8d9huRkdVsdJMbsR3dx2DKGUnxV5pluQlz VrR77KQxMKNSxToqvnoQ8O/nguxyMdajfA== X-Google-Smtp-Source: AMsMyM5RZXxUpIKwtB+fvnh1ZfTvO9fmQFmdkxf47H6mmR88+015RplTzcJpxtw3tiltqLKoeCfXag== X-Received: by 2002:a05:6a00:1488:b0:563:9d96:660f with SMTP id v8-20020a056a00148800b005639d96660fmr6427429pfu.0.1665766160682; Fri, 14 Oct 2022 09:49:20 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id f3-20020a62db03000000b0056265011136sm1963368pfg.112.2022.10.14.09.49.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 09:49:19 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer Subject: [edk2-staging/RiscV64QemuVirt PATCH V4 14/34] UefiCpuPkg/CpuTimerLib: Add support for RISC-V Date: Fri, 14 Oct 2022 22:18:16 +0530 Message-Id: <20221014164836.1513036-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221014164836.1513036-1-sunilvl@ventanamicro.com> References: <20221014164836.1513036-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L --- UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf | 3 + UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c | 199 ++++++++++++++++++++ 2 files changed, 202 insertions(+) diff --git a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf index 4b263965ed90..4492ee26caae 100644 --- a/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf +++ b/UefiCpuPkg/Library/CpuTimerLib/BaseCpuTimerLib.inf @@ -22,6 +22,9 @@ [Sources.IA32, Sources.X64] Ia32X64/CpuTimerLib.c Ia32X64/BaseCpuTimerLib.c +[Sources.RISCV64] + RiscV64/CpuTimerLib.c + [Packages] MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec diff --git a/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c new file mode 100644 index 000000000000..9c8efc0f3530 --- /dev/null +++ b/UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c @@ -0,0 +1,199 @@ +/** @file + RISC-V instance of Timer Library. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalRiscVTimerDelay ( + IN UINT32 Delay + ) +{ + UINT32 Ticks; + UINT32 Times; + + Times = Delay >> (RISCV_TIMER_COMPARE_BITS - 2); + Delay &= ((1 << (RISCV_TIMER_COMPARE_BITS - 2)) - 1); + do { + // + // The target timer count is calculated here + // + Ticks = RiscVReadTimer () + Delay; + Delay = 1 << (RISCV_TIMER_COMPARE_BITS - 2); + while (((Ticks - RiscVReadTimer ()) & (1 << (RISCV_TIMER_COMPARE_BITS - 1))) == 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalRiscVTimerDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + PcdGet64 (PcdCpuCoreCrystalClockFrequency) + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter. The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return (UINT64)RiscVReadTimer (); +} + +/**return + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter starts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end with + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartValue + is less than EndValue, then the performance counter counts up. If StartValue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a StartValue + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with before + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue != NULL) { + *StartValue = 0; + } + + if (EndValue != NULL) { + *EndValue = 32 - 1; + } + + return PcdGet64 (PcdCpuCoreCrystalClockFrequency); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance counter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 NanoSeconds; + UINT32 Remainder; + + // + // Ticks + // Time = --------- x 1,000,000,000 + // Frequency + // + NanoSeconds = MultU64x32 (DivU64x32Remainder (Ticks, PcdGet64 (PcdCpuCoreCrystalClockFrequency), &Remainder), 1000000000u); + + // + // Frequency < 0x100000000, so Remainder < 0x100000000, then (Remainder * 1,000,000,000) + // will not overflow 64-bit. + // + NanoSeconds += DivU64x32 (MultU64x32 ((UINT64)Remainder, 1000000000u), PcdGet64 (PcdCpuCoreCrystalClockFrequency)); + + return NanoSeconds; +} -- 2.38.0