From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oa1-f49.google.com (mail-oa1-f49.google.com [209.85.160.49]) by mx.groups.io with SMTP id smtpd.web09.9641.1665766186172946011 for ; Fri, 14 Oct 2022 09:49:46 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=W4cCCmTc; spf=pass (domain: ventanamicro.com, ip: 209.85.160.49, mailfrom: sunilvl@ventanamicro.com) Received: by mail-oa1-f49.google.com with SMTP id 586e51a60fabf-132fb4fd495so6482440fac.12 for ; Fri, 14 Oct 2022 09:49:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AS0de70Aof+Biv3CFMbNN9bquEZL6ugp5+9IdT8bofI=; b=W4cCCmTcGCNx4cj2HlFa0TFLsvm7AZMU8i1Rgb6KI3NdJ9XdVruZNuX+IpARCKifCd A2AykTjDskxzwNq5AbxYqo2LDrEWvAKDOFi8OHXiCyCi7tJiJwMh7QtEx7MZSoiAZuMg Vohj1cvPzIM/dOrCXSPamIBRlhgVkRklp5+PFmrh2kEB5ueHjEPaWiXqC/L63NeXDQxx PWx6+RQmclGJmRvmXpvdKc+JzRstBkra/Naj5Xfe8qTZTBl2US5r+DxdJWm18p6Kyw2u q/eHZxDd+IWExPjpBcwz9TmEkvbqgrF3vptAuZ0AdIiVeOknPNkpXyvY1Z7SKp4VGrVj +FkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AS0de70Aof+Biv3CFMbNN9bquEZL6ugp5+9IdT8bofI=; b=jTEjbhn1Gku0VfE4ObpOY0tEWdkjJm2/gQpcGK6n1D5I8NGnCPCKwegJDxFkOJsTH3 c9Eoc3hmwA1kEOcADJNowKj4eFgqPnymE6DfXJ4qHg4O9p0fv5l2WruPIpdL4pJgvB+Z imF7W+d2gQ47nNv/LQ1/NzCxyaB2JbnG81rBiD7iopbuzPE7EaxiinAa5QYvGydfShts ava96++/oi2YwusKgzr+sLkG1Jgm2ZkmiYCglIWZoAnCPPTyqDEXQwcYq2iF7LeMXtrR YsqPau2Fwhm5+OX85JlIPFtB2Fy+X7cbaf8X7cwOWfltsxpF4NICT57YVLMyYV9hZZVO rm9Q== X-Gm-Message-State: ACrzQf2SWraPCRc3J4vT03HZ233JhaP45bdbwDmjsI12Fa99sfgH+UqP JKowBaUbWp0Zt3nE6aTNH+YL+a1Dlh5irA== X-Google-Smtp-Source: AMsMyM74k3O8l9T04RWxL1bg+71V9YOqH2VwV98xDv9xrKAOxpyNgBYpJc/66QFsAOnAhIMoOE58MQ== X-Received: by 2002:a17:90b:38ca:b0:20d:a0e7:af33 with SMTP id nn10-20020a17090b38ca00b0020da0e7af33mr12609107pjb.154.1665766174142; Fri, 14 Oct 2022 09:49:34 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.13.138]) by smtp.gmail.com with ESMTPSA id f3-20020a62db03000000b0056265011136sm1963368pfg.112.2022.10.14.09.49.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 09:49:33 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer Subject: [edk2-staging/RiscV64QemuVirt PATCH V4 19/34] UefiCpuPkg/CpuDxe: Add RISCV_EFI_BOOT_PROTOCOL support Date: Fri, 14 Oct 2022 22:18:21 +0530 Message-Id: <20221014164836.1513036-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221014164836.1513036-1-sunilvl@ventanamicro.com> References: <20221014164836.1513036-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add the support for this protocol which is defined in the spec: https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_UEFI_PROTOCOL-spec.pdf Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Signed-off-by: Sunil V L --- UefiCpuPkg/UefiCpuPkg.dsc | 12 ++-- UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 60 +++++++++++++++++++- 3 files changed, 68 insertions(+), 7 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index f694b3a77c2e..6ea90507e36f 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -122,9 +122,13 @@ [Components] UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf - -[Components.IA32, Components.X64] UefiCpuPkg/CpuDxe/CpuDxe.inf + UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +!if $(TOOL_CHAIN_TAG) != "XCODE5" + UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf +!endif + +[Components.IA32, Components.X64] UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf { NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -141,10 +145,6 @@ [Components.IA32, Components.X64] UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf - UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf -!if $(TOOL_CHAIN_TAG) != "XCODE5" - UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf -!endif UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 235100d86274..b16b640946c6 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -74,6 +74,9 @@ [Protocols] gEfiMpServiceProtocolGuid ## PRODUCES gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES +[Protocols.RISCV64] + gRiscVEfiBootProtocolGuid ## PRODUCES + [Guids] gIdleLoopEventGuid ## CONSUMES ## Event gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ## SystemTable diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c index 9f557b776a09..7551e0653603 100644 --- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -2,6 +2,7 @@ RISC-V CPU DXE driver. Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -14,6 +15,39 @@ // STATIC BOOLEAN mInterruptState = FALSE; STATIC EFI_HANDLE mCpuHandle = NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +/** + Get the boot hartid + + @param This Protocol instance structure + @param BootHartId Pointer to the Boot Hart ID variable + + @retval EFI_SUCCESS If BootHartId is returned + @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is not + a valid RISCV_EFI_BOOT_PROTOCOL instance. + +**/ +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if ((This != &gRiscvBootProtocol) || (BootHartId == NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId = mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; EFI_CPU_ARCH_PROTOCOL gCpu = { CpuFlushCpuDataCache, @@ -285,14 +319,38 @@ InitializeCpu ( ) { EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; - InitializeCpuExceptionHandlers(NULL); + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext != NULL); + if (FirmwareContext == NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_CONTEXT\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__, FirmwareContext)); + + mBootHartId = FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__, mBootHartId)); + + InitializeCpuExceptionHandlers (NULL); // // Make sure interrupts are disabled // DisableInterrupts (); + // + // Install Boot protocol + // + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + ASSERT_EFI_ERROR (Status); + // // Install CPU Architectural Protocol // -- 2.38.0