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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT033.mail.protection.outlook.com (10.13.172.221) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5746.16 via Frontend Transport; Wed, 19 Oct 2022 04:34:32 +0000 Received: from TPE-L1-ABNCHANG.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Tue, 18 Oct 2022 23:34:14 -0500 From: "Chang, Abner" To: CC: Ray Ni , Michael D Kinney , Sunil V L , Abdul Lateef Attar , Leif Lindholm , Abdul Lateef Attar , Ray Ni Subject: [tianocore-docs][PATCH V3 2/2] edk II C Coding Standard: Updates 4.2 and 4.3 sections Date: Wed, 19 Oct 2022 12:33:52 +0800 Message-ID: <20221019043352.211-1-abner.chang@amd.com> X-Mailer: git-send-email 2.37.1.windows.1 MIME-Version: 1.0 Return-Path: Abner.Chang@amd.com X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT033:EE_|CO6PR12MB5490:EE_ X-MS-Office365-Filtering-Correlation-Id: e4ce5bff-d2b2-41c9-9554-08dab18b37ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Oct 2022 04:34:32.0265 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e4ce5bff-d2b2-41c9-9554-08dab18b37ce X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT033.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR12MB5490 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain From: Abner Chang Updates 4.2 Directory names and 4.3 file names for the guidelines of module directory and file naming. PR: https://github.com/tianocore-docs/edk2-CCodingStandardsSpecification/pu= ll/2/files Signed-off-by: Abner Chang Cc: Ray Ni Cc: Michael D Kinney Cc: Sunil V L Cc: Abdul Lateef Attar Cc: Leif Lindholm Acked-by: Sunil V L Reviewed-by: Abdul Lateef Attar Reviewed-by: Ray Ni --- 4_naming_conventions/42_directory_names.md | 101 +++++++++++++++++++ 4_naming_conventions/43_file_names.md | 109 ++++++++++++++++++++- 2 files changed, 209 insertions(+), 1 deletion(-) diff --git a/4_naming_conventions/42_directory_names.md b/4_naming_conventi= ons/42_directory_names.md index 766ccb1..c590f64 100644 --- a/4_naming_conventions/42_directory_names.md +++ b/4_naming_conventions/42_directory_names.md @@ -2,6 +2,7 @@ 4.2 Directory Names =20 Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2022, Intel Corporation. All rights reserved.
=20 Redistribution and use in source (original document form) and 'compiled' forms (converted to PDF, epub, HTML and other formats) with or without @@ -28,3 +29,103 @@ ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. =20 --> + +## 4.2 Directory Names +Below sections are the directory naming guidelines for EDK II modules. The= guidelines are not +just considering the uniformity of directory naming, but they also provide= the flexibility of +directory name construction for the scenario of different EDK II module de= signs; such as the +support for multiple processor architectures and vendors. It may require f= urther discussions +between EDK II maintainers and contributors in order to determine the best= naming of the EDK II +module directory. + +#### 4.2.1 EDKII package directory + +``` +Pkg + + REQUIRED * +``` + +#### 4.2.2 EDKII Module directory + +* The guideline below is applied to all CPU architectures support, specifi= c CPU architecture and vendors support, or the implementation is shared by = certain CPU archs: +``` +[[]] + or +[/[/]] + + REQUIRED * + REQUIRED Base, Sec, Pei, Dxe, DxeRuntime, Mm, Standal= oneMm, Smm, + Uefi. + OPTIONAL The is represented with a BNF, + ::=3D'Ia32' | 'X64' | 'Arm' | 'AArch6= 4' | 'RiscV64' | + 'LoongArch64' | 'Ebc' =20 + ::=3D []* + =20 + Example: Ia32X64Arm or RiscV64LoongArch64 + =20 + OPTIONAL * + +Example: + - SmbiosDxe/ + - CpuDxe/ # First implementation of CpuDxe. + - CpuDxeIa32X64Amd/ # Ia32 and X64 AMD specific implementation= . + - CpuDxe/RiscV64/ # RiscV64 specific implementation. + / # Common files for the RiscV64 and other a= rchs. + - CpuDxe/Ia32X64/Amd/ # Ia32 and X64 AMD specific implementation= . + / # Common files for Ia32 and X64 archs. + /ArmAArch64/ # Arm and AArch64 implementation of CpuDxe= . + / # Common files for the Arm, AArch64, Ia32 = and X64. +``` + +* If the implementation does not have any shared code between phases (e.g. +MdeModulePkg/Universal/PCD). The guideline below is applied to all CPU arc= hitectures support, specific CPU architecture and vendors support, or the i= mplementation is shared by certain CPU architectures: + +``` +/[/[/]] + + REQUIRED * + REQUIRED Base, Sec, Pei, Dxe, DxeRuntime, Mm, Standal= oneMm, Smm, + Uefi. + OPTIONAL The is represented with a BNF, + ::=3D'Ia32' | 'X64' | 'Arm' | 'AArch6= 4' | 'RiscV64' | + 'LoongArch64' | 'Ebc' + ::=3D []* + + Example: Ia32X64Arm or RiscV64LoongArch64 + OPTIONAL * +Example: + Pcd/Dxe/ +``` + +#### 4.2.2 EDKII Library directory +``` +[[]][] + or +[]/[[/]] + + REQUIRED Base, Sec, Pei, Dxe, DxeRuntime, Mm, + StandaloneMm, Smm, Uefi. + OPTIONAL The is represented with a B= NF, + ::=3D'Ia32' | 'X64' | 'Arm' | = 'AArch64' | 'RiscV64' | + 'LoongArch64' | 'Ebc' + ::=3D []* + + Example: Ia32X64Arm or RiscV64LoongAr= ch64 + OPTIONAL * + REQUIRED * + OPTIONAL * (Typically name of PPI, Protocol, L= ibraryClass + that the implementation is layered = on top of). + +Example: + - BaseXApicLib/ + - SmmIa32X64AmdSmmCpuFeaturesLib/ + - SmmArmAArch64SmmCpuFeaturesLib/ + - BaseMpInitLib/RiscV64/ # RiscV64 specific implementation. + /Ia32X64/ # Ia32 and X64 specific implementation. + /Ia32X64/Amd # Ia32 and X64 AMD specific implementat= ion. + /ArmAArch64/ # Arm and AAch64 specific implementatio= n. + /LoongArch64/ # LoongArch64 specific implementation. + / # Common files for RiscV64, Ia32, X64, = Arm, AArch64 and + LoongArch64. +``` diff --git a/4_naming_conventions/43_file_names.md b/4_naming_conventions/4= 3_file_names.md index 13e0c63..226f046 100644 --- a/4_naming_conventions/43_file_names.md +++ b/4_naming_conventions/43_file_names.md @@ -1,7 +1,8 @@