From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f53.google.com (mail-pj1-f53.google.com [209.85.216.53]) by mx.groups.io with SMTP id smtpd.web11.8318.1667136534610489128 for ; Sun, 30 Oct 2022 06:28:54 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Ibn0TjWN; spf=pass (domain: ventanamicro.com, ip: 209.85.216.53, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pj1-f53.google.com with SMTP id u8-20020a17090a5e4800b002106dcdd4a0so13778239pji.1 for ; Sun, 30 Oct 2022 06:28:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tUik/4PCFuqcF7t3bEZ83CqtKnInu2mCNlKjmSl3BZo=; b=Ibn0TjWNNCUrnD7iuQ2qcogSAdegGy+dQy9TP4V1e4pbFBx3A7A9xLdzIGcm28T09T hbaszGejQsiyTgz6164CZ8W1L++FCM/JbXm7Ujg//aKqYwt1E74hRIqrSw/EVFzwHR1w +v8nYfoxjzZo8bRmOdhYVzzsO5KwEJRzkdDLCxZuYYyC8kDhh3TEyansuNFF0O4GsN3H vP1rrSFlbzx/wprqk/13eU6WmtwdcW7yMoiIn71t/KPhkqqVe5HhsWogIpj6Lqs8Njhh 3+OwIenGSSzAxoQvDax65owdItw4Q+qrySfMDVQVPrXZjq7bAKM+ruRKshKIuSirGyu+ tQQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tUik/4PCFuqcF7t3bEZ83CqtKnInu2mCNlKjmSl3BZo=; b=zKtVvnJtf1PlzR86mrg2pLxlG1U2sBmgi9JoNrTAsBZ0vRtL5WWf48QVLGqJFzy2OL 1+lkSzLaW4hvvlJwtIEf27S+jE5FZg6EIXyA2YrNEUh4++efJSXaRmll78xKgS+uuQWK qTTHsMdplLfXv6wocXNaJFQA293TfVoK44zCHlrwbeJlYIkG9TBY9dIJXVENLQoMw6mB +lFUAS8aYc94cNRH+vaq740i4LEiMGX1/gvlvOSgAh86cJH5QcSPyjbZV9va8YrG1zXl envkXLpYXwxRsvd85PXt5E/hwMAv5WdOWc/zUOTgqylF9+8xEMvq/YcG9ty6AoNa5xmM YXqQ== X-Gm-Message-State: ACrzQf2PglDwRxwenFXZjtfHwPshCgUXagNsUJRExWFSC+ZMcCZyTeLp XfSR+G72YmReiUnQUZ/emXEzIOyB48ZTFA== X-Google-Smtp-Source: AMsMyM5khPr4iH3cIZgy1PW52Fu9WQVd+rqkpqN0C4sSiTPUHdtbNcREphtUUchPTiC/3py/NEwnXA== X-Received: by 2002:a17:902:d490:b0:186:c544:8ac7 with SMTP id c16-20020a170902d49000b00186c5448ac7mr9309930plg.158.1667136533863; Sun, 30 Oct 2022 06:28:53 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.28.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:28:53 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu , Abner Chang Subject: [edk2-staging/RiscV64QemuVirt PATCH V5 01/30] MdePkg/Register: Add register definition header files for RISC-V Date: Sun, 30 Oct 2022 18:58:13 +0530 Message-Id: <20221030132842.54077-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Sunil V L Acked-by: Abner Chang --- MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 119 ++++++++++++++++++++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 ++++ 2 files changed, 144 insertions(+) diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h new file mode 100644 index 000000000000..5c2989b797bf --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h @@ -0,0 +1,119 @@ +/** @file + RISC-V CSR encodings + + Copyright (c) 2019, Western Digital Corporation or its affiliates. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_ENCODING_H_ +#define RISCV_ENCODING_H_ + +#define MSTATUS_SIE 0x00000002UL +#define MSTATUS_MIE 0x00000008UL +#define MSTATUS_SPIE_SHIFT 5 +#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) +#define MSTATUS_UBE 0x00000040UL +#define MSTATUS_MPIE 0x00000080UL +#define MSTATUS_SPP_SHIFT 8 +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) +#define MSTATUS_MPP_SHIFT 11 +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) + +#define SSTATUS_SIE MSTATUS_SIE +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT +#define SSTATUS_SPIE MSTATUS_SPIE +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT +#define SSTATUS_SPP MSTATUS_SPP + +#define IRQ_S_SOFT 1 +#define IRQ_VS_SOFT 2 +#define IRQ_M_SOFT 3 +#define IRQ_S_TIMER 5 +#define IRQ_VS_TIMER 6 +#define IRQ_M_TIMER 7 +#define IRQ_S_EXT 9 +#define IRQ_VS_EXT 10 +#define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_PMU_OVF 13 + +#define MIP_SSIP (1UL << IRQ_S_SOFT) +#define MIP_VSSIP (1UL << IRQ_VS_SOFT) +#define MIP_MSIP (1UL << IRQ_M_SOFT) +#define MIP_STIP (1UL << IRQ_S_TIMER) +#define MIP_VSTIP (1UL << IRQ_VS_TIMER) +#define MIP_MTIP (1UL << IRQ_M_TIMER) +#define MIP_SEIP (1UL << IRQ_S_EXT) +#define MIP_VSEIP (1UL << IRQ_VS_EXT) +#define MIP_MEIP (1UL << IRQ_M_EXT) +#define MIP_SGEIP (1UL << IRQ_S_GEXT) +#define MIP_LCOFIP (1UL << IRQ_PMU_OVF) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP + +#define PRV_U 0UL +#define PRV_S 1UL +#define PRV_M 3UL + +#define SATP64_MODE 0xF000000000000000ULL +#define SATP64_ASID 0x0FFFF00000000000ULL +#define SATP64_PPN 0x00000FFFFFFFFFFFULL + +#define SATP_MODE_OFF 0UL +#define SATP_MODE_SV32 1UL +#define SATP_MODE_SV39 8UL +#define SATP_MODE_SV48 9UL +#define SATP_MODE_SV57 10UL +#define SATP_MODE_SV64 11UL + +#define SATP_MODE SATP64_MODE + +/* User Counters/Timers */ +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 + +/* Supervisor Trap Setup */ +#define CSR_SSTATUS 0x100 +#define CSR_SEDELEG 0x102 +#define CSR_SIDELEG 0x103 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 + +/* Supervisor Configuration */ +#define CSR_SENVCFG 0x10a + +/* Supervisor Trap Handling */ +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_STVAL 0x143 +#define CSR_SIP 0x144 + +/* Supervisor Protection and Translation */ +#define CSR_SATP 0x180 + +/* Trap/Exception Causes */ +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FETCH_ACCESS 0x1 +#define CAUSE_ILLEGAL_INSTRUCTION 0x2 +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_LOAD_ACCESS 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_STORE_ACCESS 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_VIRTUAL_SUPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_FETCH_GUEST_PAGE_FAULT 0x14 +#define CAUSE_LOAD_GUEST_PAGE_FAULT 0x15 +#define CAUSE_VIRTUAL_INST_FAULT 0x16 +#define CAUSE_STORE_GUEST_PAGE_FAULT 0x17 + +#endif diff --git a/MdePkg/Include/Register/RiscV64/RiscVImpl.h b/MdePkg/Include/Register/RiscV64/RiscVImpl.h new file mode 100644 index 000000000000..ee5c2ba60377 --- /dev/null +++ b/MdePkg/Include/Register/RiscV64/RiscVImpl.h @@ -0,0 +1,25 @@ +/** @file + RISC-V package definitions. + + Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef RISCV_IMPL_H_ +#define RISCV_IMPL_H_ + +#include + +#define _ASM_FUNC(Name, Section) \ + .global Name ; \ + .section #Section, "ax" ; \ + .type Name, %function ; \ + .p2align 2 ; \ + Name: + +#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name) +#define RISCV_TIMER_COMPARE_BITS 32 + +#endif -- 2.38.0