[edk2-staging/RiscV64QemuVirt PATCH V5 19/30] UefiCpuPkg/CpuDxe: Add RISCV_EFI_BOOT_PROTOCOL support

["Sunil V L" <sunilvl@ventanamicro.com>]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076

RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL.
Add the support for this protocol which is defined in the spec:
https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_UEFI_PROTOCOL-spec.pdf

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Daniel Schaefer <git@danielschaefer.me>
Cc: Abner Chang <abner.chang@amd.com>
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@amd.com>
---
 UefiCpuPkg/UefiCpuPkg.dsc          | 12 ++--
 UefiCpuPkg/CpuDxe/CpuDxe.inf       |  3 +
 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 66 ++++++++++++++++++--
 3 files changed, 71 insertions(+), 10 deletions(-)

diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc
index 0e1a99ddc09f..aaf761fdcf48 100644
--- a/UefiCpuPkg/UefiCpuPkg.dsc
+++ b/UefiCpuPkg/UefiCpuPkg.dsc
@@ -125,9 +125,13 @@ [Components]
   UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf
   UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf
   UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf
-
-[Components.IA32, Components.X64]
   UefiCpuPkg/CpuDxe/CpuDxe.inf
+  UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
+!if $(TOOL_CHAIN_TAG) != "XCODE5"
+  UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
+!endif
+
+[Components.IA32, Components.X64]
   UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf {
     <LibraryClasses>
       NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
@@ -144,10 +148,6 @@ [Components.IA32, Components.X64]
   UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
   UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf
   UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf
-  UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf
-!if $(TOOL_CHAIN_TAG) != "XCODE5"
-  UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf
-!endif
   UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf
   UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
   UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf
diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index eddc86a38965..857b84ac3122 100644
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -74,6 +74,9 @@ [Protocols]
   gEfiMpServiceProtocolGuid                     ## PRODUCES
   gEfiSmmBase2ProtocolGuid                      ## SOMETIMES_CONSUMES
 
+[Protocols.RISCV64]
+  gRiscVEfiBootProtocolGuid                     ## PRODUCES
+
 [Guids]
   gIdleLoopEventGuid                            ## CONSUMES           ## Event
   gEfiVectorHandoffTableGuid                    ## SOMETIMES_CONSUMES ## SystemTable
diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
index 9f557b776a09..7551e0653603 100644
--- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
+++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c
@@ -2,6 +2,7 @@
   RISC-V CPU DXE driver.
 
   Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+  Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.<BR>
 
   SPDX-License-Identifier: BSD-2-Clause-Patent
 
@@ -12,8 +13,41 @@
 //
 // Global Variables
 //
-STATIC BOOLEAN     mInterruptState = FALSE;
-STATIC EFI_HANDLE  mCpuHandle      = NULL;
+STATIC BOOLEAN           mInterruptState = FALSE;
+STATIC EFI_HANDLE        mCpuHandle      = NULL;
+STATIC UINTN             mBootHartId;
+RISCV_EFI_BOOT_PROTOCOL  gRiscvBootProtocol;
+
+/**
+  Get the boot hartid
+
+  @param  This                   Protocol instance structure
+  @param  BootHartId             Pointer to the Boot Hart ID variable
+
+  @retval EFI_SUCCESS            If BootHartId is returned
+  @retval EFI_INVALID_PARAMETER  Either "BootHartId" is NULL or "This" is not
+                                 a valid RISCV_EFI_BOOT_PROTOCOL instance.
+
+**/
+EFI_STATUS
+EFIAPI
+RiscvGetBootHartId (
+  IN RISCV_EFI_BOOT_PROTOCOL  *This,
+  OUT UINTN                   *BootHartId
+  )
+{
+  if ((This != &gRiscvBootProtocol) || (BootHartId == NULL)) {
+    return EFI_INVALID_PARAMETER;
+  }
+
+  *BootHartId = mBootHartId;
+  return EFI_SUCCESS;
+}
+
+RISCV_EFI_BOOT_PROTOCOL  gRiscvBootProtocol = {
+  RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION,
+  RiscvGetBootHartId
+};
 
 EFI_CPU_ARCH_PROTOCOL  gCpu = {
   CpuFlushCpuDataCache,
@@ -284,15 +318,39 @@ InitializeCpu (
   IN EFI_SYSTEM_TABLE  *SystemTable
   )
 {
-  EFI_STATUS  Status;
+  EFI_STATUS                  Status;
+  EFI_RISCV_FIRMWARE_CONTEXT  *FirmwareContext;
 
-  InitializeCpuExceptionHandlers(NULL);
+  GetFirmwareContextPointer (&FirmwareContext);
+  ASSERT (FirmwareContext != NULL);
+  if (FirmwareContext == NULL) {
+    DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_CONTEXT\n"));
+    return EFI_NOT_FOUND;
+  }
+
+  DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__, FirmwareContext));
+
+  mBootHartId = FirmwareContext->BootHartId;
+  DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__, mBootHartId));
+
+  InitializeCpuExceptionHandlers (NULL);
 
   //
   // Make sure interrupts are disabled
   //
   DisableInterrupts ();
 
+  //
+  // Install Boot protocol
+  //
+  Status = gBS->InstallProtocolInterface (
+                  &ImageHandle,
+                  &gRiscVEfiBootProtocolGuid,
+                  EFI_NATIVE_INTERFACE,
+                  &gRiscvBootProtocol
+                  );
+  ASSERT_EFI_ERROR (Status);
+
   //
   // Install CPU Architectural Protocol
   //
-- 
2.38.0