From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f176.google.com (mail-pg1-f176.google.com [209.85.215.176]) by mx.groups.io with SMTP id smtpd.web11.8328.1667136581208830893 for ; Sun, 30 Oct 2022 06:29:41 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=KNF8sYJl; spf=pass (domain: ventanamicro.com, ip: 209.85.215.176, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pg1-f176.google.com with SMTP id f193so8671903pgc.0 for ; Sun, 30 Oct 2022 06:29:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rakt/5c45wkE5r0dxVkV9rpQo47B6U5h62TtvxfQdEQ=; b=KNF8sYJldu7RDNctNEFdWReRJYiYcFBxgmZib+QWZTta006XQkdy8jdGvNAMEDXxoM kWNm95pMVdVrga4M0KXrgUpiU3ay3lSxpr9NmCRZKn1gUPgRWqu/jCsovZiI7dLHFB/I xAVwui1Pa0XXeEDgfA8nd+CnhXPXzzeKpf3H+fUR54CmCJbKP4GCFUH5jd8K5xXDZmnx LukPnq77PmIJ7ZN1zGPsFR9HtbQAUZ5Z4cCd5/jcSB2LpepcOdrqe0lTQ6hV8aAiGdSA x9FNf4DFkqZhzyzDUclJHs6dZh7DkFu4pxDGTicDduHaxgqBJzAwmxe0xAAYWoJnnvzG y9jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rakt/5c45wkE5r0dxVkV9rpQo47B6U5h62TtvxfQdEQ=; b=FHDiqu7ABfkMQscHzAoXqNNsjJQXCe39TrbMppyeMTwY+tsKwXH29kXk1rHPIh/brN 7+sporgJBfG4wKY14NOyUuBKwAd+AMuUCMFfHWdf4xAgQwqCayINWEZzxYC4SEHJFjB+ Jx7RAFVMM1aPpV/h0lFJ66XaWigGKhuWbxF9aVVwIibSFR3bWKnGhNEKi7NqDgPQ2Afh GYCkP4b1BLirvp8Wz1IW6Tsi27EDCUWEO23VDdngATKnLkPXuk9EzJPvF/f6suyI6O3j B2L0fdmK+C69cVREJolz46/XDanrRBEgUwwnY2eQZ1NxaveGSKO4KeLrLMrxj9QBJabr E88A== X-Gm-Message-State: ACrzQf280V/jaSOsGcBcvDHkuh3G9Aw6280Cl5xdAUnZewTZWmR0jDMx 0GzMV8FlyxqpmH2KfUQ8qjv0XUmaOeX7rg== X-Google-Smtp-Source: AMsMyM6eOoIp6NbteoSsDECMUKV3o5B1EGPJm0fg1B8a9ycCg7LRVSZ0uSHgEDTCvLHPNmfXHZlc2A== X-Received: by 2002:a63:de0e:0:b0:46f:23c6:e7d9 with SMTP id f14-20020a63de0e000000b0046f23c6e7d9mr8197840pgg.68.1667136580510; Sun, 30 Oct 2022 06:29:40 -0700 (PDT) Return-Path: Received: from localhost.localdomain ([49.206.12.236]) by smtp.gmail.com with ESMTPSA id r10-20020aa79eca000000b0056b6a22d6c9sm2612330pfq.212.2022.10.30.06.29.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Oct 2022 06:29:40 -0700 (PDT) From: "Sunil V L" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Rahul Kumar , Daniel Schaefer , Abner Chang Subject: [edk2-staging/RiscV64QemuVirt PATCH V5 19/30] UefiCpuPkg/CpuDxe: Add RISCV_EFI_BOOT_PROTOCOL support Date: Sun, 30 Oct 2022 18:58:31 +0530 Message-Id: <20221030132842.54077-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221030132842.54077-1-sunilvl@ventanamicro.com> References: <20221030132842.54077-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V UEFI platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add the support for this protocol which is defined in the spec: https://github.com/riscv-non-isa/riscv-uefi/releases/download/1.0.0/RISCV_UEFI_PROTOCOL-spec.pdf Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Daniel Schaefer Cc: Abner Chang Signed-off-by: Sunil V L Acked-by: Abner Chang --- UefiCpuPkg/UefiCpuPkg.dsc | 12 ++-- UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 66 ++++++++++++++++++-- 3 files changed, 71 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 0e1a99ddc09f..aaf761fdcf48 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -125,9 +125,13 @@ [Components] UefiCpuPkg/Library/CpuCacheInfoLib/PeiCpuCacheInfoLib.inf UefiCpuPkg/Library/CpuCacheInfoLib/DxeCpuCacheInfoLib.inf UefiCpuPkg/MicrocodeMeasurementDxe/MicrocodeMeasurementDxe.inf - -[Components.IA32, Components.X64] UefiCpuPkg/CpuDxe/CpuDxe.inf + UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf +!if $(TOOL_CHAIN_TAG) != "XCODE5" + UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf +!endif + +[Components.IA32, Components.X64] UefiCpuPkg/CpuFeatures/CpuFeaturesPei.inf { NULL|UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf @@ -144,10 +148,6 @@ [Components.IA32, Components.X64] UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.inf - UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.inf -!if $(TOOL_CHAIN_TAG) != "XCODE5" - UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.inf -!endif UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHandlerLib.inf diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index eddc86a38965..857b84ac3122 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -74,6 +74,9 @@ [Protocols] gEfiMpServiceProtocolGuid ## PRODUCES gEfiSmmBase2ProtocolGuid ## SOMETIMES_CONSUMES +[Protocols.RISCV64] + gRiscVEfiBootProtocolGuid ## PRODUCES + [Guids] gIdleLoopEventGuid ## CONSUMES ## Event gEfiVectorHandoffTableGuid ## SOMETIMES_CONSUMES ## SystemTable diff --git a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c index 9f557b776a09..7551e0653603 100644 --- a/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c +++ b/UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c @@ -2,6 +2,7 @@ RISC-V CPU DXE driver. Copyright (c) 2016 - 2022, Hewlett Packard Enterprise Development LP. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -12,8 +13,41 @@ // // Global Variables // -STATIC BOOLEAN mInterruptState = FALSE; -STATIC EFI_HANDLE mCpuHandle = NULL; +STATIC BOOLEAN mInterruptState = FALSE; +STATIC EFI_HANDLE mCpuHandle = NULL; +STATIC UINTN mBootHartId; +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol; + +/** + Get the boot hartid + + @param This Protocol instance structure + @param BootHartId Pointer to the Boot Hart ID variable + + @retval EFI_SUCCESS If BootHartId is returned + @retval EFI_INVALID_PARAMETER Either "BootHartId" is NULL or "This" is not + a valid RISCV_EFI_BOOT_PROTOCOL instance. + +**/ +EFI_STATUS +EFIAPI +RiscvGetBootHartId ( + IN RISCV_EFI_BOOT_PROTOCOL *This, + OUT UINTN *BootHartId + ) +{ + if ((This != &gRiscvBootProtocol) || (BootHartId == NULL)) { + return EFI_INVALID_PARAMETER; + } + + *BootHartId = mBootHartId; + return EFI_SUCCESS; +} + +RISCV_EFI_BOOT_PROTOCOL gRiscvBootProtocol = { + RISCV_EFI_BOOT_PROTOCOL_LATEST_VERSION, + RiscvGetBootHartId +}; EFI_CPU_ARCH_PROTOCOL gCpu = { CpuFlushCpuDataCache, @@ -284,15 +318,39 @@ InitializeCpu ( IN EFI_SYSTEM_TABLE *SystemTable ) { - EFI_STATUS Status; + EFI_STATUS Status; + EFI_RISCV_FIRMWARE_CONTEXT *FirmwareContext; - InitializeCpuExceptionHandlers(NULL); + GetFirmwareContextPointer (&FirmwareContext); + ASSERT (FirmwareContext != NULL); + if (FirmwareContext == NULL) { + DEBUG ((DEBUG_ERROR, "Failed to get the pointer of EFI_RISCV_FIRMWARE_CONTEXT\n")); + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO, " %a: Firmware Context is at 0x%x.\n", __FUNCTION__, FirmwareContext)); + + mBootHartId = FirmwareContext->BootHartId; + DEBUG ((DEBUG_INFO, " %a: mBootHartId = 0x%x.\n", __FUNCTION__, mBootHartId)); + + InitializeCpuExceptionHandlers (NULL); // // Make sure interrupts are disabled // DisableInterrupts (); + // + // Install Boot protocol + // + Status = gBS->InstallProtocolInterface ( + &ImageHandle, + &gRiscVEfiBootProtocolGuid, + EFI_NATIVE_INTERFACE, + &gRiscvBootProtocol + ); + ASSERT_EFI_ERROR (Status); + // // Install CPU Architectural Protocol // -- 2.38.0