From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.3084.1667368035767473787 for ; Tue, 01 Nov 2022 22:47:16 -0700 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=Gh+T1Ny/; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: chasel.chiu@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667368035; x=1698904035; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=0Sq7RtDbeeJGtkYmolK33Sf/P2fmW1Rj1fVcaIpindk=; b=Gh+T1Ny/jRZtrUwVtI/clOf4/VwDJxjpBChjI0kVm12/unK2MWhap6jF mOYewQL5YZQignfZaNaQBU6/A4aOzjXD6xdTr1vB8i/QtvTjpLhNRKA7A OMztaBMas/M1bX5L6jDtVHy4BVtHDBlaAe1gs3pdrP1vkeAbBbW5AZ2MG /vcJ/O4hr1nlM2a8It/9TdmVgLIYk2UlK7vxERVSZgMacGyvnq6hopUN2 SC+TXbqHgEhUwL61iJ3ccUS6WUu6pzmeHe8nznvzWg59Dfyb1qZ2qH2Sm OiMLDL809GGQt8YRYVp/GIJfJKhdn3oBV7gHH1QwupRWwSFf+zep+K5Qe Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="310423455" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="310423455" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 22:47:15 -0700 X-IronPort-AV: E=McAfee;i="6500,9779,10518"; a="879349602" X-IronPort-AV: E=Sophos;i="5.95,232,1661842800"; d="scan'208";a="879349602" Received: from cchiu4-mobl.gar.corp.intel.com ([10.209.113.8]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Nov 2022 22:47:14 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng Subject: [PATCH v2] IntelFsp2Pkg: FSP should support input UPD as NULL. Date: Tue, 1 Nov 2022 22:46:27 -0700 Message-Id: <20221102054627.1496-1-chasel.chiu@intel.com> X-Mailer: git-send-email 2.35.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4114 FSP specification supports input UPD as NULL cases which FSP will use built-in UPD region instead. FSP should not return INVALID_PARAMETER in such cases. In FSP-T entry point case, the valid FSP-T UPD region pointer will be passed to platform FSP code to consume. In FSP-M and FSP-S cases, valid UPD pointer will be decided when updating corresponding pointer field in FspGlobalData. Cc: Nate DeSimone Cc: Star Zeng Signed-off-by: Chasel Chiu --- IntelFsp2Pkg/FspSecCore/SecFspApiChk.c | 12 ++++++++++-- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 73 ++++++++++++++++++++++= +++++++++++++++++++++++++++++++++------------------ IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 40 ++++++++++++++++++++++= ++++-------------- 3 files changed, 91 insertions(+), 34 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c b/IntelFsp2Pkg/FspSecCo= re/SecFspApiChk.c index a44fbf2a50..5f59938518 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c +++ b/IntelFsp2Pkg/FspSecCore/SecFspApiChk.c @@ -44,6 +44,8 @@ FspApiCallingCheck ( //=0D if (((UINTN)FspData !=3D MAX_ADDRESS) && ((UINTN)FspData !=3D MAX_UINT= 32)) {=0D Status =3D EFI_UNSUPPORTED;=0D + } else if (ApiParam =3D=3D NULL) {=0D + Status =3D EFI_SUCCESS;=0D } else if (EFI_ERROR (FspUpdSignatureCheck (ApiIdx, ApiParam))) {=0D Status =3D EFI_INVALID_PARAMETER;=0D }=0D @@ -67,9 +69,13 @@ FspApiCallingCheck ( } else {=0D if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) {=0D Status =3D EFI_UNSUPPORTED;=0D - } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex, = ApiParam))) {=0D - Status =3D EFI_INVALID_PARAMETER;=0D } else if (ApiIdx =3D=3D FspSiliconInitApiIndex) {=0D + if (ApiParam =3D=3D NULL) {=0D + Status =3D EFI_SUCCESS;=0D + } else if (EFI_ERROR (FspUpdSignatureCheck (FspSiliconInitApiIndex= , ApiParam))) {=0D + Status =3D EFI_INVALID_PARAMETER;=0D + }=0D +=0D //=0D // Reset MultiPhase NumberOfPhases to zero=0D //=0D @@ -89,6 +95,8 @@ FspApiCallingCheck ( } else {=0D if (FspData->Signature !=3D FSP_GLOBAL_DATA_SIGNATURE) {=0D Status =3D EFI_UNSUPPORTED;=0D + } else if (ApiParam =3D=3D NULL) {=0D + Status =3D EFI_SUCCESS;=0D } else if (EFI_ERROR (FspUpdSignatureCheck (FspSmmInitApiIndex, ApiP= aram))) {=0D Status =3D EFI_INVALID_PARAMETER;=0D }=0D diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 61030a843b..73821ad22a 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -21,7 +21,7 @@ extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) ; Following functions will be provided in PlatformSecLib=0D ;=0D extern ASM_PFX(AsmGetFspBaseAddress)=0D -extern ASM_PFX(AsmGetFspInfoHeader)=0D +extern ASM_PFX(AsmGetFspInfoHeaderNoStack)=0D ;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation=0D extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation=0D extern ASM_PFX(SecCarInit)=0D @@ -160,6 +160,47 @@ endstruc RET_ESI_EXT mm7=0D %endmacro=0D =0D +%macro CALL_EDI 1=0D +=0D + mov edi, %%ReturnAddress=0D + jmp %1=0D +%%ReturnAddress:=0D +=0D +%endmacro=0D +=0D +%macro CALL_EBP 1=0D + mov ebp, %%ReturnAddress=0D + jmp %1=0D +%%ReturnAddress:=0D +%endmacro=0D +=0D +%macro RET_EBP 0=0D + jmp ebp ; restore EIP from EBP=0D +%endmacro=0D +=0D +;=0D +; Load UPD region pointer in ECX=0D +;=0D +global ASM_PFX(LoadUpdPointerToECX)=0D +ASM_PFX(LoadUpdPointerToECX):=0D + ;=0D + ; esp + 4 is input UPD parameter=0D + ; If esp + 4 is NULL the default UPD should be used=0D + ; ecx will be the UPD region that should be used=0D + ;=0D + mov ecx, dword [esp + 4]=0D + cmp ecx, 0=0D + jnz ParamValid=0D +=0D + ;=0D + ; Fall back to default UPD region=0D + ;=0D + CALL_EDI ASM_PFX(AsmGetFspInfoHeaderNoStack)=0D + mov ecx, DWORD [eax + 01Ch] ; Read FsptImageBaseAddress=0D + add ecx, DWORD [eax + 024h] ; Get Cfg Region base address =3D= FsptImageBaseAddress + CfgRegionOffset=0D +ParamValid:=0D + RET_EBP=0D +=0D ;=0D ; @todo: The strong/weak implementation does not work.=0D ; This needs to be reviewed later.=0D @@ -187,10 +228,9 @@ endstruc global ASM_PFX(LoadMicrocodeDefault)=0D ASM_PFX(LoadMicrocodeDefault):=0D ; Inputs:=0D - ; esp -> LoadMicrocodeParams pointer=0D + ; ecx -> UPD region contains LoadMicrocodeParams pointer=0D ; Register Usage:=0D - ; esp Preserved=0D - ; All others destroyed=0D + ; All are destroyed=0D ; Assumptions:=0D ; No memory available, stack is hard-coded and used for return addres= s=0D ; Executed by SBSP and NBSP=0D @@ -201,12 +241,9 @@ ASM_PFX(LoadMicrocodeDefault): ;=0D movd ebp, mm7=0D =0D + mov esp, ecx ; ECX has been assigned to UPD region=0D cmp esp, 0=0D jz ParamError=0D - mov eax, dword [esp + 4] ; Parameter pointer=0D - cmp eax, 0=0D - jz ParamError=0D - mov esp, eax=0D =0D ; skip loading Microcode if the MicrocodeCodeSize is zero=0D ; and report error if size is less than 2k=0D @@ -444,13 +481,15 @@ Done: Exit2:=0D jmp ebp=0D =0D -=0D +;=0D +; EstablishStackFsp: EDI should be preserved cross this function=0D +;=0D global ASM_PFX(EstablishStackFsp)=0D ASM_PFX(EstablishStackFsp):=0D ;=0D ; Save parameter pointer in edx=0D ;=0D - mov edx, dword [esp + 4]=0D + mov edx, ecx ; ECX has been assigned to UPD region=0D =0D ;=0D ; Enable FSP STACK=0D @@ -555,39 +594,37 @@ ASM_PFX(TempRamInitApi): SAVE_EAX=0D SAVE_EDX=0D =0D - ;=0D - ; Check Parameter=0D - ;=0D - mov eax, dword [esp + 4]=0D - cmp eax, 0=0D - mov eax, 80000002h=0D - jz TempRamInitExit=0D -=0D ;=0D ; Sec Platform Init=0D ;=0D + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D CALL_MMX ASM_PFX(SecPlatformInit)=0D cmp eax, 0=0D jnz TempRamInitExit=0D =0D ; Load microcode=0D LOAD_ESP=0D + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D CALL_MMX ASM_PFX(LoadMicrocodeDefault)=0D SXMMN xmm6, 3, eax ;Save microcode return status in ECX-S= LOT 3 in xmm6.=0D ;@note If return value eax is not 0, microcode did not load, but continu= e and attempt to boot.=0D =0D ; Call Sec CAR Init=0D LOAD_ESP=0D + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D CALL_MMX ASM_PFX(SecCarInit)=0D cmp eax, 0=0D jnz TempRamInitExit=0D =0D LOAD_ESP=0D + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param=0D + mov edi, ecx ; Save UPD param to EDI for later= code use=0D CALL_MMX ASM_PFX(EstablishStackFsp)=0D cmp eax, 0=0D jnz TempRamInitExit=0D =0D LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error f= rom ECX-SLOT 3 in xmm6.=0D + SXMMN xmm6, 3, edi ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 = in xmm6.=0D =0D TempRamInitExit:=0D mov bl, al ; save al data in bl=0D diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index 7dd89c531a..cdebe90fab 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -21,7 +21,7 @@ extern ASM_PFX(PcdGet32 (PcdFspReservedBufferSize)) ; Following functions will be provided in PlatformSecLib=0D ;=0D extern ASM_PFX(AsmGetFspBaseAddress)=0D -extern ASM_PFX(AsmGetFspInfoHeader)=0D +extern ASM_PFX(AsmGetFspInfoHeaderNoStack)=0D ;extern ASM_PFX(LoadMicrocode) ; @todo: needs a weak implementation=0D extern ASM_PFX(SecPlatformInit) ; @todo: needs a weak implementation=0D extern ASM_PFX(SecCarInit)=0D @@ -87,6 +87,14 @@ struc LoadMicrocodeParamsFsp24 .size:=0D endstruc=0D =0D +%macro CALL_RDI 1=0D +=0D + mov rdi, %%ReturnAddress=0D + jmp %1=0D +%%ReturnAddress:=0D +=0D +%endmacro=0D +=0D ;=0D ; @todo: The strong/weak implementation does not work.=0D ; This needs to be reviewed later.=0D @@ -116,8 +124,7 @@ ASM_PFX(LoadMicrocodeDefault): ; Inputs:=0D ; rcx -> LoadMicrocodeParams pointer=0D ; Register Usage:=0D - ; rsp Preserved=0D - ; All others destroyed=0D + ; All are destroyed=0D ; Assumptions:=0D ; No memory available, stack is hard-coded and used for return addres= s=0D ; Executed by SBSP and NBSP=0D @@ -420,10 +427,6 @@ ASM_PFX(TempRamInitApi): ENABLE_SSE=0D ENABLE_AVX=0D ;=0D - ; Save Input Parameter in YMM10=0D - ;=0D - SAVE_RCX=0D - ;=0D ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6=0D ;=0D SAVE_REGS=0D @@ -433,6 +436,22 @@ ASM_PFX(TempRamInitApi): ;=0D SAVE_BFV rbp=0D =0D + ;=0D + ; Save Input Parameter in YMM10=0D + ;=0D + cmp rcx, 0=0D + jnz ParamValid=0D +=0D + ;=0D + ; Fall back to default UPD=0D + ;=0D + CALL_RDI ASM_PFX(AsmGetFspInfoHeaderNoStack)=0D + xor rcx, rcx=0D + mov ecx, DWORD [rax + 01Ch] ; Read FsptImageBaseAddress=0D + add ecx, DWORD [rax + 024h] ; Get Cfg Region base address = =3D FsptImageBaseAddress + CfgRegionOffset=0D +ParamValid:=0D + SAVE_RCX=0D +=0D ;=0D ; Save timestamp into YMM6=0D ;=0D @@ -441,13 +460,6 @@ ASM_PFX(TempRamInitApi): or rax, rdx=0D SAVE_TS rax=0D =0D - ;=0D - ; Check Parameter=0D - ;=0D - cmp rcx, 0=0D - mov rcx, 08000000000000002h=0D - jz TempRamInitExit=0D -=0D ;=0D ; Sec Platform Init=0D ;=0D --=20 2.35.0.windows.1