From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web09.3032.1668497570242201641 for ; Mon, 14 Nov 2022 23:32:50 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="unable to parse pub key" header.i=@intel.com header.s=intel header.b=bEVFVqZN; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: jackx.lin@intel.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668497570; x=1700033570; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=NF/32U2QE4KfHFtHahKZf+xBbPpCNr/O4O4aWS1AnDg=; b=bEVFVqZNo7g0Ry4BVseSvFpjwg21Ko5i6P9bBSTBC5R6u90K+1FkMvIj LxBI8EMkFYAzlhsxDbzlmRMLyUXMvYlU6qsKYRGp9AmndK6CnlIWdmkw+ pClkgU3pC8r9HXAHpkjrHqD2JUgvZCPZYPN8nxDD2cm8gkXCRBwUa3COC zOLE9dOCkksHtNxhpTGeJVUErounKSLD/KOD3RXONwOblrB3ziCBwSNmv ulmmnfdja8yVVt+mhyRXagPa99M7b8FnUuEcXXLOHobxqXWHtuVfjI62w 1p3ggdj9DDymc8jqY4D+d9CpY/6y9MYx+9011mndEV9F2/qzTuQQlQDy6 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10531"; a="338981521" X-IronPort-AV: E=Sophos;i="5.96,165,1665471600"; d="scan'208";a="338981521" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2022 23:32:49 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10531"; a="638846056" X-IronPort-AV: E=Sophos;i="5.96,165,1665471600"; d="scan'208";a="638846056" Received: from lins2x-desk1.gar.corp.intel.com ([10.225.33.149]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2022 23:32:47 -0800 From: "JackX Lin" To: devel@edk2.groups.io Cc: JackX Lin , JackX Lin , Dong Guo , Ray Ni , Donald Kuo , Jiewen Yao , Rangasai V Chaganty , Chandana C Kumar Subject: [edk2-platforms:PATCH] BIOS needs to present cores in order of relative performance in MADT Date: Tue, 15 Nov 2022 15:32:27 +0800 Message-Id: <20221115073227.305-1-jackx.lin@intel.com> X-Mailer: git-send-email 2.32.0.windows.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit BIOS should keep MADT ordering by big core first then small core Signed-off-by: JackX Lin Cc: Dong Guo Cc: Ray Ni Cc: Donald Kuo Cc: Jiewen Yao Cc: Rangasai V Chaganty Cc: Chandana C Kumar Cc: JackX Lin --- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 149 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 142 insertions(+), 7 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c index 6e57b638e0..02c1dd3a91 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c @@ -18,6 +18,7 @@ typedef struct { UINT32 Flags; UINT32 SocketNum; UINT32 Thread; + BOOLEAN IsBigCore; } EFI_CPU_ID_ORDER_MAP; // @@ -131,6 +132,104 @@ AppendCpuMapTableEntry ( } +/** + Detect if Hetero Core is supported. + + @retval TRUE - Processor support HeteroCore + @retval FALSE - Processor doesnt support HeteroCore +**/ +BOOLEAN +EFIAPI +IsHeteroCoreSupported ( + VOID + ) +{ + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx; + + /// + /// Check Hetero feature is supported + /// with CPUID.(EAX=7,ECX=0):EDX[15]=1 + /// + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, NULL, NULL, &Edx.Uint32); + if (Edx.Bits.Hybrid == 1) { + return TRUE; + } + return FALSE; +} + +/** + Detect the type of core, whether it is Big/Small Core. + + @param[out] CoreType Output pointer that get CPUID_NATIVE_MODEL_ID_INFO data + 10h - Quark + 20h - Atom + 30H - Knights + 40H - Core +**/ +VOID +EFIAPI +GetCoreType ( + OUT UINT8 *CoreType + ) +{ + UINT32 Eax; + + if (IsHeteroCoreSupported ()) { + // + // Check which is the running core by reading CPUID.(EAX=1AH, ECX=00H):EAX + // + AsmCpuid (CPUID_HYBRID_INFORMATION, &Eax, NULL, NULL, NULL); + *CoreType = (UINT8)((Eax & 0xFF000000) >> 24); + } else { + *CoreType = CPUID_CORE_TYPE_INTEL_CORE; + } +} + +/** + Function will go through all processors to identify Core or Atom + by checking Core Type and update in IsBigCore. + + @param[in] CpuApicIdOrderTable Point to a buffer which will be filled in Core type information. +**/ +VOID +STATIC +EFIAPI +CollectCpuCoreType ( + IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable + ) +{ + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx; + UINT32 Eax; + UINTN ApNumber; + EFI_STATUS Status; + UINT8 CoreType; + + Status = mMpService->WhoAmI ( + mMpService, + &ApNumber + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Check Hetero feature is supported + /// with CPUID.(EAX=7,ECX=0):EDX[15]=1 + /// + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, NULL, NULL, &Edx.Uint32); + if (Edx.Bits.Hybrid == 1) { + // + // Check which is the running core by reading CPUID.(EAX=1AH, ECX=00H):EAX + // + AsmCpuid (CPUID_HYBRID_INFORMATION, &Eax, NULL, NULL, NULL); + CoreType = (UINT8) ((Eax & 0xFF000000) >> 24); + } else { + CoreType = CPUID_CORE_TYPE_INTEL_CORE; + } + + if (CoreType == CPUID_CORE_TYPE_INTEL_CORE) { + CpuApicIdOrderTable[ApNumber].IsBigCore = TRUE; + } +} + /** Collect all processors information and create a Cpu Apic Id table. @@ -138,7 +237,7 @@ AppendCpuMapTableEntry ( **/ EFI_STATUS CreateCpuLocalApicInTable ( - IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable + IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable ) { EFI_STATUS Status; @@ -146,9 +245,24 @@ CreateCpuLocalApicInTable ( UINT32 Index; UINT32 CurrProcessor; EFI_CPU_ID_ORDER_MAP *CpuIdMapPtr; + EFI_CPU_ID_ORDER_MAP *TempCpuApicIdOrderTable; UINT32 Socket; - Status = EFI_SUCCESS; + TempCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_ID_ORDER_MAP)); + if (TempCpuApicIdOrderTable == NULL) { + return EFI_UNSUPPORTED; + } + + CollectCpuCoreType (TempCpuApicIdOrderTable); + mMpService->StartupAllAPs ( + mMpService, // This + (EFI_AP_PROCEDURE) CollectCpuCoreType, // Procedure + TRUE, // SingleThread + NULL, // WaitEvent + 0, // TimeoutInMicrosecsond + TempCpuApicIdOrderTable, // ProcedureArgument + NULL // FailedCpuList + ); for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++, Index++) { Status = mMpService->GetProcessorInfo ( @@ -157,9 +271,9 @@ CreateCpuLocalApicInTable ( &ProcessorInfoBuffer ); - CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *) &CpuApicIdOrderTable[Index]; + CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *) &TempCpuApicIdOrderTable[Index]; if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0) { - CpuIdMapPtr->ApicId = (UINT32)ProcessorInfoBuffer.ProcessorId; + CpuIdMapPtr->ApicId = (UINT32) ProcessorInfoBuffer.ProcessorId; CpuIdMapPtr->Thread = ProcessorInfoBuffer.Location.Thread; CpuIdMapPtr->Flags = ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0); CpuIdMapPtr->SocketNum = ProcessorInfoBuffer.Location.Package; @@ -184,22 +298,43 @@ CreateCpuLocalApicInTable ( // DEBUG ((DEBUG_INFO, "BspApicId - 0x%x\n", GetApicId ())); - // // Fill in AcpiProcessorUid. // for (Socket = 0; Socket < FixedPcdGet32 (PcdMaxCpuSocketCount); Socket++) { for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) { - if (CpuApicIdOrderTable[CurrProcessor].Flags && (CpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) { - CpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid = (CpuApicIdOrderTable[CurrProcessor].SocketNum << mNumOfBitShift) + Index; + if (TempCpuApicIdOrderTable[CurrProcessor].Flags && (TempCpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) { + TempCpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid = (TempCpuApicIdOrderTable[CurrProcessor].SocketNum << mNumOfBitShift) + Index; Index++; } } } + // + // Re-ordering Cpu cores information to CpuApicIdOrderTable + // by big core first, then small core. + // + for (Index = 0, CurrProcessor = 0; Index < mNumberOfCpus; Index++) { + if (TempCpuApicIdOrderTable[Index].IsBigCore) { + CopyMem (&CpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); + CurrProcessor++; + } + } + + for (Index = 0; Index < mNumberOfCpus; Index++) { + if (!(TempCpuApicIdOrderTable[Index].IsBigCore)) { + CopyMem (&CpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); + CurrProcessor++; + } + } + DEBUG ((DEBUG_INFO, "::ACPI:: APIC ID Order Table Init. mNumOfBitShift = %x\n", mNumOfBitShift)); DebugDisplayReOrderTable (CpuApicIdOrderTable); + if (TempCpuApicIdOrderTable != NULL) { + FreePool (TempCpuApicIdOrderTable); + } + return Status; } -- 2.32.0.windows.2