From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f179.google.com (mail-pg1-f179.google.com [209.85.215.179]) by mx.groups.io with SMTP id smtpd.web10.132056.1671108996551968216 for ; Thu, 15 Dec 2022 04:56:36 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@ventanamicro.com header.s=google header.b=J2NnpoM4; spf=pass (domain: ventanamicro.com, ip: 209.85.215.179, mailfrom: sunilvl@ventanamicro.com) Received: by mail-pg1-f179.google.com with SMTP id w37so4100556pga.5 for ; Thu, 15 Dec 2022 04:56:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=g2W6jb99cFFSOxlWisS0qP1Ln33E9VDPHD3kG8VCrFk=; b=J2NnpoM4CwSetPS83WWrAa/OFWqZNzg0U2eLBVZscFJ4wR9V5u2PaQoXfThZFZPCJg g9NK6WYeJWWeSnTLusawF/53sC7zm6ubd4ui08h/bge/C6bHlemF9izSogZKyq0hjokm 2O7x6VKZgS/X75c94Bv50iUyXxvs8qh5ImR59PjiKFwqkVYM0R6EBEqVuv4C8+7HNtlK Pz8p5ofEpimrbu5g97E/tyhLwmjhsJ5wof5L+wxkFel9feq10gDN5cyby67xDPArINxQ Pi5ALhVF1Aj6Ln7xdwbm9bQDSHkMLE85ZnujT8Zg+EbpLScKmZ5FB5ozHEkVcsLeb6XT P5Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=g2W6jb99cFFSOxlWisS0qP1Ln33E9VDPHD3kG8VCrFk=; b=ENT6yCaEXn8X+jFV520OTxXVmVKegPPDFlpEtJuywUp+VQ7J4KkM1UCMdj9lDgehMy 8jR3Dhd62iI5HSl6zgdXVsvgzbyKObSsBOsznkZU/Bsf6NJR+ExC6zfLBBcYtTRCXGC6 z1T0W+mcYHf7qflQ09RTusGDOWYTMEoKY4k/FMcWNl7whRRVYM7fZTZjBfr2V1o0F+K/ lVqwTR05BpufXnm0GFwfKRbSRm+jEh+9UMP4mrCQn4Mzk4ZC5RerotBI9FjQ+/0P9Bxy 2JPYVLrwol8b6WWDVfOFHBngD5k4Bg+nIXaDbyJ3GiEUbgz19+0ydXpVYgYOFzWHX6VI qWfw== X-Gm-Message-State: ANoB5pkB3xTw9WG0+amatpotnXoakf83dVdiVVSs/0K69vP+5XDQaKjJ EyeVo3OUd5MuJvwSLjNCaEHhif33GnBkFmfv/CKPlg== X-Google-Smtp-Source: AA0mqf4DBEbbSvYI5TBBbifuqPPKDIzP4t609+tRrwFyXNizK9ScSIoSvrfOlnyPzYFqxP/GCvVWcg== X-Received: by 2002:a62:1687:0:b0:574:e5aa:a8dd with SMTP id 129-20020a621687000000b00574e5aaa8ddmr27484338pfw.17.1671108995556; Thu, 15 Dec 2022 04:56:35 -0800 (PST) Return-Path: Received: from localhost.localdomain ([49.206.11.246]) by smtp.gmail.com with ESMTPSA id j2-20020a625502000000b005762905c89asm1674384pfb.66.2022.12.15.04.56.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Dec 2022 04:56:35 -0800 (PST) From: "Sunil V L" To: devel@edk2.groups.io Cc: Abner Chang , Daniel Schaefer , Michael D Kinney , Liming Gao , Zhiguang Liu , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Gerd Hoffmann , Rebecca Cran , Peter Grehan , Brijesh Singh , Erdem Aktas , James Bottomley , Min Xu , Tom Lendacky , Eric Dong , Ray Ni , Rahul Kumar , Leif Lindholm , Sami Mujawar , Andrew Fish , Jian J Wang , Anup Patel , Heinrich Schuchardt , Andrei Warkentin Subject: [edk2-staging/RiscV64QemuVirt PATCH V6 00/23] Add support for RISC-V virt machine Date: Thu, 15 Dec 2022 18:26:03 +0530 Message-Id: <20221215125626.545372-1-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.38.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add support for RISC-V qemu virt machine. Most of the changes are migrated from edk2-platforms repo and followed the latest guidelines for EDK2 code structuring. The series has passed all CI tests (https://github.com/tianocore/edk2/pull/3471) These changes are available at: https://github.com/vlsunil/edk2/tree/RiscV64QemuVirt Changes since V5: 1) Avoided editing the existing INF files (as per feedback from Ray Ni). This reduced several refactor patches. 2) Moved to PEI less design (as per suggestion from Andrei Warkentin). 3) Added PciCpuIo2Dxe driver in OvmfPkg. 4) Removed APRIORI requirement in DSC/FDF infrastructure files. Now they are very similar to ArmVirtQemu. 5) Addressed Heinrich's feedback. 6) Rebased and added the tags Changes since V4: 1) Rebased and added ACKs 2) Dropped few patches related to VirtNorFlashDxe since they are already taken care by Ard. Changes since V3: 1) Addressed Abner's comments 2) Changed folder name from Ia32_X64 to Ia32X64 as per latest guidelines. 2) Rebased Changes since V2: 1) Fixed issues detected by CI (https://github.com/tianocore/edk2/pull/3471) 2) Added an extra patch to fix up the consumers of NvVarStoreFormattedLib Changes since V1: 1) Added couple of patches from Ard to optimize the NorFlashDxe in Ovmf. Note: There will be a separate patch series in future to update existing consumers of NorFlashDxe driver. 2) Migrated NvVarStoreFormattedLib from EmbeddedPkg to MdeModulePkg 3) Created Null instance of the NorFlashPlatformLib library class 4) Moved NorFlashPlatformLib.h from ArmPlatformPkg Cc: Abner Chang Cc: Daniel Schaefer Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Rebecca Cran Cc: Peter Grehan Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Min Xu Cc: Tom Lendacky Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Leif Lindholm Cc: Sami Mujawar Cc: Andrew Fish Cc: Jian J Wang Cc: Anup Patel Cc: Heinrich Schuchardt Cc: Andrei Warkentin Sunil V L (23): MdePkg/Register: Add register definition header files for RISC-V MdePkg: Add RISCV_EFI_BOOT_PROTOCOL related definitions MdePkg/BaseLib: RISC-V: Add few more helper functions MdePkg: Add BaseRiscVSbiLib Library for RISC-V UefiCpuPkg: Add CpuTimerDxe module UefiCpuPkg/CpuExceptionHandlerLib: Add RISC-V instance UefiCpuPkg/CpuDxe: Add RISC-V instance UefiCpuPkg/CpuTimerLib: Add RISC-V instance UefiCpuPkg/UefiCpuPkg.ci.yaml: Ignore RISC-V file EmbeddedPkg: Enable PcdPrePiCpuIoSize for RISC-V EmbeddedPkg/NvVarStoreFormattedLib: Migrate to MdeModulePkg ArmVirtPkg: Update the references to NvVarStoreFormattedLib ArmVirtPkg/PlatformHasAcpiDtDxe: Move to OvmfPkg ArmVirtPkg: Fix up the location of PlatformHasAcpiDtDxe OvmfPkg: Add VirtNorFlashPlatformLib library OvmfPkg/PlatformInitLib: Add RISC-V instance OvmfPkg: Add PrePiHobListPointerLib library OvmfPkg: Add PciCpuIo2Dxe driver OvmfPkg/ResetSystemLib: Add RISC-V instance OvmfPkg/Sec: Add RISC-V SEC module OvmfPkg/PlatformBootManagerLib: Add RISC-V instance OvmfPkg: RiscVVirt: Add Qemu Virt platform support Maintainers.txt: Add entry for OvmfPkg/RiscVVirt ArmVirtPkg/ArmVirtPkg.dec | 9 - EmbeddedPkg/EmbeddedPkg.dec | 6 +- MdeModulePkg/MdeModulePkg.dec | 3 + MdePkg/MdePkg.dec | 9 + OvmfPkg/OvmfPkg.dec | 11 + OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 338 ++++++ ArmVirtPkg/ArmVirtCloudHv.dsc | 2 +- ArmVirtPkg/ArmVirtKvmTool.dsc | 2 +- ArmVirtPkg/ArmVirtQemu.dsc | 6 +- ArmVirtPkg/ArmVirtQemuKernel.dsc | 4 +- MdeModulePkg/MdeModulePkg.dsc | 2 + MdePkg/MdePkg.dsc | 3 + OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 510 +++++++++ UefiCpuPkg/UefiCpuPkg.dsc | 6 + OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 306 ++++++ ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf | 2 +- ArmVirtPkg/KvmtoolPlatformDxe/KvmtoolPlatformDxe.inf | 2 +- {EmbeddedPkg => MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf | 1 - MdePkg/Library/BaseLib/BaseLib.inf | 3 + MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf | 25 + OvmfPkg/Library/PlatformBootManagerLib/DxeRiscV64PlatformBootManagerLib.inf | 75 ++ OvmfPkg/Library/PlatformInitLib/BaseRiscV64PlatformInitLib.inf | 51 + OvmfPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf | 23 + OvmfPkg/Library/ResetSystemLib/BaseRiscV64ResetSystemLib.inf | 38 + OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf | 40 + OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf | 30 + OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.inf | 48 + {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf | 3 +- OvmfPkg/Sec/SecMainRiscV64.inf | 58 ++ UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf | 68 ++ UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf | 51 + UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf | 42 + UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf | 32 + {EmbeddedPkg => MdeModulePkg}/Include/Guid/NvVarStoreFormatted.h | 0 MdePkg/Include/Library/BaseLib.h | 50 + MdePkg/Include/Library/BaseRiscVSbiLib.h | 127 +++ MdePkg/Include/Protocol/RiscVBootProtocol.h | 34 + MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 119 +++ MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 + OvmfPkg/Include/Library/PlatformInitLib.h | 39 + OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.h | 45 + OvmfPkg/Sec/RiscV64/SecMain.h | 63 ++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h | 199 ++++ UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h | 177 ++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h | 116 +++ {EmbeddedPkg => MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c | 0 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c | 227 +++++ OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.c | 1078 ++++++++++++++++++++ OvmfPkg/Library/PlatformBootManagerLib/RiscV64/QemuKernel.c | 77 ++ OvmfPkg/Library/PlatformInitLib/RiscV64/Cpu.c | 33 + OvmfPkg/Library/PlatformInitLib/RiscV64/Memory.c | 263 +++++ OvmfPkg/Library/PlatformInitLib/RiscV64/Platform.c | 83 ++ OvmfPkg/Library/PrePiHobListPointerLib/RiscV64/PrePiHobListPointer.c | 65 ++ OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c | 20 + OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c | 128 +++ OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.c | 136 +++ OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c | 40 + OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.c | 557 ++++++++++ {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c | 0 OvmfPkg/Sec/RiscV64/SecMain.c | 104 ++ UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c | 365 +++++++ UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c | 294 ++++++ UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c | 133 +++ UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c | 199 ++++ ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 2 +- Maintainers.txt | 4 + MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 + MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 23 + MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 +- MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 23 + OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc | 41 + OvmfPkg/RiscVVirt/VarStore.fdf.inc | 79 ++ OvmfPkg/Sec/RiscV64/SecEntry.S | 21 + UefiCpuPkg/CpuTimerDxe/CpuTimer.uni | 14 + UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni | 12 + UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S | 105 ++ UefiCpuPkg/UefiCpuPkg.ci.yaml | 1 + 77 files changed, 6985 insertions(+), 29 deletions(-) create mode 100644 OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc create mode 100644 OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc create mode 100644 OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf rename {EmbeddedPkg => MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.inf (96%) create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.inf create mode 100644 OvmfPkg/Library/PlatformBootManagerLib/DxeRiscV64PlatformBootManagerLib.inf create mode 100644 OvmfPkg/Library/PlatformInitLib/BaseRiscV64PlatformInitLib.inf create mode 100644 OvmfPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf create mode 100644 OvmfPkg/Library/ResetSystemLib/BaseRiscV64ResetSystemLib.inf create mode 100644 OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.inf create mode 100644 OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.inf create mode 100644 OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.inf rename {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.inf (89%) create mode 100644 OvmfPkg/Sec/SecMainRiscV64.inf create mode 100644 UefiCpuPkg/CpuDxe/CpuDxeRiscV64.inf create mode 100644 UefiCpuPkg/CpuTimerDxe/CpuTimerDxe.inf create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/BaseRiscV64CpuExceptionHandlerLib.inf create mode 100644 UefiCpuPkg/Library/CpuTimerLib/BaseRiscV64CpuTimerLib.inf rename {EmbeddedPkg => MdeModulePkg}/Include/Guid/NvVarStoreFormatted.h (100%) create mode 100644 MdePkg/Include/Library/BaseRiscVSbiLib.h create mode 100644 MdePkg/Include/Protocol/RiscVBootProtocol.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h create mode 100644 OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.h create mode 100644 OvmfPkg/Sec/RiscV64/SecMain.h create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.h create mode 100644 UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.h create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.h rename {EmbeddedPkg => MdeModulePkg}/Library/NvVarStoreFormattedLib/NvVarStoreFormattedLib.c (100%) create mode 100644 MdePkg/Library/BaseRiscVSbiLib/BaseRiscVSbiLib.c create mode 100644 OvmfPkg/Library/PlatformBootManagerLib/RiscV64/PlatformBm.c create mode 100644 OvmfPkg/Library/PlatformBootManagerLib/RiscV64/QemuKernel.c create mode 100644 OvmfPkg/Library/PlatformInitLib/RiscV64/Cpu.c create mode 100644 OvmfPkg/Library/PlatformInitLib/RiscV64/Memory.c create mode 100644 OvmfPkg/Library/PlatformInitLib/RiscV64/Platform.c create mode 100644 OvmfPkg/Library/PrePiHobListPointerLib/RiscV64/PrePiHobListPointer.c create mode 100644 OvmfPkg/Library/ResetSystemLib/RiscV64/DxeResetShutdown.c create mode 100644 OvmfPkg/Library/ResetSystemLib/RiscV64/ResetSystemLib.c create mode 100644 OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashDeviceTreeLib.c create mode 100644 OvmfPkg/Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c create mode 100644 OvmfPkg/PciCpuIo2Dxe/PciCpuIo2Dxe.c rename {ArmVirtPkg => OvmfPkg}/PlatformHasAcpiDtDxe/PlatformHasAcpiDtDxe.c (100%) create mode 100644 OvmfPkg/Sec/RiscV64/SecMain.c create mode 100644 UefiCpuPkg/CpuDxe/RiscV64/CpuDxe.c create mode 100644 UefiCpuPkg/CpuTimerDxe/RiscV64/Timer.c create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/CpuExceptionHandlerLib.c create mode 100644 UefiCpuPkg/Library/CpuTimerLib/RiscV64/CpuTimerLib.c create mode 100644 MdePkg/Library/BaseLib/RiscV64/CpuScratch.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S create mode 100644 MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S create mode 100644 OvmfPkg/RiscVVirt/RiscVVirt.fdf.inc create mode 100644 OvmfPkg/RiscVVirt/VarStore.fdf.inc create mode 100644 OvmfPkg/Sec/RiscV64/SecEntry.S create mode 100644 UefiCpuPkg/CpuTimerDxe/CpuTimer.uni create mode 100644 UefiCpuPkg/CpuTimerDxe/CpuTimerExtra.uni create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/RiscV64/SupervisorTrapHandler.S -- 2.38.0